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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:42 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:42 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v5 14/42] UefiCpuPkg/CpuExceptionHandler: Add support for MSR_PROT NAE events Date: Mon, 2 Mar 2020 17:06:45 -0600 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: FvLn9vhkQslnE/RGGQPTf4nERwUaHfxTiSR62fTqbn8lqhEUJ45l43RLgHY44TRlZ9X8g0n3b8VMT3GVECUdWC2rbrkk5QyHtgwvs6wEOAf9Unn0OVHD4i8snzJlyHTPUWYnz8gw36J232V44GGCmORl2imyDCWAGLYSNCBnPSklAJSsqtPVWC0K/PzqIYpNeJvGJGHulbdVvDFFjP1AJhcJc+h3TZT+7loUHh0XY+Uu2NuBqGSLUfwcrB26b6T6hCgxSVJM6fm5ASacmCqP9peIOF3iPhoqKFTguw/ZTjoO35Djvx199fpdY88c56dVd9xfITE/aBt5PQARSOxyVjaopi72ca9APYbtmPsBdmnwQeMcQGx/HhWa+gxtuf6G/kZnX8dLIf1fy/s1P96P6yaHKiNg42wNdwIvMl/sqlhx5Pq+igtkqNy0avBW5taH1zlEgBVkStQapVxMKe4LQW4beWg6B5CWm/DwE12l7sgpKyPrQh4HeRD6lpe5tyNpA87gvehWyYuG5lzxdHonIA== X-MS-Exchange-AntiSpam-MessageData: nThcIdjoYcBPGDfI16vonF44uRYJQl2cAft0uHlHmqLtMEHK9aRjej+0/UI2qEsJWnehDH2WDbs8cbFQK5cRzA9HQX4nDr0l0QIbt1wCn0Xmt1bk7Uro9WSs6/zEFVjkmCEOaq4DHHuCT+CzX/raAA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0f5bfab-fc2a-4acc-8b7c-08d7befe82fd X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:42.7078 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: n4onTP5SCDTBmCbq48/4rMnBhwUYml+EywvUuN3HFO1d9EVRvg0903Q6rnygRjavdFhiaZ/PznspLv94p3mUvg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support an MSR_PROT NAE event. Parse the instruction that generated the #VC exception to determine whether it is RDMSR or WRMSR, setting the required register register values in the GHCB and creating the proper SW_EXIT_INFO1 value in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 970ee8752253..6f91cfff5fc8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -294,6 +294,51 @@ UnsupportedExit ( return Status; } +STATIC +UINT64 +MsrExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 = 0; + + switch (*(InstructionData->OpCodes + 1)) { + case 0x30: // WRMSR + ExitInfo1 = 1; + Ghcb->SaveArea.Rax = Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rdx = Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + /* Fallthrough */ + case 0x32: // RDMSR + Ghcb->SaveArea.Rcx = Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + break; + default: + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + Status = VmgExit (Ghcb, SvmExitMsr, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (!ExitInfo1) { + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rdx = Ghcb->SaveArea.Rdx; + } + + return 0; +} + #define IOIO_TYPE_STR (1 << 2) #define IOIO_TYPE_IN 1 #define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) @@ -558,6 +603,10 @@ DoVcCommon ( NaeExit = IoioExit; break; + case SvmExitMsr: + NaeExit = MsrExit; + break; + default: NaeExit = UnsupportedExit; } -- 2.17.1