From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CD4E781EFA for ; Wed, 16 Nov 2016 07:53:25 -0800 (PST) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 388BE67BA3; Wed, 16 Nov 2016 15:53:30 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-80.phx2.redhat.com [10.3.116.80]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAGFrR8w024105; Wed, 16 Nov 2016 10:53:28 -0500 To: "Yao, Jiewen" , "Fan, Jeff" , "edk2-devel@lists.01.org" References: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386CF501@shsmsx102.ccr.corp.intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4A2DAC96@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386CF65D@shsmsx102.ccr.corp.intel.com> <437279e7-879f-af4f-03d8-babdd3576e84@redhat.com> Cc: "Kinney, Michael D" , Paolo Bonzini , "Tian, Feng" , "Zeng, Star" From: Laszlo Ersek Message-ID: Date: Wed, 16 Nov 2016 16:53:27 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <437279e7-879f-af4f-03d8-babdd3576e84@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Wed, 16 Nov 2016 15:53:30 +0000 (UTC) Subject: Re: [PATCH V3 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Nov 2016 15:53:25 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 11/15/16 03:47, Laszlo Ersek wrote: > On 11/11/16 13:59, Laszlo Ersek wrote: >> On 11/11/16 13:53, Yao, Jiewen wrote: >>> Sorry, I did not explain it clear enough before. >>> >>> Jeff is right. The NX fix is introduced in this patch series. >>> The reason is that when we update page table to protect the SMRAM, we would like enable the protection as early as possible. >>> We moved the NX enabling code from C function to ASM function to achieve that. >>> >>> You can see my GIT message in 5/6. >>> ============== >>> The XD enabling code is moved to SmiEntry to let NX take effect. >>> ============== >>> >>> Unfortunately, I introduced a bug there. You help to catch it and now I fix it. >>> It is not related to current code. >>> >>> What about your idea? >> >> Right, I missed that the XD handling in SmiEntry.nasm was brand new code >> added by this series. So, the current structure of both series should be >> fine; I should be able to start testing them (hopefully) soon. > > Jeff's v2 series was fine, and it is now committed (see > ). > > However, in order to test it successfully with OVMF, I needed the > patches linked in . > I intend to test this v3 series too with those (QEMU and OVMF) patches > applied. I hope I can get to it tomorrow or so. (1) I tested this series as fetched from Jiewen's public SmmProtection_V3_Rebase branch (which is based on current master, ec8a38770090 "UefiCpuPkg/PiSmmCpuDxeSmm: Decrease mNumberToFinish in AP safe code"), *plus* I applied the QEMU and OVMF patches listed in and . series OVMF VCPU boot S3 resume # applied platform PcdCpuMaxLogicalProcessorNumber PcdCpuSmmStaticPageTable topology result result -- ------- -------- ------------------------------- ------------------------ -------- ------ --------- 1 no Ia32 64 n/a 1x2x2 pass pass 4 no Ia32X64 64 n/a 1x2x2 pass pass 7 v3 Ia32 64 FALSE 1x2x2 pass pass (40 cycles) 8 v3 Ia32 64 TRUE 1x2x2 pass pass (40 cycles) 13 v3 Ia32X64 64 FALSE 1x2x2 pass pass (40 cycles) 14 v3 Ia32X64 64 TRUE 1x2x2 pass pass (40 cycles) For patches #1 through #5: Tested-by: Laszlo Ersek (2) Jiewen, after this series is reviewed and you commit it, can you please submit an OvmfPkg patch for addressing the following messages in the log: > SMM !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!! For that, I believe we need a patch similar to: commit ddd89cd50dd3a989e58a75ed38011168e3ec0954 Author: Ard Biesheuvel Date: Wed Sep 30 08:53:00 2015 +0000 OvmfPkg: set 4 KB section alignment for DXE_RUNTIME_DRIVER modules Increase the section alignment to 4 KB for DXE_RUNTIME_DRIVER modules. This allows the OS to map them with tightened permissions (i.e., R-X for .text and RW- for .data). This is a prerequisite for enabling the EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA (sic) feature that was introduced in UEFIv2.5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek Reviewed-by: Jordan Justen Tested-by: Laszlo Ersek git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18564 6f19259b-4bc3-4df7-8a09-765794883524 just that it should be for DXE_SMM_DRIVER and for SMM_CORE. ... Basically, please submit patch #6 for OvmfPkg as well. (I can test that too for you, but I prefer to see this series committed first, so this patch should be separate.) Thank you, Laszlo