[PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno

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* [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno
@ 2022-04-27 14:59 PierreGondois
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology PierreGondois
                   ` (4 more replies)
  0 siblings, 5 replies; 12+ messages in thread
From: PierreGondois @ 2022-04-27 14:59 UTC (permalink / raw)
  To: devel; +Cc: Ard Biesheuvel, Sami Mujawar

From: Pierre Gondois <pierre.gondois@arm.com>

DEPENDENCY:
This patch set relies on a fix sent at:
https://edk2.groups.io/g/devel/message/89348

The DynamicTablesPkg can now generate the AML description of the
PCI/CPU topology information. Use these new features and remove
the static ASL description of the PCI/CPU topology when the
DynamicTables are used (i.e. when -D DYNAMIC_TABLES_FRAMEWORK is
provided).

Also provide a small fix for debug printing.

Pierre Gondois (3):
  Platform/ARM: Juno: Generate ASL description of CPU topology
  Platform/ARM: Juno: Print debug values in right order
  Platform/ARM: Juno: Generate ASL description of a PCIe bus

 .../AslTables/Dsdt.asl                        | 198 --------
 .../AslTables/SsdtPci.asl                     | 195 --------
 .../ConfigurationManager.c                    | 425 +++++++++++++++++-
 .../ConfigurationManager.h                    |  47 +-
 .../ConfigurationManagerDxe.inf               |   1 -
 5 files changed, 456 insertions(+), 410 deletions(-)
 delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl

-- 
2.25.1


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology
  2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
@ 2022-04-27 14:59 ` PierreGondois
  2022-07-18 13:25   ` Sami Mujawar
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order PierreGondois
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 12+ messages in thread
From: PierreGondois @ 2022-04-27 14:59 UTC (permalink / raw)
  To: devel; +Cc: Ard Biesheuvel, Sami Mujawar

From: Pierre Gondois <Pierre.Gondois@arm.com>

The Dynamic Tables Framework has been updated to add support for
generating an ASL description of a CPU topology and its _LPI states.
This patch:
 - Describes the _LPI states in the Configuration Manager of the Juno
 - Add the generation of a new SSDT table describing the CPU topology
   and its _LPI states
 - Removes the CPU topology description of the DSDT table

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
 .../AslTables/Dsdt.asl                        | 198 ------------------
 .../ConfigurationManager.c                    | 196 ++++++++++++++++-
 .../ConfigurationManager.h                    |  20 +-
 3 files changed, 206 insertions(+), 208 deletions(-)

diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
index 63c70c1e4f06..2270b517cd12 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
@@ -33,204 +33,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
       }
       Return (Arg3)
     }
-    Device (CLU0) { // Cluster0 state
-      Name(_HID, "ACPI0010")
-      Name(_UID, 1)
-      Name (_LPI, Package() {
-        0, // Version
-        0, // Level Index
-        1, // Count
-        Package() { // Power Gating state for Cluster
-          2500, // Min residency (uS)
-          1150, // Wake latency (uS)
-          1, // Flags
-          1, // Arch Context Flags
-          100, //Residency Counter Frequency
-          0, // No Parent State
-          0x01000000, // Integer Entry method
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "CluPwrDn"
-        },
-      })
-      Name(PLPI, Package() {
-        0, // Version
-        0, // Level Index
-        2, // Count
-        Package() { // WFI for CPU
-          1, // Min residency (uS)
-          1, // Wake latency (uS)
-          1, // Flags
-          0, // Arch Context Flags
-          100, //Residency Counter Frequency
-          0, // No parent state
-          ResourceTemplate () {
-            // Register Entry method
-            Register (FFixedHW,
-              0x20,               // Bit Width
-              0x00,               // Bit Offset
-              0xFFFFFFFF,         // Address
-              0x03,               // Access Size
-              )
-          },
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "WFI",
-        },
-        Package() { // Power Gating state for CPU
-          150, // Min residency (uS)
-          350, // Wake latency (uS)
-          1, // Flags
-          1, // Arch Context Flags
-          100, //Residency Counter Frequency
-          1, // Parent node can be in any state
-          ResourceTemplate () {
-            // Register Entry method
-            Register (FFixedHW,
-              0x20,               // Bit Width
-              0x00,               // Bit Offset
-              0x00010000,         // Address
-              0x03,               // Access Size
-              )
-          },
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "CorePwrDn"
-        },
-      })
-      Device(CPU0) { // A57-0: Cluster 0, Cpu 0
-        Name(_HID, "ACPI0007")
-        Name(_UID, 0)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-      Device(CPU1) { // A57-1: Cluster 0, Cpu 1
-        Name(_HID, "ACPI0007")
-        Name(_UID, 1)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-    }
-    Device (CLU1) { // Cluster1 state
-      Name(_HID, "ACPI0010")
-      Name(_UID, 2)
-      Name (_LPI, Package() {
-        0, // Version
-        0, // Level Index
-        1, // Count
-        Package() { // Power Gating state for Cluster
-          2500, // Min residency (uS)
-          1150, // Wake latency (uS)
-          1, // Flags
-          1, // Arch Context Flags
-          100, //Residency Counter Frequency
-          0, // No Parent State
-          0x01000000, // Integer Entry method
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "CluPwrDn"
-        },
-      })
-      Name(PLPI, Package() {
-        0, // Version
-        0, // Level Index
-        2, // Count
-        Package() { // WFI for CPU
-          1, // Min residency (uS)
-          1, // Wake latency (uS)
-          1, // Flags
-          0, // Arch Context Flags
-          100, //Residency Counter Frequency
-          0, // No parent state
-          ResourceTemplate () {
-            // Register Entry method
-            Register (FFixedHW,
-              0x20,               // Bit Width
-              0x00,               // Bit Offset
-              0xFFFFFFFF,         // Address
-              0x03,               // Access Size
-              )
-          },
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "WFI",
-        },
-        Package() { // Power Gating state for CPU
-          150, // Min residency (uS)
-          350, // Wake latency (uS)
-          1, // Flags
-          1, // Arch Context Flags
-          100, //Residency Counter Frequency
-          1, // Parent node can be in any state
-          ResourceTemplate () {
-            // Register Entry method
-            Register (FFixedHW,
-              0x20,               // Bit Width
-              0x00,               // Bit Offset
-              0x00010000,         // Address
-              0x03,               // Access Size
-              )
-          },
-          ResourceTemplate() { // Null Residency Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          ResourceTemplate() { // Null Usage Counter
-            Register (SystemMemory, 0, 0, 0, 0)
-          },
-          "CorePwrDn"
-        },
-      })
-      Device(CPU2) { // A53-0: Cluster 1, Cpu 0
-        Name(_HID, "ACPI0007")
-        Name(_UID, 2)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-      Device(CPU3) { // A53-1: Cluster 1, Cpu 1
-        Name(_HID, "ACPI0007")
-        Name(_UID, 3)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-      Device(CPU4) { // A53-2: Cluster 1, Cpu 2
-        Name(_HID, "ACPI0007")
-        Name(_UID, 4)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-      Device(CPU5) { // A53-3: Cluster 1, Cpu 3
-        Name(_HID, "ACPI0007")
-        Name(_UID, 5)
-        Method (_LPI, 0, NotSerialized) {
-          return(PLPI)
-        }
-      }
-    }
 
     //
     // LAN9118 Ethernet
diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 8a0464c5f637..977aba5da5c4 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -1,7 +1,7 @@
 /** @file
   Configuration Manager Dxe
 
-  Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
+  Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -90,6 +90,14 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
       NULL
     },
+    // SSDT Table (Cpu topology)
+    {
+      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+      0, // Unused
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtCpuTopology),
+      NULL,
+      SIGNATURE_64 ('C','P','U','-','T','O','P','O')
+    },
     /* PCI MCFG Table
        PCIe is only available on Juno R1 and R2.
        Add the PCI table entries at the end of the table so that
@@ -277,6 +285,8 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       0,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      CM_NULL_TOKEN,
+      // CM_OBJECT_TOKEN  LpiToken
       CM_NULL_TOKEN
     },
     // 'big' cluster
@@ -298,7 +308,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       BIG_CLUSTER_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (BigClusterResources)
+      REFERENCE_TOKEN (BigClusterResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (ClustersLpiRef)
     },
     // 'LITTLE' cluster
     {
@@ -319,7 +331,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       LITTLE_CLUSTER_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (LittleClusterResources)
+      REFERENCE_TOKEN (LittleClusterResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (ClustersLpiRef)
     },
     // Two 'big' cores
     {
@@ -340,7 +354,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       BIG_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (BigCoreResources)
+      REFERENCE_TOKEN (BigCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     },
     {
       // CM_OBJECT_TOKEN  Token
@@ -360,7 +376,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       BIG_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (BigCoreResources)
+      REFERENCE_TOKEN (BigCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     },
     // Four 'LITTLE' cores
     {
@@ -381,7 +399,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       LITTLE_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (LittleCoreResources)
+      REFERENCE_TOKEN (LittleCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     },
     {
       // CM_OBJECT_TOKEN  Token
@@ -401,7 +421,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       LITTLE_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (LittleCoreResources)
+      REFERENCE_TOKEN (LittleCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     },
     {
       // CM_OBJECT_TOKEN  Token
@@ -421,7 +443,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       LITTLE_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (LittleCoreResources)
+      REFERENCE_TOKEN (LittleCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     },
     {
       // CM_OBJECT_TOKEN  Token
@@ -441,7 +465,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
       // UINT32  NoOfPrivateResources
       LITTLE_CORE_RESOURCE_COUNT,
       // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
-      REFERENCE_TOKEN (LittleCoreResources)
+      REFERENCE_TOKEN (LittleCoreResources),
+      // CM_OBJECT_TOKEN  LpiToken
+      REFERENCE_TOKEN (CoresLpiRef)
     }
   },
 
@@ -549,6 +575,84 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
   {
     { REFERENCE_TOKEN (CacheInfo[4]) }, // -> 'LITTLE' core's L1 I-cache
     { REFERENCE_TOKEN (CacheInfo[5]) }  // -> 'LITTLE' core's L1 D-cache
+  },
+
+  // Low Power Idle state information (LPI) for all cores/clusters
+  {
+    { // LpiInfo[0] -> Clusters CluPwrDn
+      2500,         // MinResidency
+      1150,         // WorstCaseWakeLatency
+      1,            // Flags
+      1,            // ArchFlags
+      100,          // ResCntFreq
+      0,            // EnableParentState
+      1,            // IsInteger
+      0x01000000,   // IntegerEntryMethod
+      // RegisterEntryMethod (NULL, use IntegerEntryMethod)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      // ResidencyCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      // UsageCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      "CluPwrDn" // StateName
+    },
+    // LpiInfo[1] -> Cores WFI
+    {
+      1,            // MinResidency
+      1,            // WorstCaseWakeLatency
+      1,            // Flags
+      0,            // ArchFlags
+      100,          // ResCntFreq
+      0,            // EnableParentState
+      0,            // IsInteger
+      0,            // IntegerEntryMethod (0, use RegisterEntryMethod)
+      // RegisterEntryMethod
+      {
+        EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE, // AddressSpaceId
+        0x20, // RegisterBitWidth
+        0x00, // RegisterBitOffset
+        0x03, // AccessSize
+        0xFFFFFFFF // Address
+      },
+      // ResidencyCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      // UsageCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      "WFI" // StateName
+    },
+    // LpiInfo[2] -> Cores CorePwrDn
+    {
+      150,          // MinResidency
+      350,          // WorstCaseWakeLatency
+      1,            // Flags
+      1,            // ArchFlags
+      100,          // ResCntFreq
+      1,            // EnableParentState
+      0,            // IsInteger
+      0,            // IntegerEntryMethod (0, use RegisterEntryMethod)
+      // RegisterEntryMethod
+      {
+          EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE, // AddressSpaceId
+          0x20, // RegisterBitWidth
+          0x00, // RegisterBitOffset
+          0x03, // AccessSize
+          0x00010000 // Address
+      },
+      // ResidencyCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      // UsageCounterRegister (NULL)
+      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
+      "CorePwrDn" // StateName
+    },
+  },
+  // Cluster Low Power Idle state references (LPI)
+  {
+    { REFERENCE_TOKEN (LpiInfo[0]) }
+  },
+  // Cores Low Power Idle state references (LPI)
+  {
+    { REFERENCE_TOKEN (LpiInfo[1]) },
+    { REFERENCE_TOKEN (LpiInfo[2]) },
   }
 };
 
@@ -809,6 +913,55 @@ GetGicCInfo (
   return EFI_NOT_FOUND;
 }
 
+/** Return Lpi State Infor.
+
+  @param [in]      This           Pointer to the Configuration Manager Protocol.
+  @param [in]      CmObjectId     The Object ID of the CM object requested
+  @param [in]      SearchToken    A unique token for identifying the requested
+                                  CM_ARM_LPI_INFO object.
+  @param [in, out] CmObject       Pointer to the Configuration Manager Object
+                                  descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS             Success.
+  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
+  @retval EFI_NOT_FOUND           The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetLpiInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINT32                            TotalObjCount;
+  UINT32                            ObjIndex;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  TotalObjCount = ARRAY_SIZE (PlatformRepo->LpiInfo);
+
+  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
+    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->LpiInfo[ObjIndex]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->LpiInfo[ObjIndex]);
+      CmObject->Data = (VOID*)&PlatformRepo->LpiInfo[ObjIndex];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
 /** Return a list of Configuration Manager object references pointed to by the
     given input token.
 
@@ -866,6 +1019,18 @@ GetCmObjRefs (
     CmObject->Count = ARRAY_SIZE (PlatformRepo->LittleCoreResources);
     return EFI_SUCCESS;
   }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->ClustersLpiRef) {
+    CmObject->Size = sizeof (PlatformRepo->ClustersLpiRef);
+    CmObject->Data = (VOID*)&PlatformRepo->ClustersLpiRef;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->ClustersLpiRef);
+    return EFI_SUCCESS;
+  }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CoresLpiRef) {
+    CmObject->Size = sizeof (PlatformRepo->CoresLpiRef);
+    CmObject->Data = (VOID*)&PlatformRepo->CoresLpiRef;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->CoresLpiRef);
+    return EFI_SUCCESS;
+  }
 
   return EFI_NOT_FOUND;
 }
@@ -1142,6 +1307,19 @@ GetArmNameSpaceObject (
       }
       break;
 
+    case EArmObjLpiInfo:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 NULL,
+                 0,
+                 0,
+                 Token,
+                 GetLpiInfo,
+                 CmObject
+                 );
+      break;
+
     default: {
       Status = EFI_NOT_FOUND;
       DEBUG ((
diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
index 771b00c31b9e..1bc242bc9d85 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -115,7 +115,7 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
 
 /** The number of ACPI tables to install
 */
-#define PLAT_ACPI_TABLE_COUNT   10
+#define PLAT_ACPI_TABLE_COUNT   11
 
 /** The number of platform generic timer blocks
 */
@@ -172,6 +172,15 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
 */
 #define LITTLE_CORE_RESOURCE_COUNT  2
 
+/** The number of Lpi states for the platform:
+    - two for the cores
+    - one for the clusters
+*/
+#define CORES_LPI_STATE_COUNT           2
+#define CLUSTERS_LPI_STATE_COUNT        1
+#define LPI_STATE_COUNT                 (CORES_LPI_STATE_COUNT +              \
+                                         CLUSTERS_LPI_STATE_COUNT)
+
 /** A structure describing the platform configuration
     manager repository information
 */
@@ -238,6 +247,15 @@ typedef struct PlatformRepositoryInfo {
   // 'LITTLE' core private resources
   CM_ARM_OBJ_REF                        LittleCoreResources[LITTLE_CORE_RESOURCE_COUNT];
 
+  // Low Power Idle state information (LPI) for all cores/clusters
+  CM_ARM_LPI_INFO                       LpiInfo[LPI_STATE_COUNT];
+
+  // Clusters Low Power Idle state references (LPI)
+  CM_ARM_OBJ_REF                        ClustersLpiRef[CLUSTERS_LPI_STATE_COUNT];
+
+  // Cores Low Power Idle state references (LPI)
+  CM_ARM_OBJ_REF                        CoresLpiRef[CORES_LPI_STATE_COUNT];
+
   /// Juno Board Revision
   UINT32                                JunoRevision;
 } EDKII_PLATFORM_REPOSITORY_INFO;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology PierreGondois
@ 2022-07-18 13:25   ` Sami Mujawar
  2022-07-18 13:30     ` PierreGondois
  0 siblings, 1 reply; 12+ messages in thread
From: Sami Mujawar @ 2022-07-18 13:25 UTC (permalink / raw)
  To: Pierre.Gondois, devel; +Cc: Ard Biesheuvel, nd

Hi Pierre,

Thank you for this patch.

Please find my response inline marked [SAMI].

Other than the comment below, these changes looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 27/04/2022 03:59 pm, Pierre.Gondois@arm.com wrote:
> From: Pierre Gondois <Pierre.Gondois@arm.com>
>
> The Dynamic Tables Framework has been updated to add support for
> generating an ASL description of a CPU topology and its _LPI states.
> This patch:
>   - Describes the _LPI states in the Configuration Manager of the Juno
>   - Add the generation of a new SSDT table describing the CPU topology
>     and its _LPI states
>   - Removes the CPU topology description of the DSDT table
>
> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
> ---
>   .../AslTables/Dsdt.asl                        | 198 ------------------
>   .../ConfigurationManager.c                    | 196 ++++++++++++++++-
>   .../ConfigurationManager.h                    |  20 +-
>   3 files changed, 206 insertions(+), 208 deletions(-)
>
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
> index 63c70c1e4f06..2270b517cd12 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
> @@ -33,204 +33,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
>         }
>         Return (Arg3)
>       }
> -    Device (CLU0) { // Cluster0 state
> -      Name(_HID, "ACPI0010")
> -      Name(_UID, 1)
> -      Name (_LPI, Package() {
> -        0, // Version
> -        0, // Level Index
> -        1, // Count
> -        Package() { // Power Gating state for Cluster
> -          2500, // Min residency (uS)
> -          1150, // Wake latency (uS)
> -          1, // Flags
> -          1, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          0, // No Parent State
> -          0x01000000, // Integer Entry method
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "CluPwrDn"
> -        },
> -      })
> -      Name(PLPI, Package() {
> -        0, // Version
> -        0, // Level Index
> -        2, // Count
> -        Package() { // WFI for CPU
> -          1, // Min residency (uS)
> -          1, // Wake latency (uS)
> -          1, // Flags
> -          0, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          0, // No parent state
> -          ResourceTemplate () {
> -            // Register Entry method
> -            Register (FFixedHW,
> -              0x20,               // Bit Width
> -              0x00,               // Bit Offset
> -              0xFFFFFFFF,         // Address
> -              0x03,               // Access Size
> -              )
> -          },
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "WFI",
> -        },
> -        Package() { // Power Gating state for CPU
> -          150, // Min residency (uS)
> -          350, // Wake latency (uS)
> -          1, // Flags
> -          1, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          1, // Parent node can be in any state
> -          ResourceTemplate () {
> -            // Register Entry method
> -            Register (FFixedHW,
> -              0x20,               // Bit Width
> -              0x00,               // Bit Offset
> -              0x00010000,         // Address
> -              0x03,               // Access Size
> -              )
> -          },
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "CorePwrDn"
> -        },
> -      })
> -      Device(CPU0) { // A57-0: Cluster 0, Cpu 0
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 0)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -      Device(CPU1) { // A57-1: Cluster 0, Cpu 1
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 1)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -    }
> -    Device (CLU1) { // Cluster1 state
> -      Name(_HID, "ACPI0010")
> -      Name(_UID, 2)
> -      Name (_LPI, Package() {
> -        0, // Version
> -        0, // Level Index
> -        1, // Count
> -        Package() { // Power Gating state for Cluster
> -          2500, // Min residency (uS)
> -          1150, // Wake latency (uS)
> -          1, // Flags
> -          1, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          0, // No Parent State
> -          0x01000000, // Integer Entry method
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "CluPwrDn"
> -        },
> -      })
> -      Name(PLPI, Package() {
> -        0, // Version
> -        0, // Level Index
> -        2, // Count
> -        Package() { // WFI for CPU
> -          1, // Min residency (uS)
> -          1, // Wake latency (uS)
> -          1, // Flags
> -          0, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          0, // No parent state
> -          ResourceTemplate () {
> -            // Register Entry method
> -            Register (FFixedHW,
> -              0x20,               // Bit Width
> -              0x00,               // Bit Offset
> -              0xFFFFFFFF,         // Address
> -              0x03,               // Access Size
> -              )
> -          },
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "WFI",
> -        },
> -        Package() { // Power Gating state for CPU
> -          150, // Min residency (uS)
> -          350, // Wake latency (uS)
> -          1, // Flags
> -          1, // Arch Context Flags
> -          100, //Residency Counter Frequency
> -          1, // Parent node can be in any state
> -          ResourceTemplate () {
> -            // Register Entry method
> -            Register (FFixedHW,
> -              0x20,               // Bit Width
> -              0x00,               // Bit Offset
> -              0x00010000,         // Address
> -              0x03,               // Access Size
> -              )
> -          },
> -          ResourceTemplate() { // Null Residency Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          ResourceTemplate() { // Null Usage Counter
> -            Register (SystemMemory, 0, 0, 0, 0)
> -          },
> -          "CorePwrDn"
> -        },
> -      })
> -      Device(CPU2) { // A53-0: Cluster 1, Cpu 0
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 2)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -      Device(CPU3) { // A53-1: Cluster 1, Cpu 1
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 3)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -      Device(CPU4) { // A53-2: Cluster 1, Cpu 2
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 4)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -      Device(CPU5) { // A53-3: Cluster 1, Cpu 3
> -        Name(_HID, "ACPI0007")
> -        Name(_UID, 5)
> -        Method (_LPI, 0, NotSerialized) {
> -          return(PLPI)
> -        }
> -      }
> -    }
>   
>       //
>       // LAN9118 Ethernet
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index 8a0464c5f637..977aba5da5c4 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -1,7 +1,7 @@
>   /** @file
>     Configuration Manager Dxe
>   
> -  Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
> +  Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>
>   
>     SPDX-License-Identifier: BSD-2-Clause-Patent
>   
> @@ -90,6 +90,14 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
>         NULL
>       },
> +    // SSDT Table (Cpu topology)
> +    {
> +      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
> +      0, // Unused
> +      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtCpuTopology),
> +      NULL,
> +      SIGNATURE_64 ('C','P','U','-','T','O','P','O')
> +    },
>       /* PCI MCFG Table
>          PCIe is only available on Juno R1 and R2.
>          Add the PCI table entries at the end of the table so that
> @@ -277,6 +285,8 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         0,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> +      CM_NULL_TOKEN,
> +      // CM_OBJECT_TOKEN  LpiToken
>         CM_NULL_TOKEN
>       },
>       // 'big' cluster
> @@ -298,7 +308,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         BIG_CLUSTER_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (BigClusterResources)
> +      REFERENCE_TOKEN (BigClusterResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (ClustersLpiRef)
>       },
>       // 'LITTLE' cluster
>       {
> @@ -319,7 +331,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         LITTLE_CLUSTER_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (LittleClusterResources)
> +      REFERENCE_TOKEN (LittleClusterResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (ClustersLpiRef)
>       },
>       // Two 'big' cores
>       {
> @@ -340,7 +354,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         BIG_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (BigCoreResources)
> +      REFERENCE_TOKEN (BigCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       },
>       {
>         // CM_OBJECT_TOKEN  Token
> @@ -360,7 +376,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         BIG_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (BigCoreResources)
> +      REFERENCE_TOKEN (BigCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       },
>       // Four 'LITTLE' cores
>       {
> @@ -381,7 +399,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         LITTLE_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (LittleCoreResources)
> +      REFERENCE_TOKEN (LittleCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       },
>       {
>         // CM_OBJECT_TOKEN  Token
> @@ -401,7 +421,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         LITTLE_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (LittleCoreResources)
> +      REFERENCE_TOKEN (LittleCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       },
>       {
>         // CM_OBJECT_TOKEN  Token
> @@ -421,7 +443,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         LITTLE_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (LittleCoreResources)
> +      REFERENCE_TOKEN (LittleCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       },
>       {
>         // CM_OBJECT_TOKEN  Token
> @@ -441,7 +465,9 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>         // UINT32  NoOfPrivateResources
>         LITTLE_CORE_RESOURCE_COUNT,
>         // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
> -      REFERENCE_TOKEN (LittleCoreResources)
> +      REFERENCE_TOKEN (LittleCoreResources),
> +      // CM_OBJECT_TOKEN  LpiToken
> +      REFERENCE_TOKEN (CoresLpiRef)
>       }
>     },
>   
> @@ -549,6 +575,84 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>     {
>       { REFERENCE_TOKEN (CacheInfo[4]) }, // -> 'LITTLE' core's L1 I-cache
>       { REFERENCE_TOKEN (CacheInfo[5]) }  // -> 'LITTLE' core's L1 D-cache
> +  },
> +
> +  // Low Power Idle state information (LPI) for all cores/clusters
> +  {
> +    { // LpiInfo[0] -> Clusters CluPwrDn
> +      2500,         // MinResidency
> +      1150,         // WorstCaseWakeLatency
> +      1,            // Flags
> +      1,            // ArchFlags
> +      100,          // ResCntFreq
> +      0,            // EnableParentState
> +      1,            // IsInteger

[SAMI] IsInteger field is of type BOOLEAN. Therefore, the value here 
should be TRUE. Similar changes are requires at other places in this file.

If you agree, I will make the nessary changes locally before pushing the 
patch.

[/SAMI]

> +      0x01000000,   // IntegerEntryMethod
> +      // RegisterEntryMethod (NULL, use IntegerEntryMethod)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      // ResidencyCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      // UsageCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      "CluPwrDn" // StateName
> +    },
> +    // LpiInfo[1] -> Cores WFI
> +    {
> +      1,            // MinResidency
> +      1,            // WorstCaseWakeLatency
> +      1,            // Flags
> +      0,            // ArchFlags
> +      100,          // ResCntFreq
> +      0,            // EnableParentState
> +      0,            // IsInteger
> +      0,            // IntegerEntryMethod (0, use RegisterEntryMethod)
> +      // RegisterEntryMethod
> +      {
> +        EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE, // AddressSpaceId
> +        0x20, // RegisterBitWidth
> +        0x00, // RegisterBitOffset
> +        0x03, // AccessSize
> +        0xFFFFFFFF // Address
> +      },
> +      // ResidencyCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      // UsageCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      "WFI" // StateName
> +    },
> +    // LpiInfo[2] -> Cores CorePwrDn
> +    {
> +      150,          // MinResidency
> +      350,          // WorstCaseWakeLatency
> +      1,            // Flags
> +      1,            // ArchFlags
> +      100,          // ResCntFreq
> +      1,            // EnableParentState
> +      0,            // IsInteger
> +      0,            // IntegerEntryMethod (0, use RegisterEntryMethod)
> +      // RegisterEntryMethod
> +      {
> +          EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE, // AddressSpaceId
> +          0x20, // RegisterBitWidth
> +          0x00, // RegisterBitOffset
> +          0x03, // AccessSize
> +          0x00010000 // Address
> +      },
> +      // ResidencyCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      // UsageCounterRegister (NULL)
> +      { EFI_ACPI_6_3_SYSTEM_MEMORY, 0, 0, 0, 0 },
> +      "CorePwrDn" // StateName
> +    },
> +  },
> +  // Cluster Low Power Idle state references (LPI)
> +  {
> +    { REFERENCE_TOKEN (LpiInfo[0]) }
> +  },
> +  // Cores Low Power Idle state references (LPI)
> +  {
> +    { REFERENCE_TOKEN (LpiInfo[1]) },
> +    { REFERENCE_TOKEN (LpiInfo[2]) },
>     }
>   };
>   
> @@ -809,6 +913,55 @@ GetGicCInfo (
>     return EFI_NOT_FOUND;
>   }
>   
> +/** Return Lpi State Infor.
> +
> +  @param [in]      This           Pointer to the Configuration Manager Protocol.
> +  @param [in]      CmObjectId     The Object ID of the CM object requested
> +  @param [in]      SearchToken    A unique token for identifying the requested
> +                                  CM_ARM_LPI_INFO object.
> +  @param [in, out] CmObject       Pointer to the Configuration Manager Object
> +                                  descriptor describing the requested Object.
> +
> +  @retval EFI_SUCCESS             Success.
> +  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
> +  @retval EFI_NOT_FOUND           The required object information is not found.
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetLpiInfo (
> +  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
> +  IN  CONST CM_OBJECT_ID                                  CmObjectId,
> +  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
> +  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
> +  )
> +{
> +  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
> +  UINT32                            TotalObjCount;
> +  UINT32                            ObjIndex;
> +
> +  if ((This == NULL) || (CmObject == NULL)) {
> +    ASSERT (This != NULL);
> +    ASSERT (CmObject != NULL);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  PlatformRepo = This->PlatRepoInfo;
> +
> +  TotalObjCount = ARRAY_SIZE (PlatformRepo->LpiInfo);
> +
> +  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
> +    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->LpiInfo[ObjIndex]) {
> +      CmObject->ObjectId = CmObjectId;
> +      CmObject->Size = sizeof (PlatformRepo->LpiInfo[ObjIndex]);
> +      CmObject->Data = (VOID*)&PlatformRepo->LpiInfo[ObjIndex];
> +      CmObject->Count = 1;
> +      return EFI_SUCCESS;
> +    }
> +  }
> +
> +  return EFI_NOT_FOUND;
> +}
> +
>   /** Return a list of Configuration Manager object references pointed to by the
>       given input token.
>   
> @@ -866,6 +1019,18 @@ GetCmObjRefs (
>       CmObject->Count = ARRAY_SIZE (PlatformRepo->LittleCoreResources);
>       return EFI_SUCCESS;
>     }
> +  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->ClustersLpiRef) {
> +    CmObject->Size = sizeof (PlatformRepo->ClustersLpiRef);
> +    CmObject->Data = (VOID*)&PlatformRepo->ClustersLpiRef;
> +    CmObject->Count = ARRAY_SIZE (PlatformRepo->ClustersLpiRef);
> +    return EFI_SUCCESS;
> +  }
> +  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CoresLpiRef) {
> +    CmObject->Size = sizeof (PlatformRepo->CoresLpiRef);
> +    CmObject->Data = (VOID*)&PlatformRepo->CoresLpiRef;
> +    CmObject->Count = ARRAY_SIZE (PlatformRepo->CoresLpiRef);
> +    return EFI_SUCCESS;
> +  }
>   
>     return EFI_NOT_FOUND;
>   }
> @@ -1142,6 +1307,19 @@ GetArmNameSpaceObject (
>         }
>         break;
>   
> +    case EArmObjLpiInfo:
> +      Status = HandleCmObjectRefByToken (
> +                 This,
> +                 CmObjectId,
> +                 NULL,
> +                 0,
> +                 0,
> +                 Token,
> +                 GetLpiInfo,
> +                 CmObject
> +                 );
> +      break;
> +
>       default: {
>         Status = EFI_NOT_FOUND;
>         DEBUG ((
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> index 771b00c31b9e..1bc242bc9d85 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> @@ -115,7 +115,7 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
>   
>   /** The number of ACPI tables to install
>   */
> -#define PLAT_ACPI_TABLE_COUNT   10
> +#define PLAT_ACPI_TABLE_COUNT   11
>   
>   /** The number of platform generic timer blocks
>   */
> @@ -172,6 +172,15 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
>   */
>   #define LITTLE_CORE_RESOURCE_COUNT  2
>   
> +/** The number of Lpi states for the platform:
> +    - two for the cores
> +    - one for the clusters
> +*/
> +#define CORES_LPI_STATE_COUNT           2
> +#define CLUSTERS_LPI_STATE_COUNT        1
> +#define LPI_STATE_COUNT                 (CORES_LPI_STATE_COUNT +              \
> +                                         CLUSTERS_LPI_STATE_COUNT)
> +
>   /** A structure describing the platform configuration
>       manager repository information
>   */
> @@ -238,6 +247,15 @@ typedef struct PlatformRepositoryInfo {
>     // 'LITTLE' core private resources
>     CM_ARM_OBJ_REF                        LittleCoreResources[LITTLE_CORE_RESOURCE_COUNT];
>   
> +  // Low Power Idle state information (LPI) for all cores/clusters
> +  CM_ARM_LPI_INFO                       LpiInfo[LPI_STATE_COUNT];
> +
> +  // Clusters Low Power Idle state references (LPI)
> +  CM_ARM_OBJ_REF                        ClustersLpiRef[CLUSTERS_LPI_STATE_COUNT];
> +
> +  // Cores Low Power Idle state references (LPI)
> +  CM_ARM_OBJ_REF                        CoresLpiRef[CORES_LPI_STATE_COUNT];
> +
>     /// Juno Board Revision
>     UINT32                                JunoRevision;
>   } EDKII_PLATFORM_REPOSITORY_INFO;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology
  2022-07-18 13:25   ` Sami Mujawar
@ 2022-07-18 13:30     ` PierreGondois
  0 siblings, 0 replies; 12+ messages in thread
From: PierreGondois @ 2022-07-18 13:30 UTC (permalink / raw)
  To: Sami Mujawar, devel; +Cc: Ard Biesheuvel, nd

Hi Sami,

On 7/18/22 15:25, Sami Mujawar wrote:
> Hi Pierre,
> 
> Thank you for this patch.
> 
> Please find my response inline marked [SAMI].
> 
> Other than the comment below, these changes looks good to me.
> 
> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
> 
> Regards,
> 
> Sami Mujawar
> 
> On 27/04/2022 03:59 pm, Pierre.Gondois@arm.com wrote:
>> From: Pierre Gondois <Pierre.Gondois@arm.com>
>>
>> The Dynamic Tables Framework has been updated to add support for
>> generating an ASL description of a CPU topology and its _LPI states.
>> This patch:
>>    - Describes the _LPI states in the Configuration Manager of the Juno
>>    - Add the generation of a new SSDT table describing the CPU topology
>>      and its _LPI states
>>    - Removes the CPU topology description of the DSDT table
>>
>> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
>> ---
>>    .../AslTables/Dsdt.asl                        | 198 ------------------
>>    .../ConfigurationManager.c                    | 196 ++++++++++++++++-
>>    .../ConfigurationManager.h                    |  20 +-
>>    3 files changed, 206 insertions(+), 208 deletions(-)
>>

[snip]

>>    
>> @@ -549,6 +575,84 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>>      {
>>        { REFERENCE_TOKEN (CacheInfo[4]) }, // -> 'LITTLE' core's L1 I-cache
>>        { REFERENCE_TOKEN (CacheInfo[5]) }  // -> 'LITTLE' core's L1 D-cache
>> +  },
>> +
>> +  // Low Power Idle state information (LPI) for all cores/clusters
>> +  {
>> +    { // LpiInfo[0] -> Clusters CluPwrDn
>> +      2500,         // MinResidency
>> +      1150,         // WorstCaseWakeLatency
>> +      1,            // Flags
>> +      1,            // ArchFlags
>> +      100,          // ResCntFreq
>> +      0,            // EnableParentState
>> +      1,            // IsInteger
> 
> [SAMI] IsInteger field is of type BOOLEAN. Therefore, the value here
> should be TRUE. Similar changes are requires at other places in this file.
> 
> If you agree, I will make the nessary changes locally before pushing the
> patch.
> 
> [/SAMI]
> 

Thanks for catching this. Yes if you can make this change it would be awesome,

Regards,
Pierre

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order
  2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology PierreGondois
@ 2022-04-27 14:59 ` PierreGondois
  2022-07-18 13:26   ` Sami Mujawar
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus PierreGondois
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 12+ messages in thread
From: PierreGondois @ 2022-04-27 14:59 UTC (permalink / raw)
  To: devel; +Cc: Ard Biesheuvel, Sami Mujawar

From: Pierre Gondois <Pierre.Gondois@arm.com>

The values printed in the 'DEBUG' are not printed in the right
order. Re-order them.

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
 .../ConfigurationManagerDxe/ConfigurationManager.c              | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 977aba5da5c4..d147bbc317db 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -790,8 +790,8 @@ HandleCmObjectSearchPlatformRepo (
   DEBUG ((
     DEBUG_INFO,
     "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
-    CmObjectId,
     (VOID*)Token,
+    CmObjectId,
     CmObjectDesc->Data,
     CmObjectDesc->Size,
     CmObjectDesc->Count
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order PierreGondois
@ 2022-07-18 13:26   ` Sami Mujawar
  0 siblings, 0 replies; 12+ messages in thread
From: Sami Mujawar @ 2022-07-18 13:26 UTC (permalink / raw)
  To: Pierre.Gondois, devel; +Cc: Ard Biesheuvel, nd

Hi Pierre,

Thank you for this fix.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 27/04/2022 03:59 pm, Pierre.Gondois@arm.com wrote:
> From: Pierre Gondois <Pierre.Gondois@arm.com>
>
> The values printed in the 'DEBUG' are not printed in the right
> order. Re-order them.
>
> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
> ---
>   .../ConfigurationManagerDxe/ConfigurationManager.c              | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index 977aba5da5c4..d147bbc317db 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -790,8 +790,8 @@ HandleCmObjectSearchPlatformRepo (
>     DEBUG ((
>       DEBUG_INFO,
>       "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
> -    CmObjectId,
>       (VOID*)Token,
> +    CmObjectId,
>       CmObjectDesc->Data,
>       CmObjectDesc->Size,
>       CmObjectDesc->Count

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus
  2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology PierreGondois
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order PierreGondois
@ 2022-04-27 14:59 ` PierreGondois
  2022-07-18 14:02   ` Sami Mujawar
  2022-04-29 13:35 ` [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno Ard Biesheuvel
  2022-07-18 16:25 ` Sami Mujawar
  4 siblings, 1 reply; 12+ messages in thread
From: PierreGondois @ 2022-04-27 14:59 UTC (permalink / raw)
  To: devel; +Cc: Ard Biesheuvel, Sami Mujawar

From: Pierre Gondois <Pierre.Gondois@arm.com>

The Dynamic Tables Framework has been updated to add support for
generating an ASL description of PCIe busses.
This patch:
 - Describes the PCI address-range mapping and PCI devices legacy
   interrupts in the Configuration Manager of the Juno
 - Add the generation of a new SSDT table describing the PCIe bus
 - Removes the existing (and hard-coded) SSDT table describing the
   PCIe bus

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
 .../AslTables/SsdtPci.asl                     | 195 ---------------
 .../ConfigurationManager.c                    | 227 +++++++++++++++++-
 .../ConfigurationManager.h                    |  27 +++
 .../ConfigurationManagerDxe.inf               |   1 -
 4 files changed, 249 insertions(+), 201 deletions(-)
 delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl

diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
deleted file mode 100644
index 2ed37ea83c6c..000000000000
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
+++ /dev/null
@@ -1,195 +0,0 @@
-/** @file
-  SSDT for Juno PCIe
-
-  Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.<BR>
-    SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "ArmPlatform.h"
-
-/*
-  See ACPI 6.1 Section 6.2.13
-
-  There are two ways that _PRT can be used.
-
-  In the first model, a PCI Link device is used to provide additional
-  configuration information such as whether the interrupt is Level or
-  Edge triggered, it is active High or Low, Shared or Exclusive, etc.
-
-  In the second model, the PCI interrupts are hardwired to specific
-  interrupt inputs on the interrupt controller and are not
-  configurable. In this case, the Source field in _PRT does not
-  reference a device, but instead contains the value zero, and the
-  Source Index field contains the global system interrupt to which the
-  PCI interrupt is hardwired.
-
-  We use the first model with link indirection to set the correct
-  interrupt type as PCI defaults (Level Triggered, Active Low) are not
-  compatible with GICv2.
-*/
-#define LNK_DEVICE(Unique_Id, Link_Name, irq)                           \
-  Device(Link_Name) {                                                   \
-  Name(_HID, EISAID("PNP0C0F"))                                         \
-  Name(_UID, Unique_Id)                                                 \
-  Name(_PRS, ResourceTemplate() {                                       \
-    Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
-    })                                                                  \
-  Method (_CRS, 0) { Return (_PRS) }                                    \
-  Method (_SRS, 1) { }                                                  \
-  Method (_DIS) { }                                                     \
-}
-
-#define PRT_ENTRY(Address, Pin, Link)                                                   \
-  Package (4) {                                                                         \
-    Address,  /* uses the same format as _ADR */                                        \
-    Pin,      /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD)  */  \
-    Link,     /* Interrupt allocated via Link device  */                                \
-    Zero      /* global system interrupt number (no used) */                            \
-}
-
-/*
-  See Reference [1] 6.1.1
-  "High word–Device #, Low word–Function #. (for example, device 3,
-  function 2 is 0x00030002). To refer to all the functions on a device #,
-  use a function number of FFFF)."
-*/
-#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)
-                                                    // Device 0 for Bridge.
-
-DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
-  Scope(_SB) {
-    //
-    // PCI Root Complex
-    //
-    LNK_DEVICE(1, LNKA, 168)
-    LNK_DEVICE(2, LNKB, 169)
-    LNK_DEVICE(3, LNKC, 170)
-    LNK_DEVICE(4, LNKD, 171)
-
-    Device(PCI0)
-    {
-      Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
-      Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
-      Name(_SEG, Zero) // PCI Segment Group number
-      Name(_BBN, Zero) // PCI Base Bus Number
-      Name(_CCA, 1)    // Initially mark the PCI coherent (for JunoR1)
-
-      // Root Complex 0
-      Device (RP0) {
-        Name(_ADR, 0xF0000000)    // Dev 0, Func 0
-      }
-
-      // PCI Routing Table
-      Name(_PRT, Package() {
-        ROOT_PRT_ENTRY(0, LNKA),   // INTA
-        ROOT_PRT_ENTRY(1, LNKB),   // INTB
-        ROOT_PRT_ENTRY(2, LNKC),   // INTC
-        ROOT_PRT_ENTRY(3, LNKD),   // INTD
-        })
-      // Root complex resources
-      Method (_CRS, 0, Serialized) {
-      Name (RBUF, ResourceTemplate () {
-        WordBusNumber ( // Bus numbers assigned to this root
-          ResourceProducer,
-          MinFixed, MaxFixed, PosDecode,
-          0,   // AddressGranularity
-          0,   // AddressMinimum - Minimum Bus Number
-          255, // AddressMaximum - Maximum Bus Number
-          0,   // AddressTranslation - Set to 0
-          256  // RangeLength - Number of Busses
-          )
-
-        DWordMemory ( // 32-bit BAR Windows
-          ResourceProducer, PosDecode,
-          MinFixed, MaxFixed,
-          Cacheable, ReadWrite,
-          0x00000000,                          // Granularity
-          0x50000000,                          // Min Base Address
-          0x57FFFFFF,                          // Max Base Address
-          0x00000000,                          // Translate
-          0x08000000                           // Length
-          )
-
-        QWordMemory ( // 64-bit BAR Windows
-          ResourceProducer, PosDecode,
-          MinFixed, MaxFixed,
-          Cacheable, ReadWrite,
-          0x00000000,                          // Granularity
-          0x4000000000,                        // Min Base Address
-          0x40FFFFFFFF,                        // Max Base Address
-          0x00000000,                          // Translate
-          0x100000000                          // Length
-          )
-
-        DWordIo ( // IO window
-          ResourceProducer,
-          MinFixed,
-          MaxFixed,
-          PosDecode,
-          EntireRange,
-          0x00000000,                          // Granularity
-          0x00000000,                          // Min Base Address
-          0x007fffff,                          // Max Base Address
-          0x5f800000,                          // Translate
-          0x00800000,                          // Length
-          ,,,TypeTranslation
-          )
-        }) // Name(RBUF)
-
-        Return (RBUF)
-      } // Method(_CRS)
-
-      //
-      // OS Control Handoff
-      //
-      Name(SUPP, Zero) // PCI _OSC Support Field value
-      Name(CTRL, Zero) // PCI _OSC Control Field value
-
-      /*
-        See [1] 6.2.10, [2] 4.5
-      */
-      Method(_OSC,4) {
-        // Check for proper UUID
-        If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
-          // Create DWord-adressable fields from the Capabilities Buffer
-          CreateDWordField(Arg3,0,CDW1)
-          CreateDWordField(Arg3,4,CDW2)
-          CreateDWordField(Arg3,8,CDW3)
-
-          // Save Capabilities DWord2 & 3
-          Store(CDW2,SUPP)
-          Store(CDW3,CTRL)
-
-          // Only allow native hot plug control if OS supports:
-          // * ASPM
-          // * Clock PM
-          // * MSI/MSI-X
-          If(LNotEqual(And(SUPP, 0x16), 0x16)) {
-            And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
-          }
-
-          // Always allow native PME, AER (no dependencies)
-
-          // Never allow SHPC (no SHPC controller in this system)
-          And(CTRL,0x1D,CTRL)
-
-          If(LNotEqual(Arg1,One)) {        // Unknown revision
-            Or(CDW1,0x08,CDW1)
-          }
-
-          If(LNotEqual(CDW3,CTRL)) {        // Capabilities bits were masked
-            Or(CDW1,0x10,CDW1)
-          }
-
-          // Update DWORD3 in the buffer
-          Store(CTRL,CDW3)
-          Return(Arg3)
-        } Else {
-          Or(CDW1,4,CDW1) // Unrecognized UUID
-          Return(Arg3)
-        }
-      } // End _OSC
-    } // PCI0
-  }
-}
diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index d147bbc317db..61c704411620 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -111,11 +111,12 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
     },
     // SSDT table describing the PCI root complex
     {
-      EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
       0, // Unused
-      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
-      (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
-    }
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtPciExpress),
+      NULL,
+      SIGNATURE_64 ('S','S','D','T','-','P','C','I')
+    },
   },
 
   // Boot architecture information
@@ -244,7 +245,86 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
     // The start bus number
     FixedPcdGet32 (PcdPciBusMin),
     // The end bus number
-    FixedPcdGet32 (PcdPciBusMax)
+    FixedPcdGet32 (PcdPciBusMax),
+    // AddressMapToken
+    REFERENCE_TOKEN (PciAddressMapRef),
+    // InterruptMapToken
+    REFERENCE_TOKEN (PciInterruptMapRef)
+  },
+
+  // PCI address-range mapping references
+  {
+    { REFERENCE_TOKEN (PciAddressMapInfo[0]) },
+    { REFERENCE_TOKEN (PciAddressMapInfo[1]) },
+    { REFERENCE_TOKEN (PciAddressMapInfo[2]) }
+  },
+  // PCI address-range mapping information
+  {
+    { // PciAddressMapInfo[0] -> 32-bit BAR Window
+      PCI_SS_M32,    // SpaceCode
+      0x50000000,    // PciAddress
+      0x50000000,    // CpuAddress
+      0x08000000     // AddressSize
+    },
+    { // PciAddressMapInfo[1] -> 64-bit BAR Window
+      PCI_SS_M64,    // SpaceCode
+      0x4000000000,  // PciAddress
+      0x4000000000,  // CpuAddress
+      0x0100000000   // AddressSize
+    },
+    { // PciAddressMapInfo[2] -> IO BAR Window
+      PCI_SS_IO,     // SpaceCode
+      0x00000000,    // PciAddress
+      0x5f800000,    // CpuAddress
+      0x00800000     // AddressSize
+    },
+  },
+
+  // PCI device legacy interrupts mapping information
+  {
+    { REFERENCE_TOKEN (PciInterruptMapInfo[0]) },
+    { REFERENCE_TOKEN (PciInterruptMapInfo[1]) },
+    { REFERENCE_TOKEN (PciInterruptMapInfo[2]) },
+    { REFERENCE_TOKEN (PciInterruptMapInfo[3]) }
+  },
+  // PCI device legacy interrupts mapping information
+  {
+    { // PciInterruptMapInfo[0] -> Device 0, INTA
+      0,   // PciBus
+      0,   // PciDevice
+      0,   // PciInterrupt
+      {
+        168, // Interrupt
+        0x0  // Flags
+      }
+    },
+    { // PciInterruptMapInfo[1] -> Device 0, INTB
+      0,   // PciBus
+      0,   // PciDevice
+      1,   // PciInterrupt
+      {
+        169, // Interrupt
+        0x0  // Flags
+      }
+    },
+    { // PciInterruptMapInfo[2] -> Device 0, INTC
+      0,   // PciBus
+      0,   // PciDevice
+      2,   // PciInterrupt
+      {
+        170, // Interrupt
+        0x0  // Flags
+      }
+    },
+    { // PciInterruptMapInfo[3] -> Device 0, INTD
+      0,   // PciBus
+      0,   // PciDevice
+      3,   // PciInterrupt
+      {
+        171, // Interrupt
+        0x0  // Flags
+      }
+    },
   },
 
   // GIC Msi Frame Info
@@ -962,6 +1042,105 @@ GetLpiInfo (
   return EFI_NOT_FOUND;
 }
 
+
+/** Return PCI address-range mapping Info.
+
+  @param [in]      This           Pointer to the Configuration Manager Protocol.
+  @param [in]      CmObjectId     The Object ID of the CM object requested
+  @param [in]      SearchToken    A unique token for identifying the requested
+                                  CM_ARM_PCI_ADDRESS_MAP_INFO object.
+  @param [in, out] CmObject       Pointer to the Configuration Manager Object
+                                  descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS             Success.
+  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
+  @retval EFI_NOT_FOUND           The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetPciAddressMapInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINT32                            TotalObjCount;
+  UINT32                            ObjIndex;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  TotalObjCount = ARRAY_SIZE (PlatformRepo->PciAddressMapInfo);
+
+  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
+    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciAddressMapInfo[ObjIndex]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->PciAddressMapInfo[ObjIndex]);
+      CmObject->Data = (VOID*)&PlatformRepo->PciAddressMapInfo[ObjIndex];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/** Return PCI device legacy interrupt mapping Info.
+
+  @param [in]      This           Pointer to the Configuration Manager Protocol.
+  @param [in]      CmObjectId     The Object ID of the CM object requested
+  @param [in]      SearchToken    A unique token for identifying the requested
+                                  CM_ARM_PCI_INTERRUPT_MAP_INFO object.
+  @param [in, out] CmObject       Pointer to the Configuration Manager Object
+                                  descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS             Success.
+  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
+  @retval EFI_NOT_FOUND           The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetPciInterruptMapInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINT32                            TotalObjCount;
+  UINT32                            ObjIndex;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  TotalObjCount = ARRAY_SIZE (PlatformRepo->PciInterruptMapInfo);
+
+  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
+    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciInterruptMapInfo[ObjIndex]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->PciInterruptMapInfo[ObjIndex]);
+      CmObject->Data = (VOID*)&PlatformRepo->PciInterruptMapInfo[ObjIndex];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
 /** Return a list of Configuration Manager object references pointed to by the
     given input token.
 
@@ -1031,6 +1210,18 @@ GetCmObjRefs (
     CmObject->Count = ARRAY_SIZE (PlatformRepo->CoresLpiRef);
     return EFI_SUCCESS;
   }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciAddressMapRef) {
+    CmObject->Size = sizeof (PlatformRepo->PciAddressMapRef);
+    CmObject->Data = (VOID*)&PlatformRepo->PciAddressMapRef;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->PciAddressMapRef);
+    return EFI_SUCCESS;
+  }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciInterruptMapRef) {
+    CmObject->Size = sizeof (PlatformRepo->PciInterruptMapRef);
+    CmObject->Data = (VOID*)&PlatformRepo->PciInterruptMapRef;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->PciInterruptMapRef);
+    return EFI_SUCCESS;
+  }
 
   return EFI_NOT_FOUND;
 }
@@ -1320,6 +1511,32 @@ GetArmNameSpaceObject (
                  );
       break;
 
+    case EArmObjPciAddressMapInfo:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->PciAddressMapInfo,
+                 sizeof (PlatformRepo->PciAddressMapInfo),
+                 ARRAY_SIZE (PlatformRepo->PciAddressMapInfo),
+                 Token,
+                 GetPciAddressMapInfo,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjPciInterruptMapInfo:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->PciInterruptMapInfo,
+                 sizeof (PlatformRepo->PciInterruptMapInfo),
+                 ARRAY_SIZE (PlatformRepo->PciInterruptMapInfo),
+                 Token,
+                 GetPciInterruptMapInfo,
+                 CmObject
+                 );
+      break;
+
     default: {
       Status = EFI_NOT_FOUND;
       DEBUG ((
diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
index 1bc242bc9d85..5b5e62427f2b 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -90,6 +90,21 @@ extern CHAR8  ssdtpci_aml_code[];
     (WritePolicy << 4)                                                  \
   )
 
+/** PCI space codes.
+*/
+#define PCI_SS_CONFIG   0
+#define PCI_SS_IO       1
+#define PCI_SS_M32      2
+#define PCI_SS_M64      3
+
+/** Count of PCI address-range mapping struct.
+*/
+#define PCI_ADDRESS_MAP_COUNT       3
+
+/** Count of PCI device legacy interrupt mapping struct.
+*/
+#define PCI_INTERRUPT_MAP_COUNT     4
+
 /** A function that prepares Configuration Manager Objects for returning.
 
   @param [in]  This        Pointer to the Configuration Manager Protocol.
@@ -226,6 +241,18 @@ typedef struct PlatformRepositoryInfo {
   /// PCI configuration space information
   CM_ARM_PCI_CONFIG_SPACE_INFO          PciConfigInfo;
 
+  // PCI address-range mapping references
+  CM_ARM_OBJ_REF                        PciAddressMapRef[PCI_ADDRESS_MAP_COUNT];
+
+  // PCI address-range mapping information
+  CM_ARM_PCI_ADDRESS_MAP_INFO           PciAddressMapInfo[PCI_ADDRESS_MAP_COUNT];
+
+  // PCI device legacy interrupts mapping references
+  CM_ARM_OBJ_REF                        PciInterruptMapRef[PCI_INTERRUPT_MAP_COUNT];
+
+  // PCI device legacy interrupts mapping information
+  CM_ARM_PCI_INTERRUPT_MAP_INFO         PciInterruptMapInfo[PCI_INTERRUPT_MAP_COUNT];
+
   /// GIC MSI Frame information
   CM_ARM_GIC_MSI_FRAME_INFO             GicMsiFrameInfo;
 
diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 7ca134d6674b..91bffe8d5d82 100644
--- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -24,7 +24,6 @@ [Sources]
   ConfigurationManager.c
   AslTables/Dsdt.asl
   AslTables/SsdtJunoUsb.asl
-  AslTables/SsdtPci.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus PierreGondois
@ 2022-07-18 14:02   ` Sami Mujawar
  0 siblings, 0 replies; 12+ messages in thread
From: Sami Mujawar @ 2022-07-18 14:02 UTC (permalink / raw)
  To: Pierre.Gondois, devel; +Cc: Ard Biesheuvel, nd

Hi Pierre,

Thank you for this patch.

These changes look good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 27/04/2022 03:59 pm, Pierre.Gondois@arm.com wrote:
> From: Pierre Gondois <Pierre.Gondois@arm.com>
>
> The Dynamic Tables Framework has been updated to add support for
> generating an ASL description of PCIe busses.
> This patch:
>   - Describes the PCI address-range mapping and PCI devices legacy
>     interrupts in the Configuration Manager of the Juno
>   - Add the generation of a new SSDT table describing the PCIe bus
>   - Removes the existing (and hard-coded) SSDT table describing the
>     PCIe bus
>
> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
> ---
>   .../AslTables/SsdtPci.asl                     | 195 ---------------
>   .../ConfigurationManager.c                    | 227 +++++++++++++++++-
>   .../ConfigurationManager.h                    |  27 +++
>   .../ConfigurationManagerDxe.inf               |   1 -
>   4 files changed, 249 insertions(+), 201 deletions(-)
>   delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
>
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> deleted file mode 100644
> index 2ed37ea83c6c..000000000000
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> +++ /dev/null
> @@ -1,195 +0,0 @@
> -/** @file
> -  SSDT for Juno PCIe
> -
> -  Copyright (c) 2014 - 2019, ARM Ltd. All rights reserved.<BR>
> -    SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include "ArmPlatform.h"
> -
> -/*
> -  See ACPI 6.1 Section 6.2.13
> -
> -  There are two ways that _PRT can be used.
> -
> -  In the first model, a PCI Link device is used to provide additional
> -  configuration information such as whether the interrupt is Level or
> -  Edge triggered, it is active High or Low, Shared or Exclusive, etc.
> -
> -  In the second model, the PCI interrupts are hardwired to specific
> -  interrupt inputs on the interrupt controller and are not
> -  configurable. In this case, the Source field in _PRT does not
> -  reference a device, but instead contains the value zero, and the
> -  Source Index field contains the global system interrupt to which the
> -  PCI interrupt is hardwired.
> -
> -  We use the first model with link indirection to set the correct
> -  interrupt type as PCI defaults (Level Triggered, Active Low) are not
> -  compatible with GICv2.
> -*/
> -#define LNK_DEVICE(Unique_Id, Link_Name, irq)                           \
> -  Device(Link_Name) {                                                   \
> -  Name(_HID, EISAID("PNP0C0F"))                                         \
> -  Name(_UID, Unique_Id)                                                 \
> -  Name(_PRS, ResourceTemplate() {                                       \
> -    Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq }   \
> -    })                                                                  \
> -  Method (_CRS, 0) { Return (_PRS) }                                    \
> -  Method (_SRS, 1) { }                                                  \
> -  Method (_DIS) { }                                                     \
> -}
> -
> -#define PRT_ENTRY(Address, Pin, Link)                                                   \
> -  Package (4) {                                                                         \
> -    Address,  /* uses the same format as _ADR */                                        \
> -    Pin,      /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD)  */  \
> -    Link,     /* Interrupt allocated via Link device  */                                \
> -    Zero      /* global system interrupt number (no used) */                            \
> -}
> -
> -/*
> -  See Reference [1] 6.1.1
> -  "High word–Device #, Low word–Function #. (for example, device 3,
> -  function 2 is 0x00030002). To refer to all the functions on a device #,
> -  use a function number of FFFF)."
> -*/
> -#define ROOT_PRT_ENTRY(Pin, Link)   PRT_ENTRY(0x0000FFFF, Pin, Link)
> -                                                    // Device 0 for Bridge.
> -
> -DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
> -  Scope(_SB) {
> -    //
> -    // PCI Root Complex
> -    //
> -    LNK_DEVICE(1, LNKA, 168)
> -    LNK_DEVICE(2, LNKB, 169)
> -    LNK_DEVICE(3, LNKC, 170)
> -    LNK_DEVICE(4, LNKD, 171)
> -
> -    Device(PCI0)
> -    {
> -      Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> -      Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> -      Name(_SEG, Zero) // PCI Segment Group number
> -      Name(_BBN, Zero) // PCI Base Bus Number
> -      Name(_CCA, 1)    // Initially mark the PCI coherent (for JunoR1)
> -
> -      // Root Complex 0
> -      Device (RP0) {
> -        Name(_ADR, 0xF0000000)    // Dev 0, Func 0
> -      }
> -
> -      // PCI Routing Table
> -      Name(_PRT, Package() {
> -        ROOT_PRT_ENTRY(0, LNKA),   // INTA
> -        ROOT_PRT_ENTRY(1, LNKB),   // INTB
> -        ROOT_PRT_ENTRY(2, LNKC),   // INTC
> -        ROOT_PRT_ENTRY(3, LNKD),   // INTD
> -        })
> -      // Root complex resources
> -      Method (_CRS, 0, Serialized) {
> -      Name (RBUF, ResourceTemplate () {
> -        WordBusNumber ( // Bus numbers assigned to this root
> -          ResourceProducer,
> -          MinFixed, MaxFixed, PosDecode,
> -          0,   // AddressGranularity
> -          0,   // AddressMinimum - Minimum Bus Number
> -          255, // AddressMaximum - Maximum Bus Number
> -          0,   // AddressTranslation - Set to 0
> -          256  // RangeLength - Number of Busses
> -          )
> -
> -        DWordMemory ( // 32-bit BAR Windows
> -          ResourceProducer, PosDecode,
> -          MinFixed, MaxFixed,
> -          Cacheable, ReadWrite,
> -          0x00000000,                          // Granularity
> -          0x50000000,                          // Min Base Address
> -          0x57FFFFFF,                          // Max Base Address
> -          0x00000000,                          // Translate
> -          0x08000000                           // Length
> -          )
> -
> -        QWordMemory ( // 64-bit BAR Windows
> -          ResourceProducer, PosDecode,
> -          MinFixed, MaxFixed,
> -          Cacheable, ReadWrite,
> -          0x00000000,                          // Granularity
> -          0x4000000000,                        // Min Base Address
> -          0x40FFFFFFFF,                        // Max Base Address
> -          0x00000000,                          // Translate
> -          0x100000000                          // Length
> -          )
> -
> -        DWordIo ( // IO window
> -          ResourceProducer,
> -          MinFixed,
> -          MaxFixed,
> -          PosDecode,
> -          EntireRange,
> -          0x00000000,                          // Granularity
> -          0x00000000,                          // Min Base Address
> -          0x007fffff,                          // Max Base Address
> -          0x5f800000,                          // Translate
> -          0x00800000,                          // Length
> -          ,,,TypeTranslation
> -          )
> -        }) // Name(RBUF)
> -
> -        Return (RBUF)
> -      } // Method(_CRS)
> -
> -      //
> -      // OS Control Handoff
> -      //
> -      Name(SUPP, Zero) // PCI _OSC Support Field value
> -      Name(CTRL, Zero) // PCI _OSC Control Field value
> -
> -      /*
> -        See [1] 6.2.10, [2] 4.5
> -      */
> -      Method(_OSC,4) {
> -        // Check for proper UUID
> -        If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> -          // Create DWord-adressable fields from the Capabilities Buffer
> -          CreateDWordField(Arg3,0,CDW1)
> -          CreateDWordField(Arg3,4,CDW2)
> -          CreateDWordField(Arg3,8,CDW3)
> -
> -          // Save Capabilities DWord2 & 3
> -          Store(CDW2,SUPP)
> -          Store(CDW3,CTRL)
> -
> -          // Only allow native hot plug control if OS supports:
> -          // * ASPM
> -          // * Clock PM
> -          // * MSI/MSI-X
> -          If(LNotEqual(And(SUPP, 0x16), 0x16)) {
> -            And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
> -          }
> -
> -          // Always allow native PME, AER (no dependencies)
> -
> -          // Never allow SHPC (no SHPC controller in this system)
> -          And(CTRL,0x1D,CTRL)
> -
> -          If(LNotEqual(Arg1,One)) {        // Unknown revision
> -            Or(CDW1,0x08,CDW1)
> -          }
> -
> -          If(LNotEqual(CDW3,CTRL)) {        // Capabilities bits were masked
> -            Or(CDW1,0x10,CDW1)
> -          }
> -
> -          // Update DWORD3 in the buffer
> -          Store(CTRL,CDW3)
> -          Return(Arg3)
> -        } Else {
> -          Or(CDW1,4,CDW1) // Unrecognized UUID
> -          Return(Arg3)
> -        }
> -      } // End _OSC
> -    } // PCI0
> -  }
> -}
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> index d147bbc317db..61c704411620 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
> @@ -111,11 +111,12 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>       },
>       // SSDT table describing the PCI root complex
>       {
> -      EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
> +      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
>         0, // Unused
> -      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
> -      (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
> -    }
> +      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdtPciExpress),
> +      NULL,
> +      SIGNATURE_64 ('S','S','D','T','-','P','C','I')
> +    },
>     },
>   
>     // Boot architecture information
> @@ -244,7 +245,86 @@ EDKII_PLATFORM_REPOSITORY_INFO ArmJunoPlatformRepositoryInfo = {
>       // The start bus number
>       FixedPcdGet32 (PcdPciBusMin),
>       // The end bus number
> -    FixedPcdGet32 (PcdPciBusMax)
> +    FixedPcdGet32 (PcdPciBusMax),
> +    // AddressMapToken
> +    REFERENCE_TOKEN (PciAddressMapRef),
> +    // InterruptMapToken
> +    REFERENCE_TOKEN (PciInterruptMapRef)
> +  },
> +
> +  // PCI address-range mapping references
> +  {
> +    { REFERENCE_TOKEN (PciAddressMapInfo[0]) },
> +    { REFERENCE_TOKEN (PciAddressMapInfo[1]) },
> +    { REFERENCE_TOKEN (PciAddressMapInfo[2]) }
> +  },
> +  // PCI address-range mapping information
> +  {
> +    { // PciAddressMapInfo[0] -> 32-bit BAR Window
> +      PCI_SS_M32,    // SpaceCode
> +      0x50000000,    // PciAddress
> +      0x50000000,    // CpuAddress
> +      0x08000000     // AddressSize
> +    },
> +    { // PciAddressMapInfo[1] -> 64-bit BAR Window
> +      PCI_SS_M64,    // SpaceCode
> +      0x4000000000,  // PciAddress
> +      0x4000000000,  // CpuAddress
> +      0x0100000000   // AddressSize
> +    },
> +    { // PciAddressMapInfo[2] -> IO BAR Window
> +      PCI_SS_IO,     // SpaceCode
> +      0x00000000,    // PciAddress
> +      0x5f800000,    // CpuAddress
> +      0x00800000     // AddressSize
> +    },
> +  },
> +
> +  // PCI device legacy interrupts mapping information
> +  {
> +    { REFERENCE_TOKEN (PciInterruptMapInfo[0]) },
> +    { REFERENCE_TOKEN (PciInterruptMapInfo[1]) },
> +    { REFERENCE_TOKEN (PciInterruptMapInfo[2]) },
> +    { REFERENCE_TOKEN (PciInterruptMapInfo[3]) }
> +  },
> +  // PCI device legacy interrupts mapping information
> +  {
> +    { // PciInterruptMapInfo[0] -> Device 0, INTA
> +      0,   // PciBus
> +      0,   // PciDevice
> +      0,   // PciInterrupt
> +      {
> +        168, // Interrupt
> +        0x0  // Flags
> +      }
> +    },
> +    { // PciInterruptMapInfo[1] -> Device 0, INTB
> +      0,   // PciBus
> +      0,   // PciDevice
> +      1,   // PciInterrupt
> +      {
> +        169, // Interrupt
> +        0x0  // Flags
> +      }
> +    },
> +    { // PciInterruptMapInfo[2] -> Device 0, INTC
> +      0,   // PciBus
> +      0,   // PciDevice
> +      2,   // PciInterrupt
> +      {
> +        170, // Interrupt
> +        0x0  // Flags
> +      }
> +    },
> +    { // PciInterruptMapInfo[3] -> Device 0, INTD
> +      0,   // PciBus
> +      0,   // PciDevice
> +      3,   // PciInterrupt
> +      {
> +        171, // Interrupt
> +        0x0  // Flags
> +      }
> +    },
>     },
>   
>     // GIC Msi Frame Info
> @@ -962,6 +1042,105 @@ GetLpiInfo (
>     return EFI_NOT_FOUND;
>   }
>   
> +
> +/** Return PCI address-range mapping Info.
> +
> +  @param [in]      This           Pointer to the Configuration Manager Protocol.
> +  @param [in]      CmObjectId     The Object ID of the CM object requested
> +  @param [in]      SearchToken    A unique token for identifying the requested
> +                                  CM_ARM_PCI_ADDRESS_MAP_INFO object.
> +  @param [in, out] CmObject       Pointer to the Configuration Manager Object
> +                                  descriptor describing the requested Object.
> +
> +  @retval EFI_SUCCESS             Success.
> +  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
> +  @retval EFI_NOT_FOUND           The required object information is not found.
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetPciAddressMapInfo (
> +  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
> +  IN  CONST CM_OBJECT_ID                                  CmObjectId,
> +  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
> +  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
> +  )
> +{
> +  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
> +  UINT32                            TotalObjCount;
> +  UINT32                            ObjIndex;
> +
> +  if ((This == NULL) || (CmObject == NULL)) {
> +    ASSERT (This != NULL);
> +    ASSERT (CmObject != NULL);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  PlatformRepo = This->PlatRepoInfo;
> +
> +  TotalObjCount = ARRAY_SIZE (PlatformRepo->PciAddressMapInfo);
> +
> +  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
> +    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciAddressMapInfo[ObjIndex]) {
> +      CmObject->ObjectId = CmObjectId;
> +      CmObject->Size = sizeof (PlatformRepo->PciAddressMapInfo[ObjIndex]);
> +      CmObject->Data = (VOID*)&PlatformRepo->PciAddressMapInfo[ObjIndex];
> +      CmObject->Count = 1;
> +      return EFI_SUCCESS;
> +    }
> +  }
> +
> +  return EFI_NOT_FOUND;
> +}
> +
> +/** Return PCI device legacy interrupt mapping Info.
> +
> +  @param [in]      This           Pointer to the Configuration Manager Protocol.
> +  @param [in]      CmObjectId     The Object ID of the CM object requested
> +  @param [in]      SearchToken    A unique token for identifying the requested
> +                                  CM_ARM_PCI_INTERRUPT_MAP_INFO object.
> +  @param [in, out] CmObject       Pointer to the Configuration Manager Object
> +                                  descriptor describing the requested Object.
> +
> +  @retval EFI_SUCCESS             Success.
> +  @retval EFI_INVALID_PARAMETER   A parameter is invalid.
> +  @retval EFI_NOT_FOUND           The required object information is not found.
> +**/
> +EFI_STATUS
> +EFIAPI
> +GetPciInterruptMapInfo (
> +  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
> +  IN  CONST CM_OBJECT_ID                                  CmObjectId,
> +  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
> +  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
> +  )
> +{
> +  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
> +  UINT32                            TotalObjCount;
> +  UINT32                            ObjIndex;
> +
> +  if ((This == NULL) || (CmObject == NULL)) {
> +    ASSERT (This != NULL);
> +    ASSERT (CmObject != NULL);
> +    return EFI_INVALID_PARAMETER;
> +  }
> +
> +  PlatformRepo = This->PlatRepoInfo;
> +
> +  TotalObjCount = ARRAY_SIZE (PlatformRepo->PciInterruptMapInfo);
> +
> +  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
> +    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciInterruptMapInfo[ObjIndex]) {
> +      CmObject->ObjectId = CmObjectId;
> +      CmObject->Size = sizeof (PlatformRepo->PciInterruptMapInfo[ObjIndex]);
> +      CmObject->Data = (VOID*)&PlatformRepo->PciInterruptMapInfo[ObjIndex];
> +      CmObject->Count = 1;
> +      return EFI_SUCCESS;
> +    }
> +  }
> +
> +  return EFI_NOT_FOUND;
> +}
> +
>   /** Return a list of Configuration Manager object references pointed to by the
>       given input token.
>   
> @@ -1031,6 +1210,18 @@ GetCmObjRefs (
>       CmObject->Count = ARRAY_SIZE (PlatformRepo->CoresLpiRef);
>       return EFI_SUCCESS;
>     }
> +  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciAddressMapRef) {
> +    CmObject->Size = sizeof (PlatformRepo->PciAddressMapRef);
> +    CmObject->Data = (VOID*)&PlatformRepo->PciAddressMapRef;
> +    CmObject->Count = ARRAY_SIZE (PlatformRepo->PciAddressMapRef);
> +    return EFI_SUCCESS;
> +  }
> +  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->PciInterruptMapRef) {
> +    CmObject->Size = sizeof (PlatformRepo->PciInterruptMapRef);
> +    CmObject->Data = (VOID*)&PlatformRepo->PciInterruptMapRef;
> +    CmObject->Count = ARRAY_SIZE (PlatformRepo->PciInterruptMapRef);
> +    return EFI_SUCCESS;
> +  }
>   
>     return EFI_NOT_FOUND;
>   }
> @@ -1320,6 +1511,32 @@ GetArmNameSpaceObject (
>                    );
>         break;
>   
> +    case EArmObjPciAddressMapInfo:
> +      Status = HandleCmObjectRefByToken (
> +                 This,
> +                 CmObjectId,
> +                 PlatformRepo->PciAddressMapInfo,
> +                 sizeof (PlatformRepo->PciAddressMapInfo),
> +                 ARRAY_SIZE (PlatformRepo->PciAddressMapInfo),
> +                 Token,
> +                 GetPciAddressMapInfo,
> +                 CmObject
> +                 );
> +      break;
> +
> +    case EArmObjPciInterruptMapInfo:
> +      Status = HandleCmObjectRefByToken (
> +                 This,
> +                 CmObjectId,
> +                 PlatformRepo->PciInterruptMapInfo,
> +                 sizeof (PlatformRepo->PciInterruptMapInfo),
> +                 ARRAY_SIZE (PlatformRepo->PciInterruptMapInfo),
> +                 Token,
> +                 GetPciInterruptMapInfo,
> +                 CmObject
> +                 );
> +      break;
> +
>       default: {
>         Status = EFI_NOT_FOUND;
>         DEBUG ((
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> index 1bc242bc9d85..5b5e62427f2b 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
> @@ -90,6 +90,21 @@ extern CHAR8  ssdtpci_aml_code[];
>       (WritePolicy << 4)                                                  \
>     )
>   
> +/** PCI space codes.
> +*/
> +#define PCI_SS_CONFIG   0
> +#define PCI_SS_IO       1
> +#define PCI_SS_M32      2
> +#define PCI_SS_M64      3
> +
> +/** Count of PCI address-range mapping struct.
> +*/
> +#define PCI_ADDRESS_MAP_COUNT       3
> +
> +/** Count of PCI device legacy interrupt mapping struct.
> +*/
> +#define PCI_INTERRUPT_MAP_COUNT     4
> +
>   /** A function that prepares Configuration Manager Objects for returning.
>   
>     @param [in]  This        Pointer to the Configuration Manager Protocol.
> @@ -226,6 +241,18 @@ typedef struct PlatformRepositoryInfo {
>     /// PCI configuration space information
>     CM_ARM_PCI_CONFIG_SPACE_INFO          PciConfigInfo;
>   
> +  // PCI address-range mapping references
> +  CM_ARM_OBJ_REF                        PciAddressMapRef[PCI_ADDRESS_MAP_COUNT];
> +
> +  // PCI address-range mapping information
> +  CM_ARM_PCI_ADDRESS_MAP_INFO           PciAddressMapInfo[PCI_ADDRESS_MAP_COUNT];
> +
> +  // PCI device legacy interrupts mapping references
> +  CM_ARM_OBJ_REF                        PciInterruptMapRef[PCI_INTERRUPT_MAP_COUNT];
> +
> +  // PCI device legacy interrupts mapping information
> +  CM_ARM_PCI_INTERRUPT_MAP_INFO         PciInterruptMapInfo[PCI_INTERRUPT_MAP_COUNT];
> +
>     /// GIC MSI Frame information
>     CM_ARM_GIC_MSI_FRAME_INFO             GicMsiFrameInfo;
>   
> diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> index 7ca134d6674b..91bffe8d5d82 100644
> --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> @@ -24,7 +24,6 @@ [Sources]
>     ConfigurationManager.c
>     AslTables/Dsdt.asl
>     AslTables/SsdtJunoUsb.asl
> -  AslTables/SsdtPci.asl
>   
>   [Packages]
>     ArmPkg/ArmPkg.dec

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno
  2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
                   ` (2 preceding siblings ...)
  2022-04-27 14:59 ` [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus PierreGondois
@ 2022-04-29 13:35 ` Ard Biesheuvel
  2022-04-29 13:39   ` PierreGondois
  2022-07-18 16:25 ` Sami Mujawar
  4 siblings, 1 reply; 12+ messages in thread
From: Ard Biesheuvel @ 2022-04-29 13:35 UTC (permalink / raw)
  To: edk2-devel-groups-io, Pierre, Sami Mujawar; +Cc: Ard Biesheuvel

On Wed, 27 Apr 2022 at 17:00, PierreGondois <pierre.gondois@arm.com> wrote:
>
> From: Pierre Gondois <pierre.gondois@arm.com>
>
> DEPENDENCY:
> This patch set relies on a fix sent at:
> https://edk2.groups.io/g/devel/message/89348
>
> The DynamicTablesPkg can now generate the AML description of the
> PCI/CPU topology information. Use these new features and remove
> the static ASL description of the PCI/CPU topology when the
> DynamicTables are used (i.e. when -D DYNAMIC_TABLES_FRAMEWORK is
> provided).
>
> Also provide a small fix for debug printing.
>
> Pierre Gondois (3):
>   Platform/ARM: Juno: Generate ASL description of CPU topology
>   Platform/ARM: Juno: Print debug values in right order
>   Platform/ARM: Juno: Generate ASL description of a PCIe bus
>

Sami, please review this and let me know when it can be merged.

>  .../AslTables/Dsdt.asl                        | 198 --------
>  .../AslTables/SsdtPci.asl                     | 195 --------
>  .../ConfigurationManager.c                    | 425 +++++++++++++++++-
>  .../ConfigurationManager.h                    |  47 +-
>  .../ConfigurationManagerDxe.inf               |   1 -
>  5 files changed, 456 insertions(+), 410 deletions(-)
>  delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
>
> --
> 2.25.1
>
>
>
> ------------
> Groups.io Links: You receive all messages sent to this group.
> View/Reply Online (#89349): https://edk2.groups.io/g/devel/message/89349
> Mute This Topic: https://groups.io/mt/90732523/5717338
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub [ardb+tianocore@kernel.org]
> ------------
>
>

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno
  2022-04-29 13:35 ` [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno Ard Biesheuvel
@ 2022-04-29 13:39   ` PierreGondois
  2022-04-29 13:42     ` Ard Biesheuvel
  0 siblings, 1 reply; 12+ messages in thread
From: PierreGondois @ 2022-04-29 13:39 UTC (permalink / raw)
  To: Ard Biesheuvel, edk2-devel-groups-io, Sami Mujawar; +Cc: Ard Biesheuvel

Hello Ard,
Sami is on leave for the next 2 weeks.
Also, just in case, this patch-set has a dependency on:
https://edk2.groups.io/g/devel/message/89348

Regards,
Pierre

On 4/29/22 15:35, Ard Biesheuvel wrote:
> On Wed, 27 Apr 2022 at 17:00, PierreGondois <pierre.gondois@arm.com> wrote:
>>
>> From: Pierre Gondois <pierre.gondois@arm.com>
>>
>> DEPENDENCY:
>> This patch set relies on a fix sent at:
>> https://edk2.groups.io/g/devel/message/89348
>>
>> The DynamicTablesPkg can now generate the AML description of the
>> PCI/CPU topology information. Use these new features and remove
>> the static ASL description of the PCI/CPU topology when the
>> DynamicTables are used (i.e. when -D DYNAMIC_TABLES_FRAMEWORK is
>> provided).
>>
>> Also provide a small fix for debug printing.
>>
>> Pierre Gondois (3):
>>    Platform/ARM: Juno: Generate ASL description of CPU topology
>>    Platform/ARM: Juno: Print debug values in right order
>>    Platform/ARM: Juno: Generate ASL description of a PCIe bus
>>
> 
> Sami, please review this and let me know when it can be merged.
> 
>>   .../AslTables/Dsdt.asl                        | 198 --------
>>   .../AslTables/SsdtPci.asl                     | 195 --------
>>   .../ConfigurationManager.c                    | 425 +++++++++++++++++-
>>   .../ConfigurationManager.h                    |  47 +-
>>   .../ConfigurationManagerDxe.inf               |   1 -
>>   5 files changed, 456 insertions(+), 410 deletions(-)
>>   delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
>>
>> --
>> 2.25.1
>>
>>
>>
>> ------------
>> Groups.io Links: You receive all messages sent to this group.
>> View/Reply Online (#89349): https://edk2.groups.io/g/devel/message/89349
>> Mute This Topic: https://groups.io/mt/90732523/5717338
>> Group Owner: devel+owner@edk2.groups.io
>> Unsubscribe: https://edk2.groups.io/g/devel/unsub [ardb+tianocore@kernel.org]
>> ------------
>>
>>

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno
  2022-04-29 13:39   ` PierreGondois
@ 2022-04-29 13:42     ` Ard Biesheuvel
  0 siblings, 0 replies; 12+ messages in thread
From: Ard Biesheuvel @ 2022-04-29 13:42 UTC (permalink / raw)
  To: Pierre Gondois; +Cc: edk2-devel-groups-io, Sami Mujawar, Ard Biesheuvel

On Fri, 29 Apr 2022 at 15:39, Pierre Gondois <pierre.gondois@arm.com> wrote:
>
> Hello Ard,
> Sami is on leave for the next 2 weeks.
> Also, just in case, this patch-set has a dependency on:
> https://edk2.groups.io/g/devel/message/89348
>

Yes, that is why I asked him to review: he is the DynamicTablesPkg
maintainer, so he will need to merge the dependency first.

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno
  2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
                   ` (3 preceding siblings ...)
  2022-04-29 13:35 ` [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno Ard Biesheuvel
@ 2022-07-18 16:25 ` Sami Mujawar
  4 siblings, 0 replies; 12+ messages in thread
From: Sami Mujawar @ 2022-07-18 16:25 UTC (permalink / raw)
  To: Pierre.Gondois, devel; +Cc: Ard Biesheuvel, nd

Pushed as bc93dea9b98c..31bd1678a1db

Regards,

Sami Mujawar

On 27/04/2022 03:59 pm, Pierre.Gondois@arm.com wrote:
> From: Pierre Gondois <pierre.gondois@arm.com>
>
> DEPENDENCY:
> This patch set relies on a fix sent at:
> https://edk2.groups.io/g/devel/message/89348
>
> The DynamicTablesPkg can now generate the AML description of the
> PCI/CPU topology information. Use these new features and remove
> the static ASL description of the PCI/CPU topology when the
> DynamicTables are used (i.e. when -D DYNAMIC_TABLES_FRAMEWORK is
> provided).
>
> Also provide a small fix for debug printing.
>
> Pierre Gondois (3):
>    Platform/ARM: Juno: Generate ASL description of CPU topology
>    Platform/ARM: Juno: Print debug values in right order
>    Platform/ARM: Juno: Generate ASL description of a PCIe bus
>
>   .../AslTables/Dsdt.asl                        | 198 --------
>   .../AslTables/SsdtPci.asl                     | 195 --------
>   .../ConfigurationManager.c                    | 425 +++++++++++++++++-
>   .../ConfigurationManager.h                    |  47 +-
>   .../ConfigurationManagerDxe.inf               |   1 -
>   5 files changed, 456 insertions(+), 410 deletions(-)
>   delete mode 100644 Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
>

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2022-07-18 16:25 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-04-27 14:59 [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno PierreGondois
2022-04-27 14:59 ` [PATCH edk2-platforms v1 1/3] Platform/ARM: Juno: Generate ASL description of CPU topology PierreGondois
2022-07-18 13:25   ` Sami Mujawar
2022-07-18 13:30     ` PierreGondois
2022-04-27 14:59 ` [PATCH edk2-platforms v1 2/3] Platform/ARM: Juno: Print debug values in right order PierreGondois
2022-07-18 13:26   ` Sami Mujawar
2022-04-27 14:59 ` [PATCH edk2-platforms v1 3/3] Platform/ARM: Juno: Generate ASL description of a PCIe bus PierreGondois
2022-07-18 14:02   ` Sami Mujawar
2022-04-29 13:35 ` [edk2-devel] [PATCH edk2-platforms v1 0/3] Enable PCI/CPU topology generation for Juno Ard Biesheuvel
2022-04-29 13:39   ` PierreGondois
2022-04-29 13:42     ` Ard Biesheuvel
2022-07-18 16:25 ` Sami Mujawar

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