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Jade platform To: Leif Lindholm CC: devel@edk2.groups.io, patches@amperecomputing.com, vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Michael D Kinney , Ard Biesheuvel , Nate DeSimone References: <20211022061809.31087-1-nhi@os.amperecomputing.com> <20211022061809.31087-2-nhi@os.amperecomputing.com> <20211026111413.5aydr2pgqhqhbsyv@leviathan> From: "Nhi Pham" In-Reply-To: <20211026111413.5aydr2pgqhqhbsyv@leviathan> X-ClientProxiedBy: HKAPR03CA0005.apcprd03.prod.outlook.com (2603:1096:203:c8::10) To PH0PR01MB7287.prod.exchangelabs.com (2603:10b6:510:10a::21) Return-Path: nhi@os.amperecomputing.com MIME-Version: 1.0 Received: from [192.168.1.3] (113.188.173.157) by HKAPR03CA0005.apcprd03.prod.outlook.com (2603:1096:203:c8::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.6 via Frontend Transport; Wed, 3 Nov 2021 09:39:16 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8ab92c38-f419-4ed4-5052-08d99eadcfbf X-MS-TrafficTypeDiagnostic: PH0PR01MB7333: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable On 26/10/2021 18:14, Leif Lindholm wrote: > On Fri, Oct 22, 2021 at 13:17:39 +0700, Nhi Pham wrote: >> From: Vu Nguyen >> >> This commit adds the support for Ampere=E2=80=99s Altra processor-based = Mt. Jade >> platform that provides up to 160 processor cores in a dual socket >> configuration. The essential modules are wired up enough to boot system >> to EDK2 UiApp. >> >> Cc: Thang Nguyen >> Cc: Chuong Tran >> Cc: Phong Vo >> Cc: Leif Lindholm >> Cc: Michael D Kinney >> Cc: Ard Biesheuvel >> Cc: Nate DeSimone >> >> Signed-off-by: Nhi Pham >> Reviewed-by: Leif Lindholm >> --- >> Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec = | 45 ++ >> Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec = | 46 ++ >> Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc = | 677 ++++++++++++++++++++ >> Platform/Ampere/JadePkg/Jade.dsc = | 101 +++ >> Platform/Ampere/JadePkg/Jade.fdf = | 228 +++++++ >> Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.inf = | 41 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf = | 45 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib= .inf | 50 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.in= f | 57 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInter= faceLib.inf | 37 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLi= b.inf | 59 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicati= onLib.inf | 35 + >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf = | 33 + >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.inf= | 35 + >> Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.inf = | 29 + >> Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/Syste= mFirmwareInterfaceLib.inf | 30 + >> Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.inf = | 29 + >> Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h = | 187 ++++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h = | 276 ++++++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h = | 172 +++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h = | 44 ++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h = | 134 ++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceL= ib.h | 282 ++++++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h = | 31 + >> Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h = | 526 +++++++++++++++ >> Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h = | 62 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap= .h | 135 ++++ >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.h = | 70 ++ >> Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c = | 51 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c = | 42 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.= c | 637 ++++++++++++++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib= .c | 137 ++++ >> Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c = | 168 +++++ >> Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMem= ory.c | 256 ++++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInter= faceLib.c | 281 ++++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLi= b.c | 93 +++ >> Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicati= onLib.c | 184 ++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c = | 64 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.c = | 235 +++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.c = | 130 ++++ >> Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c = | 141 ++++ >> Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/Syste= mFirmwareInterfaceLib.c | 328 ++++++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c = | 63 ++ >> Platform/Ampere/JadePkg/JadeBoardSetting.cfg = | 225 +++++++ >> Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper= .S | 45 ++ >> Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.uni = | 13 + >> Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc = | 176 +++++ >> 47 files changed, 6765 insertions(+) >> >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.= h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h >> new file mode 100644 >> index 000000000000..6eecf6422b96 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h >> @@ -0,0 +1,187 @@ >> +/** @file >> + >> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.=
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef PLATFORM_INFO_HOB_H_ >> +#define PLATFORM_INFO_HOB_H_ >> + >> +#include >> +#include >> + >> +#define PLATFORM_INFO_HOB_GUID \ >> + { 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0x76, 0x78, 0x30, 0x32, 0x6d, 0= x79, 0xb4 } } >> + >> +extern EFI_GUID gPlatformInfoHobGuid; >> + >> +// >> +// DIMM type >> +// >> +#define UDIMM 0x00 >> +#define RDIMM 0x01 >> +#define SODIMM 0x02 >> +#define RSODIMM 0x03 >> +#define LRDIMM 0x04 >> +#define NVRDIMM 0x05 >> + >> +// >> +// DIMM status >> +// >> +#define DIMM_NOT_INSTALLED 0x00 >> +#define DIMM_INSTALLED_OPERATIONAL 0x01 // installed and operati= onal >> +#define DIMM_INSTALLED_NONOPERATIONAL 0x02 // installed and non-ope= rational >> +#define DIMM_INSTALLED_FAILED 0x03 // installed and failed >> + >> +typedef struct { >> + UINT32 NumRegion; >> + UINT64 TotalSize; >> + UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION]; >> + UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION]; >> + UINT64 Node[PLATFORM_DRAM_INFO_MAX_REGION]; >> + UINT64 Socket[PLATFORM_DRAM_INFO_MAX_REGION]; >> + UINT32 MaxSpeed; >> + UINT32 McuMask[PLATFORM_CPU_MAX_SOCKET]; >> + UINT32 NvdRegion[PLATFORM_DRAM_INFO_MAX_REGION]; >> + UINT32 NvdimmMode[PLATFORM_CPU_MAX_SOCKET]; >> +} PLATFORM_DRAM_INFO; >> + >> +typedef struct { >> + CHAR8 PartNumber[32]; >> + UINT64 DimmSize; >> + UINT16 DimmMfcId; >> + UINT16 Reserved; >> + UINT8 DimmNrRank; >> + UINT8 DimmType; >> + UINT8 DimmStatus; >> + UINT8 DimmDevType; >> +} PLATFORM_DIMM_INFO; >> + >> +typedef struct { >> + UINT8 Data[512]; >> +} PLATFORM_DIMM_SPD_DATA; >> + >> +typedef struct { >> + PLATFORM_DIMM_INFO Info; >> + PLATFORM_DIMM_SPD_DATA SpdData; >> + UINT32 NodeId; >> +} PLATFORM_DIMM; >> + >> +typedef struct { >> + UINT32 BoardDimmSlots; >> + PLATFORM_DIMM Dimm[PLATFORM_DIMM_INFO_MAX_SLOT]; >> +} PLATFORM_DIMM_LIST; >> + >> +typedef struct { >> + UINT32 EnableMask[4]; >> +} PLATFORM_CLUSTER_EN; >> + >> +// >> +// Algorithm ID defined in pre-UEFI firmware >> +// >> +typedef enum { >> + PLATFORM_ALGORITHM_SHA1 =3D 1, >> + PLATFORM_ALGORITHM_SHA256 >> +} PLATFORM_ALGORITHM_ID; > Ugh. Much as I hate adding more things this late in the day, here is > another non-coding-style compliant enum. Thanks for catching. I will fix it. > (That uncrustify support cannot come soon enough.) > > Can you please go through the set and ensure all enumerations inside > enums definitions are CamelCase? > Since it slipped through until now, I'll leave it up to you if you > want to submit that as a v5, or submit a cleanup patch for the end. > > Another big enum further down this patch. Yes, that's the enum in the=20 Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h. I will fix it by=20 converting this enum to macros. It will not affect other modules. Thanks, Nhi > > / > Leif > >> + >> +// >> +// Platform digest data definition >> +// >> +typedef union { >> + unsigned char Sha1[SHA1_DIGEST_SIZE]; >> + unsigned char Sha256[SHA256_DIGEST_SIZE]; >> +} PLATFORM_TPM_DIGEST; >> + >> +#define MAX_VIRTUAL_PCR_INDEX 0x0002 >> + >> +#pragma pack(1) >> +typedef struct { >> + PLATFORM_ALGORITHM_ID AlgorithmId; >> + struct { >> + PLATFORM_TPM_DIGEST Hash; >> + } VPcr[MAX_VIRTUAL_PCR_INDEX]; // vPCR 0 or 1 >> +} PLATFORM_VPCR_HASH_INFO; >> + >> +typedef struct { >> + UINT8 InterfaceType; // If I/F is CRB then CRB paramete= rs are expected >> + UINT64 InterfaceParametersAddress; // Physical address of interface, = by Value */ >> + UINT64 InterfaceParametersLength; >> + UINT32 SupportedAlgorithmsBitMask; >> + UINT64 EventLogAddress; >> + UINT64 EventLogLength; >> + UINT8 Reserved[3]; >> +} PLATFORM_TPM2_CONFIG_DATA; >> + >> +typedef struct { >> + UINT32 CurrentRequest; >> + UINT32 LastRequest; >> + UINT32 LastRequestStatus; >> +} PLATFORM_TPM2_PPI_REQUEST; >> + >> +typedef struct { >> + UINT64 AddressOfControlArea; >> + UINT64 ControlAreaLength; >> + UINT8 InterruptMode; >> + UINT8 Reserved[3]; >> + UINT32 InterruptNumber; // Should have a= value of zero polling >> + UINT32 SmcFunctionId; // SMC Function = ID >> + UINT64 PpiRequestNotifyAddress; // Doorbell/Inte= rrupt Address >> + PLATFORM_TPM2_PPI_REQUEST *PpiRequest; // PPI Request >> +} PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS; >> + >> +typedef struct { >> + PLATFORM_TPM2_CONFIG_DATA Tpm2ConfigData; >> + PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS Tpm2CrbInterfaceParams; >> + PLATFORM_VPCR_HASH_INFO Tpm2VPcrHashInfo; >> +} PLATFORM_TPM2_INFO; >> +#pragma pack() >> + >> +typedef struct { >> + UINT8 MajorNumber; >> + UINT8 MinorNumber; >> + UINT64 PcpClk; >> + UINT64 CpuClk; >> + UINT64 SocClk; >> + UINT64 AhbClk; >> + UINT64 SysClk; >> + UINT8 CpuInfo[128]; >> + UINT8 CpuVer[32]; >> + UINT8 SmPmProVer[32]; >> + UINT8 SmPmProBuild[32]; >> + PLATFORM_DRAM_INFO DramInfo; >> + PLATFORM_DIMM_LIST DimmList; >> + PLATFORM_CLUSTER_EN ClusterEn[2]; >> + UINT32 FailSafeStatus; >> + UINT32 RcDisableMask[2]; >> + UINT8 ResetStatus; >> + UINT16 CoreVoltage[2]; >> + UINT16 SocVoltage[2]; >> + UINT16 Dimm1Voltage[2]; >> + UINT16 Dimm2Voltage[2]; >> + >> + /* Chip information */ >> + UINT32 ScuProductId[2]; >> + UINT8 MaxNumOfCore[2]; >> + UINT8 Warranty[2]; >> + UINT8 SubNumaMode[2]; >> + UINT8 AvsEnable[2]; >> + UINT32 AvsVoltageMV[2]; >> + UINT8 TurboCapability[2]; >> + UINT32 TurboFrequency[2]; >> + >> + UINT8 SkuMaxTurbo[2]; >> + UINT8 SkuMaxCore[2]; >> + UINT32 AHBCId[2]; >> + >> + /* TPM2 Info */ >> + PLATFORM_TPM2_INFO Tpm2Info; >> + >> + /* 2P link info for RCA0/RCA1 */ >> + UINT8 Link2PSpeed[2]; >> + UINT8 Link2PWidth[2]; >> + >> +} PLATFORM_INFO_HOB; >> + >> +#endif /* PLATFORM_INFO_HOB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.= h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h >> new file mode 100644 >> index 000000000000..9355e6cc7c62 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h >> @@ -0,0 +1,276 @@ >> +/** @file >> + >> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.=
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef AMPERE_CPU_LIB_H_ >> +#define AMPERE_CPU_LIB_H_ >> + >> +#define SUBNUMA_MODE_MONOLITHIC 0 >> +#define SUBNUMA_MODE_HEMISPHERE 1 >> +#define SUBNUMA_MODE_QUADRANT 2 >> + >> +#define MONOLITIC_NUM_OF_REGION 1 >> +#define HEMISPHERE_NUM_OF_REGION 2 >> +#define QUADRANT_NUM_OF_REGION 4 >> +#define SUBNUMA_CPM_REGION_SIZE 4 >> +#define NUM_OF_CPM_PER_MESH_ROW 8 >> + >> +#define CPM_PER_ROW_OFFSET(CpmId) ((CpmId) % NUM_OF_CPM_PER_MESH_R= OW) >> +#define CPM_ROW_NUMBER(CpmId) ((CpmId) / NUM_OF_CPM_PER_MESH_R= OW) >> + >> +#define SOCKET_ID(CpuId) ((CpuId) / (PLATFORM_CPU_MAX_CPM= * PLATFORM_CPU_NUM_CORES_PER_CPM)) >> +#define CLUSTER_ID(CpuId) (((CpuId) / PLATFORM_CPU_NUM_COR= ES_PER_CPM) % PLATFORM_CPU_MAX_CPM) >> + >> + >> +/** >> + Get current CPU frequency. >> + >> + @param Socket Socket index. >> + @return UINTN Current CPU frequency. >> + >> +**/ >> +UINTN >> +EFIAPI >> +CpuGetCurrentFreq ( >> + UINT8 Socket >> + ); >> + >> +/** >> + Get maximum CPU frequency. >> + >> + @param Socket Socket index. >> + @return UINTN Maximum CPU frequency. >> + >> +**/ >> +UINTN >> +EFIAPI >> +CpuGetMaxFreq ( >> + UINT8 Socket >> + ); >> + >> +/** >> + Get CPU voltage. >> + >> + @param Socket Socket index. >> + @return UINT8 CPU voltage. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +CpuGetVoltage ( >> + UINT8 Socket >> + ); >> + >> +/** >> + Get the SubNUMA mode. >> + >> + @return UINT8 The SubNUMA mode. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +CpuGetSubNumaMode ( >> + VOID >> + ); >> + >> +/** >> + Get the number of SubNUMA region. >> + >> + @return UINT8 The number of SubNUMA region. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +CpuGetNumberOfSubNumaRegion ( >> + VOID >> + ); >> + >> +/** >> + Get the SubNUMA node of a CPM. >> + >> + @param SocketId Socket index. >> + @param Cpm CPM index. >> + @return UINT8 The SubNUMA node of a CPM. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +CpuGetSubNumNode ( >> + UINT8 Socket, >> + UINT16 Cpm >> + ); >> + >> +/** >> + Get the number of supported socket. >> + >> + @return UINT8 Number of supported socket. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +GetNumberOfSupportedSockets ( >> + VOID >> + ); >> + >> +/** >> + Get the number of active socket. >> + >> + @return UINT8 Number of active socket. >> + >> +**/ >> +UINT8 >> +EFIAPI >> +GetNumberOfActiveSockets ( >> + VOID >> + ); >> + >> +/** >> + Get the number of active CPM per socket. >> + >> + @param SocketId Socket index. >> + @return UINT16 Number of CPM. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetNumberOfActiveCPMsPerSocket ( >> + UINT8 SocketId >> + ); >> + >> +/** >> + Get the number of configured CPM per socket. >> + >> + @param SocketId Socket index. >> + @return UINT16 Number of configured CPM. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetNumberOfConfiguredCPMs ( >> + UINT8 SocketId >> + ); >> + >> +/** >> + Set the number of configured CPM per socket. >> + >> + @param SocketId Socket index. >> + @param NumberOfCPMs Number of CPM to be configured. >> + @return EFI_SUCCESS Operation succeeded. >> + @return Others An error has occurred. >> + >> +**/ >> +EFI_STATUS >> +EFIAPI >> +SetNumberOfConfiguredCPMs ( >> + UINT8 SocketId, >> + UINT16 NumberOfCPMs >> + ); >> + >> +/** >> + Get the maximum number of core per socket. This number >> + should be the same for all sockets. >> + >> + @return UINT16 Maximum number of core. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetMaximumNumberOfCores ( >> + VOID >> + ); >> + >> +/** >> + Get the maximum number of CPM per socket. This number >> + should be the same for all sockets. >> + >> + @return UINT32 Maximum number of CPM. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetMaximumNumberOfCPMs ( >> + VOID >> + ); >> + >> +/** >> + Get the number of active cores of a sockets. >> + >> + @return UINT16 Number of active core. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetNumberOfActiveCoresPerSocket ( >> + UINT8 SocketId >> + ); >> + >> +/** >> + Get the number of active cores of all socket. >> + >> + @return UINT16 Number of active core. >> + >> +**/ >> +UINT16 >> +EFIAPI >> +GetNumberOfActiveCores ( >> + VOID >> + ); >> + >> +/** >> + Check if the logical CPU is enabled or not. >> + >> + @param CpuId The logical Cpu ID. Started from 0. >> + @return BOOLEAN TRUE if the Cpu enabled >> + FALSE if the Cpu disabled. >> + >> +**/ >> +BOOLEAN >> +EFIAPI >> +IsCpuEnabled ( >> + UINT16 CpuId >> + ); >> + >> + >> +/** >> + Check if the slave socket is present >> + >> + @return BOOLEAN TRUE if the Slave Cpu is present >> + FALSE if the Slave Cpu is not present >> + >> +**/ >> +BOOLEAN >> +EFIAPI >> +IsSlaveSocketAvailable ( >> + VOID >> + ); >> + >> +/** >> + Check if the slave socket is active >> + >> + @return BOOLEAN TRUE if the Slave CPU Socket is active. >> + FALSE if the Slave CPU Socket is not active. >> + >> +**/ >> +BOOLEAN >> +EFIAPI >> +IsSlaveSocketActive ( >> + VOID >> + ); >> + >> +/** >> + Check if the CPU product ID is Ac01 >> + @return BOOLEAN TRUE if the Product ID is Ac01 >> + FALSE otherwise. >> + >> +**/ >> +BOOLEAN >> +EFIAPI >> +IsAc01Processor ( >> + VOID >> + ); >> + >> +#endif /* AMPERE_CPU_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterf= aceLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLi= b.h >> new file mode 100644 >> index 000000000000..2750487f3e96 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.= h >> @@ -0,0 +1,172 @@ >> +/** @file >> + The library implements the hardware Mailbox (Doorbell) interface for = communication >> + between the Application Processor (ARMv8) and the System Control Proc= essors (SMpro/PMpro). >> + >> + A transfer to SMpro/PMpro is performed on a doorbell channel which is= implemented through >> + hardware doorbell registers. Each transfer can be up to 12 bytes long= , including 4 bytes >> + for the message and two 4 bytes for additional data. >> + >> + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef MAILBOX_INTERFACE_LIB_H_ >> +#define MAILBOX_INTERFACE_LIB_H_ >> + >> +#define SMPRO_DB_MAX 8 >> +#define PMPRO_DB_MAX 8 >> +#define NUMBER_OF_DOORBELLS_PER_SOCKET (SMPRO_DB_MAX + PMPRO_DB_MAX) >> + >> +// >> +// General address offset of Doorbell registers >> +// >> +#define DB_IN_REG_OFST 0x00000000 // Doorbell In >> +#define DB_DIN0_REG_OFST 0x00000004 // Doorbell In Data >> +#define DB_DIN1_REG_OFST 0x00000008 // Doorbell In Data >> +#define DB_OUT_REG_OFST 0x00000010 // Doorbell Out >> +#define DB_DOUT0_REG_OFST 0x00000014 // Doorbell Out Data >> +#define DB_DOUT1_REG_OFST 0x00000018 // Doorbell Out Data >> +#define DB_STATUS_REG_OFST 0x00000020 // Doorbell Interrupt Stat= us >> +#define DB_STATUS_MASK_REG_OFST 0x00000024 // Doorbell Interrupt Stat= us Mask >> + >> +// >> +// List of supported doorbells >> +// >> +typedef enum { >> + // >> + // PMpro Doorbells >> + // >> + PMproDoorbellChannel0 =3D 0, >> + PMproDoorbellChannel1, >> + PMproDoorbellChannel2, >> + PMproDoorbellChannel3, >> + PMproDoorbellChannel4, >> + PMproDoorbellChannel5, >> + PMproDoorbellChannel6, >> + PMproDoorbellChannel7, >> + // >> + // SMpro Doorbells >> + // >> + SMproDoorbellChannel0 =3D PMPRO_DB_MAX, >> + SMproDoorbellChannel1, >> + SMproDoorbellChannel2, >> + SMproDoorbellChannel3, >> + SMproDoorbellChannel4, >> + SMproDoorbellChannel5, >> + SMproDoorbellChannel6, >> + SMproDoorbellChannel7 >> +} DOORBELL_CHANNELS; >> + >> +#pragma pack(1) >> +// >> +// Mailbox Message Data >> +// >> +// A mailbox transaction supports up to 12 bytes long, >> +// including 4 bytes for message and two 4 bytes for extended data. >> +// >> +typedef struct { >> + UINT32 Data; >> + UINT32 ExtendedData[2]; >> +} MAILBOX_MESSAGE_DATA; >> + >> +#pragma pack() >> + >> +// >> +// Timeout configuration when waiting for an doorbell interrupt status >> +// >> +#define MAILBOX_POLL_TIMEOUT_US 10000000 >> +#define MAILBOX_POLL_INTERVAL_US 1000 >> +#define MAILBOX_POLL_COUNT (MAILBOX_POLL_TIMEOUT_US / MAILBOX_POL= L_INTERVAL_US) >> + >> +/** >> + Get the base address of a doorbell. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Doorbell Doorbell channel for communication with= the SMpro/PMpro. >> + >> + @retval UINT32 The base address of the doorbell. >> + The returned value is 0 indicate that t= he input parameters are invalid. >> + >> +**/ >> +UINTN >> +EFIAPI >> +MailboxGetDoorbellAddress ( >> + IN UINT8 Socket, >> + IN DOORBELL_CHANNELS Doorbell >> + ); >> + >> +/** >> + Get the interrupt number of a doorbell. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Doorbell Doorbell channel for communication with= the SMpro/PMpro. >> + >> + @retval UINT32 The interrupt number. >> + The returned value is 0 indicate that t= he input parameters are invalid. >> + >> +**/ >> +UINT32 >> +EFIAPI >> +MailboxGetDoorbellInterruptNumber ( >> + IN UINT8 Socket, >> + IN DOORBELL_CHANNELS Doorbell >> + ); >> + >> +/** >> + Read a message via the hardware Doorbell interface. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Doorbell Doorbell channel for communication with= the SMpro/PMpro. >> + @param[out] Message Pointer to the Mailbox message. >> + >> + @retval EFI_SUCCESS Read the message successfully. >> + @retval EFI_TIMEOUT Timeout occurred when waiting for avail= able message in the mailbox. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxRead ( >> + IN UINT8 Socket, >> + IN DOORBELL_CHANNELS Doorbell, >> + OUT MAILBOX_MESSAGE_DATA *Message >> + ); >> + >> +/** >> + Write a message via the hardware Doorbell interface. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Doorbell Doorbel channel for communication with = the SMpro/PMpro. >> + @param[in] Message Pointer to the Mailbox message. >> + >> + @retval EFI_SUCCESS Write the message successfully. >> + @retval EFI_TIMEOUT Timeout occurred when waiting for ackno= wledge signal from the mailbox. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxWrite ( >> + IN UINT8 Socket, >> + IN DOORBELL_CHANNELS Doorbell, >> + IN MAILBOX_MESSAGE_DATA *Message >> + ); >> + >> +/** >> + Unmask the Doorbell interrupt status. >> + >> + @param Socket Active socket index. >> + @param Doorbell Doorbel channel for communication with the SMpro/PM= pro. >> + >> + @retval EFI_SUCCESS Unmask the Doorbell interrupt successf= ully. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxUnmaskInterrupt ( >> + IN UINT8 Socket, >> + IN UINT16 Doorbell >> + ); >> + >> +#endif /* MAILBOX_INTERFACE_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicati= onLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.= h >> new file mode 100644 >> index 000000000000..fbbf66e5187d >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h >> @@ -0,0 +1,44 @@ >> +/** @file >> + >> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.=
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef MM_COMMUNICATION_LIB_H_ >> +#define MM_COMMUNICATION_LIB_H_ >> + >> +/** >> + Communicates with a registered handler. >> + >> + This function provides an interface to send and receive messages to t= he >> + Standalone MM environment in UEFI PEI phase. >> + >> + @param[in, out] CommBuffer A pointer to the buffer to convey >> + into MMRAM. >> + @param[in, out] CommSize The size of the data buffer being >> + passed in. This is optional. >> + >> + @retval EFI_SUCCESS The message was successfully post= ed. >> + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. >> + @retval EFI_BAD_BUFFER_SIZE The buffer size is incorrect for = the MM >> + implementation. If this error is >> + returned, the MessageLength field= in >> + the CommBuffer header or the inte= ger >> + pointed by CommSize are updated t= o reflect >> + the maximum payload size the >> + implementation can accommodate. >> + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter >> + or CommSize parameter, if not omi= tted, >> + are in address range that cannot = be >> + accessed by the MM environment >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MmCommunicationCommunicate ( >> + IN OUT VOID *CommBuffer, >> + IN OUT UINTN *CommSize OPTIONAL >> + ); >> + >> +#endif /* MM_COMMUNICATION_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h = b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h >> new file mode 100644 >> index 000000000000..e8521ce336a3 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h >> @@ -0,0 +1,134 @@ >> +/** @file >> + >> + The non-volatile parameter layout in SPI-NOR is shown below. There is >> + two copies. The master copy is changeable by the user. The Last Known >> + copy is handled by the fail safe future. It is a last know bootable c= opy. >> + >> + --------------------------- >> + | Master Copy | 16KB >> + | Pre-boot parameters | >> + --------------------------- >> + | Master Copy | 16KB >> + | Pre-boot parameters | >> + | w/o failsafe support | >> + --------------------------- >> + | Master Copy | >> + | Manufactory & | 32KB >> + | Users parameters | >> + --------------------------- >> + | Last Known Copy | 16KB >> + | Pre-boot parameters | >> + --------------------------- >> + | | 16KB >> + --------------------------- >> + | Last Known Copy | >> + | Manufactory & | 32KB >> + | Users parameters | >> + --------------------------- >> + >> + As each non-volatile parameter requires 8 bytes, there is a total of = 8K >> + parameters. >> + >> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.=
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef NV_PARAM_LIB_H_ >> +#define NV_PARAM_LIB_H_ >> + >> +#define NV_PARAM_MAX_SIZE (64 * 1024) >> +#define NV_PARAM_ENTRYSIZE 8 >> + >> +#define NV_PERM_ALL 0xFFFF /* Allowed for all */ >> +#define NV_PERM_ATF 0x0001 /* Allowed for EL3 code */ >> +#define NV_PERM_OPTEE 0x0004 /* Allowed for secure El1 */ >> +#define NV_PERM_BIOS 0x0008 /* Allowed for EL2 non-secure */ >> +#define NV_PERM_MANU 0x0010 /* Allowed for manufactory interface */ >> +#define NV_PERM_BMC 0x0020 /* Allowed for BMC interface */ >> + >> +#define NVPARAM_SIZE 0x8 >> + >> +/** >> + Retrieve a non-volatile parameter. >> + >> + NOTE: If you need a signed value, cast it. It is expected that the >> + caller will carry the correct permission over various call sequences. >> + >> + @param[in] Param Parameter ID to retrieve >> + @param[in] ACLRd Permission for read operation. >> + @param[out] Val Pointer to an UINT32 to the return va= lue. >> + >> + @retval EFI_SUCCESS Operation succeeded. >> + @retval EFI_ACCESS_DENIED Permission not allowed. >> + @retval EFI_DEVICE_ERROR Service is unavailable. >> + @retval EFI_INVALID_PARAMETER Val is NULL or return status is inval= id. >> + @retval EFI_NOT_FOUND NVParam entry is not set. >> +**/ >> +EFI_STATUS >> +NVParamGet ( >> + IN UINT32 Param, >> + IN UINT16 ACLRd, >> + OUT UINT32 *Val >> + ); >> + >> +/** >> + Set a non-volatile parameter. >> + >> + NOTE: If you have a signed value, cast to unsigned. If the parameter = has >> + not being created before, the provied permission is used to create th= e >> + parameter. Otherwise, it is checked for access. It is expected that t= he >> + caller will carry the correct permission over various call sequences. >> + >> + @param[in] Param Parameter ID to set >> + @param[in] ACLRd Permission for read operation. >> + @param[in] ACLWr Permission for write operation. >> + @param[in] Val Unsigned int value to set. >> + >> + @retval EFI_SUCCESS Operation succeeded. >> + @retval EFI_ACCESS_DENIED Permission not allowed. >> + @retval EFI_DEVICE_ERROR Service is unavailable. >> + @retval EFI_INVALID_PARAMETER Return status is invalid. >> +**/ >> +EFI_STATUS >> +NVParamSet ( >> + IN UINT32 Param, >> + IN UINT16 ACLRd, >> + IN UINT16 ACLWr, >> + IN UINT32 Val >> + ); >> + >> +/** >> + Clear a non-volatile parameter. >> + >> + NOTE: It is expected that the caller will carry the correct permissio= n >> + over various call sequences. >> + >> + @param[in] Param Parameter ID to set >> + @param[in] ACLWr Permission for write operation. >> + >> + @retval EFI_SUCCESS Operation succeeded. >> + @retval EFI_ACCESS_DENIED Permission not allowed. >> + @retval EFI_DEVICE_ERROR Service is unavailable. >> + @retval EFI_INVALID_PARAMETER Return status is invalid. >> +**/ >> +EFI_STATUS >> +NVParamClr ( >> + IN UINT32 Param, >> + IN UINT16 ACLWr >> + ); >> + >> +/** >> + Clear all non-volatile parameters >> + >> + @retval EFI_SUCCESS Operation succeeded. >> + @retval EFI_DEVICE_ERROR Service is unavailable. >> + @retval EFI_INVALID_PARAMETER Return status is invalid. >> +**/ >> +EFI_STATUS >> +NVParamClrAll ( >> + VOID >> + ); >> + >> +#endif /* NV_PARAM_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwar= eInterfaceLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmw= areInterfaceLib.h >> new file mode 100644 >> index 000000000000..ce96c2a6b4b6 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterf= aceLib.h >> @@ -0,0 +1,282 @@ >> +/** @file >> + Provides functions for communication with System Firmware (SMpro/PMpr= o) >> + via interfaces like Mailbox. >> + >> + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef SYSTEM_FIRMWARE_INTERFACE_LIB_H_ >> +#define SYSTEM_FIRMWARE_INTERFACE_LIB_H_ >> + >> +// >> +// Common mailbox message format >> +// Bit 31:28 - Message type >> +// Bit 27:24 - Message subtype >> +// Bit 23:16 - Message control byte >> +// Bit 15:0 - Message data specific >> +// >> +#define MAILBOX_MESSAGE_TYPE_SHIFT 28 >> +#define MAILBOX_MESSAGE_SUBTYPE_SHIFT 24 >> +#define MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT 16 >> + >> +#define COMMON_MESSAGE_ENCODE(Type,Subtype,Control) \ >> + ( \ >> + ((Type) << MAILBOX_MESSAGE_TYPE_SHIFT) | \ >> + ((Subtype) << MAILBOX_MESSAGE_SUBTYPE_SHIFT) | \ >> + ((Control) << MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT) \ >> + ) >> + >> +#define MAILBOX_MESSAGE_CONTROL_URGENT BIT7 >> +#define MAILBOX_MESSAGE_CONTROL_TYPICAL 0 >> + >> +// >> +// Mailbox Message Types >> +// >> +#define MAILBOX_MESSAGE_TYPE_DEBUG 0x00 >> +#define MAILBOX_MESSAGE_TYPE_ADDRESS 0x05 >> +#define MAILBOX_MESSAGE_TYPE_USER 0x06 >> + >> +// >> +// Mailbox Message Type 0x00 - Debug message >> +// >> +#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_READ 0x01 >> +#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_WRITE 0x02 >> + >> +// >> +// Debug message data format >> +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE >> +// Bit 15:0 - Store lower 16-bit of the upper 64-bit address >> +// >> +#define MAILBOX_DEBUG_MESSAGE_ENCODE(Subtype,Address) \ >> + ( \ >> + (COMMON_MESSAGE_ENCODE ( \ >> + MAILBOX_MESSAGE_TYPE_DEBUG, \ >> + (Subtype), \ >> + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ >> + ((Address) & 0xFFFF) \ >> + ) >> + >> +// >> +// Mailbox Message Type 0x05 - Address message >> +// >> +#define MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC 0x03 >> + >> +// >> +// Address message data format >> +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE >> +// Bit 15:8 - Message Parameter >> +// Bit 7:4 - Address message control bit >> +// 0x4: 256 alignment >> +// 0x0: No alignment >> +// Bit 3:0 - Unused >> +// >> +#define MAILBOX_ADDRESS_MESSAGE_ENCODE(Subtype,Param,Align) \ >> + ( \ >> + (COMMON_MESSAGE_ENCODE ( \ >> + MAILBOX_MESSAGE_TYPE_ADDRESS, \ >> + (Subtype), \ >> + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ >> + ((Param) << 8) | \ >> + ((Align) << 4) \ >> + ) >> + >> +#define MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE(Subtype,Param,Align) \ >> + ( \ >> + (COMMON_MESSAGE_ENCODE ( \ >> + MAILBOX_MESSAGE_TYPE_ADDRESS, \ >> + (Subtype), \ >> + MAILBOX_MESSAGE_CONTROL_URGENT)) | \ >> + ((Param) << 8) | \ >> + ((Align) << 4) \ >> + ) >> + >> +#define MAILBOX_ADDRESS_256_ALIGNMENT 0x4 >> +#define MAILBOX_ADDRESS_NO_ALIGNMENT 0x0 >> + >> +#define MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC 0x01 >> + >> +#define MAILBOX_URGENT_CPPC_MESSAGE \ >> + ( \ >> + MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE ( \ >> + MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC, \ >> + MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC, \ >> + MAILBOX_ADDRESS_256_ALIGNMENT) \ >> + ) >> + >> +#define MAILBOX_TYPICAL_PCC_MESSAGE \ >> + ( \ >> + MAILBOX_ADDRESS_MESSAGE_ENCODE ( \ >> + MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC, \ >> + 0, \ >> + MAILBOX_ADDRESS_256_ALIGNMENT) \ >> + ) >> + >> +// >> +// Mailbox Message Type 0x06 - User message >> +// >> +#define MAILBOX_USER_MESSAGE_SUBTYPE_SET_CONFIGURATION 0x02 >> +#define MAILBOX_USER_MESSAGE_SUBTYPE_BOOT_PROGRESS 0x06 >> +#define MAILBOX_USER_MESSAGE_SUBTYPE_TRNG_PROXY 0x07 >> + >> +// >> +// User message data format >> +// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE >> +// Bit 15:8 - Message Parameter 0 >> +// Bit 7:0 - Message Parameter 1 >> +// >> +#define MAILBOX_USER_MESSAGE_ENCODE(Subtype,Param0,Param1) \ >> + ( \ >> + (COMMON_MESSAGE_ENCODE ( \ >> + MAILBOX_MESSAGE_TYPE_USER, \ >> + (Subtype), \ >> + MAILBOX_MESSAGE_CONTROL_TYPICAL)) | \ >> + ((Param0) << 8) | \ >> + (Param1) \ >> + ) >> + >> +// >> +// Parameters for True RNG Proxy Message >> +// Param0: 1 - Get a random number >> +// Param1: Unused >> +// >> +#define MAILBOX_TRNG_PROXY_GET_RANDOM_NUMBER 1 >> + >> +// >> +// Parameters for Boot Progress >> +// Param0: 1 - Set boot state >> +// Param1: Boot stage value >> +// 0x08: BL33/UEFI Stage >> +// >> +#define MAILBOX_BOOT_PROGRESS_COMMAND_SET 1 >> +#define MAILBOX_BOOT_PROGRESS_STAGE_UEFI 8 >> + >> +// >> +// Parameters for Set Configuration >> +// Param0: Configuration type >> +// 20: Turbo configuration >> +// Param1: Unused >> +// >> +#define MAILBOX_SET_CONFIGURATION_TURBO 20 >> + >> +/** >> + Read a register which is not accessible from the non-secure world >> + by sending a mailbox message to the SMpro processor. >> + >> + Note that not all addresses are allowed. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Address A 64-bit register address to be read. >> + @param[out] Value A pointer to the read value. >> + >> + @retval EFI_SUCCESS Read the register successfully. >> + @retval EFI_UNSUPPORTED The register is not allowed. >> + @retval Otherwise Errors returned from MailboxWrite/Mailb= oxRead() functions. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgRegisterRead ( >> + IN UINT8 Socket, >> + IN UINTN Address, >> + OUT UINT32 *Value >> + ); >> + >> +/** >> + Write a value to a register which is not accessible from the non-secu= re world >> + by sending a mailbox message to the SMpro processor. >> + >> + Note that not all addresses are allowed. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Address A 64-bit register address to be written. >> + @param[in] Value The value to be written to the register. >> + >> + @retval EFI_SUCCESS Write the register successfully. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + @retval Otherwise Errors returned from the MailboxWrite() func= tion. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgRegisterWrite ( >> + IN UINT8 Socket, >> + IN UINTN Address, >> + IN UINT32 Value >> + ); >> + >> +/** >> + Set the PCC shared Memory Address to service handlers in the System C= ontrol Processors, >> + using for communication between the System Firmware and OSPM. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Doorbell Doorbell index which is numbered like DO= ORBELL_CHANNELS. >> + @param[in] AddressAlign256 Enable/Disable 256 alignment. >> + @param[in] Address The shared memory address. >> + >> + @retval EFI_SUCCESS Set the shared memory address successfu= lly. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + @retval Otherwise Errors returned from the MailboxWrite()= functions. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgSetPccSharedMem ( >> + IN UINT8 Socket, >> + IN UINT8 Doorbell, >> + IN BOOLEAN AddressAlign256, >> + IN UINTN Address >> + ); >> + >> +/** >> + The True RNG is provided by the SMpro processor. This function is to = send a mailbox >> + message to the SMpro to request a 64-bit random number. >> + >> + @param[out] Buffer A pointer to the read 64-bit random num= ber. >> + >> + @retval EFI_SUCCESS The operation succeeds. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + @retval Otherwise Errors returned from the MailboxWrite/M= ailboxRead() functions. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgGetRandomNumber64 ( >> + OUT UINT8 *Buffer >> + ); >> + >> +/** >> + Report the UEFI boot progress to the SMpro. >> + >> + @param[in] Socket Active socket index. >> + @param[in] BootStatus The status of the UEFI boot. >> + @param[in] Checkpoint The UEFI Checkpoint value. >> + >> + @retval EFI_SUCCESS Set the boot progress successfully. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + @retval Otherwise Errors returned from the MailboxWrite()= functions. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgSetBootProgress ( >> + IN UINT8 Socket, >> + IN UINT8 BootStatus, >> + IN UINT32 Checkpoint >> + ); >> + >> +/** >> + Configure the Turbo (Max Performance) mode. >> + >> + @param[in] Socket Active socket index. >> + @param[in] Enable Enable/Disable the Turbo (Max performanc= e) mode. >> + >> + @retval EFI_SUCCESS Configure the Turbo successfully. >> + @retval EFI_INVALID_PARAMETER A parameter is invalid. >> + @retval Otherwise Errors returned from the MailboxWrite()= functions. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +MailboxMsgTurboConfig ( >> + IN UINT8 Socket, >> + IN BOOLEAN Enable >> + ); >> + >> +#endif /* SYSTEM_FIRMWARE_INTERFACE_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h b/S= ilicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h >> new file mode 100644 >> index 000000000000..b478986cb032 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h >> @@ -0,0 +1,31 @@ >> +/** @file >> + RNG (Random Number Generator) Library that uses Hardware RNG in SMpro= . >> + >> + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef TRNG_LIB_H_ >> +#define TRNG_LIB_H_ >> + >> +/** >> + Generates a random number by using Hardware RNG in SMpro. >> + >> + @param[out] Buffer Buffer to receive the random number. >> + @param[in] BufferSize Number of bytes in Buffer. >> + >> + @retval EFI_SUCCESS The random value was returned successfu= lly. >> + @retval EFI_DEVICE_ERROR A random value could not be retrieved >> + due to a hardware or firmware error. >> + @retval EFI_INVALID_PARAMETER Buffer is NULL or BufferSize is zero. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +GenerateRandomNumbers ( >> + OUT UINT8 *Buffer, >> + IN UINTN BufferSize >> + ); >> + >> +#endif /* TRNG_LIB_H_ */ >> diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silico= n/Ampere/AmpereAltraPkg/Include/NVParamDef.h >> new file mode 100644 >> index 000000000000..eabddf609b01 >> --- /dev/null >> +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h >> @@ -0,0 +1,526 @@ >> +/** @file >> + >> + The non-volatile parameter layout in SPI-NOR is shown below. There is >> + two copies. The master copy is changeable by the user. The Last Known >> + copy is handled by the fail safe future. It is a last know bootable c= opy. >> + >> + --------------------------- >> + | Master Copy | 16KB >> + | Pre-boot parameters | >> + --------------------------- >> + | Master Copy | 16KB >> + | Pre-boot parameters | >> + | w/o failsafe support | >> + --------------------------- >> + | Master Copy | >> + | Manufactory & | 32KB >> + | Users parameters | >> + --------------------------- >> + | Last Known Copy | 16KB >> + | Pre-boot parameters | >> + --------------------------- >> + | | 16KB >> + --------------------------- >> + | Last Known Copy | >> + | Manufactory & | 32KB >> + | Users parameters | >> + --------------------------- >> + >> + As each non-volatile parameter requires 8 bytes, there is a total of = 8K >> + parameters. >> + >> + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.=
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef NVPARAMDEF_H_ >> +#define NVPARAMDEF_H_ >> + >> +typedef enum { >> + /* >> + * SoC validation pre-boot non-volatile setting >> + * >> + * These parameters will reset to default value on failsafe. >> + * They are not used in production life cycle. >> + */ >> + NV_PREBOOT_PARAM_START =3D 0x000000, >> + NV_SI_PCP_VDMC =3D (1 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_FAILSAFE_RETRY =3D (2 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_PPR_EN =3D (3 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_RESERVED0 =3D (4 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_RESERVED1 =3D (5 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_LOG_LEVEL =3D (6 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_RESERVED2 =3D (7 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_RD_DBI_EN =3D (8 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_WR_DBI_EN =3D (9 * 8) + NV_PREBOOT_PA= RAM_START, >> + NV_SI_DDR_RETRY_EN =3D (10 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_BANK_HASH_EN =3D (11 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RESERVED3 =3D (12 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RCD_PARITY_EN =3D (13 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WRPATH_CLK_GATE_EN =3D (14 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_IOCAL_MARGIN =3D (15 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTR_S_MARGIN =3D (16 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTR_L_MARGIN =3D (17 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTR_CS_MARGIN =3D (18 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTW_S_MARGIN =3D (19 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTW_L_MARGIN =3D (20 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTW_CS_MARGIN =3D (21 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTW_S_MARGIN =3D (22 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTW_L_MARGIN =3D (23 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RTW_CS_MARGIN =3D (24 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTR_S_MARGIN =3D (25 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTR_L_MARGIN =3D (26 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WTR_CS_MARGIN =3D (27 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PARITY_EN =3D (28 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_SLC_DISABLE =3D (29 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_SLC_SIZE =3D (30 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_SLC_SCRUB =3D (31 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CCIX_DISABLE =3D (32 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_ESM_RESERVED =3D (33 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_CAL_MODE =3D (34 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_RAS_TEST_EN =3D (35 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_EYE_SCREEN_TEST_EN =3D (36 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_EYE_MASK_RD_MARGIN =3D (37 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_EYE_MASK_WR_MARGIN =3D (38 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RDODT_ON_MARGIN =3D (39 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RDODT_OFF_MARGIN =3D (40 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WRODT_ON_MARGIN =3D (41 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WRODT_OFF_MARGIN =3D (42 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_SLC_OCM_EN =3D (43 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_ESM_WIDTH =3D (44 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_TM2_DISABLE =3D (45 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CPUPLL_FREQ_MHZ =3D (46 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_ERR_INJECT_MASK_SK0 =3D (47 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_ERR_INJECT_MASK_SK1 =3D (48 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CXG_DISABLE_EARLY_COMPACK =3D (49 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CXG_ENABLE_SAME_ADDR_COMP_ORDER =3D (50 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_TURNAROUND_CONTROL =3D (51 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_HIT_TURNAROUND_CONTROL =3D (52 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_QOS_CLASS_CONTROL =3D (53 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_ESCALATION_CONTROL =3D (54 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_QV_CONTROL_31_00 =3D (55 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_QV_CONTROL_63_32 =3D (56 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_CREDIT_CONTROL =3D (57 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WRITE_PRIORITY_CONTROL_31_00 =3D (58 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_WRITE_PRIORITY_CONTROL_63_32 =3D (59 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_31_00 =3D (60 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_63_32 =3D (61 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_ATF_FAILURE_FAILSAFE =3D (62 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_UEFI_FAILURE_FAILSAFE =3D (63 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_STRIPE_DECODE =3D (64 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_DEBUG_CTRL =3D (65 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CXG_RA_DEVNR_ORD_WFC_DIS =3D (66 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD =3D (67 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD_AC =3D (68 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_INIT_UPDATE_CONFIG =3D (69 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_UPDATE_CONTROL =3D (70 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_PROFILE_EN =3D (71 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_PCIE_PHY_SETTING =3D (72 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_CAL_THRESHOLD =3D (73 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_PHY_CAL_INTERVAL_CNT =3D (74 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_RESERVED =3D (75 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_S0_RHS_RCA_EN =3D (76 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_S1_RHS_RCA_EN =3D (77 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_2P_DPLL =3D (78 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_2P_ALI_CFG =3D (79 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_2P_ALI_CFG_LINK_RETRAIN =3D (80 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_2P_ALI_CFG_CRC =3D (81 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RT_CONTROL_31_00 =3D (82 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_RT_CONTROL_63_32 =3D (83 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_DDR_TIMEOUT_CONTROL =3D (84 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CPU_LPI_FREQ_DISABLE =3D (85 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD =3D (86 * 8) + NV_PREBOOT_P= ARAM_START, >> + NV_PMPRO_REGION1_LOAD_START =3D NV_SI_SLC_DISABLE, >> + NV_PMPRO_REGION1_LOAD_END =3D NV_SI_CPU_LPI_FREQ_ENER= GY_THRSHLD, >> + /* NOTE: Add before NV_PREBOOT_PARAM_MAX and increase its value */ >> + NV_PREBOOT_PARAM_MAX =3D (86 * 8) + NV_PREBOOT_P= ARAM_START, >> + >> + /* >> + * Manufactory non-volatile memory >> + * >> + * These parameters will reset to default value on failsafe. >> + */ >> + NV_MANU_PARAM_START =3D 0x004000, >> + NV_SI_DDR_VMARGIN =3D (0 * 8) + NV_MANU_PARAM= _START, >> + NV_PMPRO_REGION2_LOAD_START =3D NV_SI_DDR_VMARGIN, >> + NV_SI_SOC_VMARGIN =3D (1 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_AVS_VMARGIN =3D (2 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_TPC_TM1_MARGIN =3D (3 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_TPC_TM2_MARGIN =3D (4 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_TPC_FREQ_THROTTLE =3D (5 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_T_LTLM_EN =3D (6 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_T_LTLM_THRSHLD =3D (7 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_T_GTLM_THRSHLD =3D (8 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_P_LM_EN =3D (9 * 8) + NV_MANU_PARAM= _START, >> + NV_SI_P_LM_THRSHLD =3D (10 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_TPC_OVERTEMP_ISR_DISABLE =3D (11 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_VPP_VMARGIN =3D (12 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PMPRO_FAILURE_FAILSAFE =3D (13 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_FAILSAFE_DISABLE =3D (14 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLIMIT_APM_DS_PERCENTAGE =3D (15 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLIMIT_APM_EP_MS =3D (16 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP =3D (17 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CPU_LPI_RESERVED0 =3D (18 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CPU_LPI_RESERVED1 =3D (19 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CCIX_OPT_CONFIG =3D (20 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_MESH_FREQ_MARGIN =3D (21 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_MESH_TURBO_EN =3D (22 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PWR_HEADROOM_WATT =3D (23 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_EXTRA_PCP_VOLT_MV =3D (24 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CPU_LPI_HYST_CNT =3D (25 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DVFS_VOLT_INC_STEP_MV =3D (26 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DVFS_VOLT_DEC_STEP_MV =3D (27 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLIMIT_APM_TEMP_THLD =3D (28 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLIMIT_APM_EN =3D (29 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_VDM_EN =3D (30 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_VDM_VMARGIN_MV =3D (31 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_EN =3D (32 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_SOCKET =3D (33 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_MCU_MASK =3D (34 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_RANK_MASK =3D (35 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_SLICE_MASK =3D (36 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_BIT_MASK =3D (37 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_X_PARAM =3D (38 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_Y_PARAM =3D (39 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_X_LEFT =3D (40 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_X_RIGHT =3D (41 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_X_STEP =3D (42 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_Y_BOTTOM =3D (43 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_Y_TOP =3D (44 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_Y_STEP =3D (45 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_START_ADDR_LO =3D (46 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_START_ADDR_UP =3D (47 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_SIZE =3D (48 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_THREAD_CNT =3D (49 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_SCREEN =3D (50 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_PLT_RSVD =3D (51 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN =3D (52 * 8) + NV_MANU_PARA= M_START, >> + NS_SI_DVFS_TCAL_F_LIMIT =3D (53 * 8) + NV_MANU_PARA= M_START, >> + NS_SI_DVFS_TCAL_T_LIMIT =3D (54 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CCIX_DIAG_CTRL1 =3D (55 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_CCIX_DIAG_CTRL2 =3D (56 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_EN =3D (57 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD =3D (58 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD =3D (59 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD =3D (60 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD =3D (61 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV =3D (62 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_PERIOD_SEC =3D (63 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV =3D (64 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_ALTRAMAX_ICCMAX_EN =3D (65 * 8) + NV_MANU_PARA= M_START, >> + NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD =3D (66 * 8) + NV_MANU_PARA= M_START, >> + NV_PMPRO_REGION2_LOAD_END =3D NV_SI_MESH_TURBO_ACTIVI= TY_THRESHOLD, >> + /* NOTE: Add before NV_MANU_PARAM_MAX and increase its value */ >> + NV_MANU_PARAM_MAX =3D (66 * 8) + NV_MANU_PARA= M_START, >> + >> + /* >> + * User non-volatile memory >> + * >> + * These parameters will reset to default value on failsafe. >> + */ >> + NV_USER_PARAM_START =3D 0x008000, >> + NV_SI_S0_PCP_ACTIVECPM_0_31 =3D (0 * 8) + NV_USER_PARAM= _START, >> + NV_SI_S0_PCP_ACTIVECPM_32_63 =3D (1 * 8) + NV_USER_PARAM= _START, >> + NV_SI_S1_PCP_ACTIVECPM_0_31 =3D (2 * 8) + NV_USER_PARAM= _START, >> + NV_SI_S1_PCP_ACTIVECPM_32_63 =3D (3 * 8) + NV_USER_PARAM= _START, >> + NV_SI_WDT_BIOS_EXP_MINS =3D (4 * 8) + NV_USER_PARAM= _START, >> + NV_SI_DDR_CE_RAS_THRESHOLD =3D (5 * 8) + NV_USER_PARAM= _START, >> + NV_SI_DDR_CE_RAS_INTERVAL =3D (6 * 8) + NV_USER_PARAM= _START, >> + NV_SI_DDR_SPEED =3D (7 * 8) + NV_USER_PARAM= _START, >> + NV_SI_DDR_SCRUB_EN =3D (8 * 8) + NV_USER_PARAM= _START, >> + NV_SI_DDR_ECC_MODE =3D (9 * 8) + NV_USER_PARAM= _START, >> + NV_SI_S0_RCA_PCI_DEVMAP =3D (10 * 8) + NV_USER_PARA= M_START, >> + NV_SI_S0_RCB_PCI_DEVMAP =3D (11 * 8) + NV_USER_PARA= M_START, >> + NV_SI_S1_RCA_PCI_DEVMAP =3D (12 * 8) + NV_USER_PARA= M_START, >> + NV_SI_S1_RCB_PCI_DEVMAP =3D (13 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_ERRCTRL =3D (14 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_REFRESH_GRANULARITY =3D (15 * 8) + NV_USER_PARA= M_START, >> + NV_SI_SUBNUMA_MODE =3D (16 * 8) + NV_USER_PARA= M_START, >> + NV_SI_ERRATUM_1542419_WA =3D (17 * 8) + NV_USER_PARA= M_START, >> + NV_SI_NEAR_ATOMIC_DISABLE =3D (18 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_SLAVE_32BIT_MEM_EN =3D (19 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPUECTLR_EL1_0_31 =3D (20 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPUECTLR_EL1_32_63 =3D (21 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HARDWARE_EINJ =3D (22 * 8) + NV_USER_PARA= M_START, >> + NV_SI_2P_CE_RAS_THRESHOLD =3D (23 * 8) + NV_USER_PARA= M_START, >> + NV_SI_2P_CE_RAS_INTERVAL =3D (24 * 8) + NV_USER_PARA= M_START, >> + NV_SI_RAS_BERT_ENABLED =3D (25 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HNF_AUX_CTL_0_31 =3D (26 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HNF_AUX_CTL_32_63 =3D (27 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPM_CE_RAS_THRESHOLD =3D (28 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPM_CE_RAS_INTERVAL =3D (29 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK =3D (30 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK =3D (31 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_WR_BACK_EN =3D (32 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK =3D (33 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK =3D (34 * 8) + NV_USER_PARA= M_START, >> + NV_SI_LINK_ERR_THRESHOLD =3D (35 * 8) + NV_USER_PARA= M_START, >> + NV_SI_SEC_WDT_BIOS_EXP_MINS =3D (36 * 8) + NV_USER_PARA= M_START, >> + NV_SI_NVDIMM_MODE =3D (37 * 8) + NV_USER_PARA= M_START, >> + NV_SI_RAS_SDEI_ENABLED =3D (38 * 8) + NV_USER_PARA= M_START, >> + NV_SI_NVDIMM_PROV_MASK_S0 =3D (39 * 8) + NV_USER_PARA= M_START, >> + NV_SI_NVDIMM_PROV_MASK_S1 =3D (40 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_ZQCS_EN =3D (41 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_CRC_MODE =3D (42 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXG_RA_AUX_CTL_0_31 =3D (43 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXG_RA_AUX_CTL_32_63 =3D (44 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK =3D (45 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK =3D (46 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXLA_AUX_CTL_0_31 =3D (47 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXLA_AUX_CTL_32_63 =3D (48 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK =3D (49 * 8) + NV_USER_PARA= M_START, >> + NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK =3D (50 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DDR_LOW_POWER_CFG =3D (51 * 8) + NV_USER_PARA= M_START, >> + NV_SI_ALERT_DIMM_SHUTDOWN_EN =3D (52 * 8) + NV_USER_PARA= M_START, >> + NV_SI_DFS_EN =3D (53 * 8) + NV_USER_PARA= M_START, >> + NV_SI_RAS_PCIE_AER_FW_FIRST =3D (54 * 8) + NV_USER_PARA= M_START, >> + NV_SI_RAS_DRAM_EINJ_NOTRIGGER =3D (55 * 8) + NV_USER_PARA= M_START, >> + NV_SI_RAS_AEST_PROC_EN =3D (56 * 8) + NV_USER_PARA= M_START, >> + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN =3D (57 * 8) + NV_USER_PARA= M_START, >> + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN =3D (58 * 8) + NV_USER_PARA= M_START, >> + NV_SI_2P_RESERVED0 =3D (59 * 8) + NV_USER_PARA= M_START, >> + NV_SI_2P_RESERVED1 =3D (60 * 8) + NV_USER_PARA= M_START, >> + NV_SI_2P_RESERVED2 =3D (61 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HCR_EL2_CTL_LOW =3D (62 * 8) + NV_USER_PARA= M_START, >> + NV_SI_HCR_EL2_CTL_HIGH =3D (63 * 8) + NV_USER_PARA= M_START, >> + NV_SI_ESM_SPEED =3D (64 * 8) + NV_USER_PARA= M_START, >> + /* NOTE: Add before NV_USER_PARAM_MAX and increase its value */ >> + NV_USER_PARAM_MAX =3D (64 * 8) + NV_USER_PARA= M_START, >> + NV_PMPRO_REGION3_LOAD_START =3D NV_USER_PARAM_START, >> + NV_PMPRO_REGION3_LOAD_END =3D NV_USER_PARAM_MAX, >> + >> + /* >> + * Non-volatile board read-only setting >> + * >> + * These parameters do not support failsafe and will always read >> + * from its location. Please note that the physical base address >> + * location for board setting is not the same as above region. This >> + * allows packaging these board setting along with the firmware >> + * image itself. See SPI-NOR flash layout design for more info. >> + * >> + * Please note that script will parse these and generate >> + * board setting. The keyword "Default: " is used to provide >> + * the default value. >> + */ >> + NV_BOARD_PARAM_START =3D 0x00C000, >> + NV_SI_RO_BOARD_VENDOR =3D (0 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x0000CD3A - Follow BMC FRU format */ >> + NV_PMPRO_REGION4_LOAD_START =3D NV_SI_RO_BOARD_VENDOR, >> + NV_SI_RO_BOARD_TYPE =3D (1 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x00000000 - Follow BMC FRU format */ >> + NV_SI_RO_BOARD_REV =3D (2 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x00000000 Follow BMC FRU format */ >> + NV_SI_RO_BOARD_CFG =3D (3 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x00000000 Follow BMC FRU format */ >> + NV_SI_RO_BOARD_S0_DIMM_AVAIL =3D (4 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x0000FFFF */ >> + NV_SI_RO_BOARD_S1_DIMM_AVAIL =3D (5 * 8) + NV_BOARD_PARA= M_START, /* Default: 0x0000FFFF */ >> + NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ =3D (6 * 8) + NV_BOARD_PARA= M_START, /* Default: 33000 */ >> + NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ =3D (7 * 8) + NV_BOARD_PARA= M_START, /* Default: 33000 */ >> + NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ =3D (8 * 8) + NV_BOARD_PARA= M_START, /* Default: 10000 */ >> + NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ =3D (9 * 8) + NV_BOARD_PARA= M_START, /* Default: 10000 */ >> + NV_SI_RO_BOARD_TPM_LOC =3D (10 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_I2C0_FREQ_KHZ =3D (11 * 8) + NV_BOARD_PAR= AM_START, /* Default: 400 */ >> + NV_SI_RO_BOARD_I2C1_FREQ_KHZ =3D (12 * 8) + NV_BOARD_PAR= AM_START, /* Default: 400 */ >> + NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ =3D (13 * 8) + NV_BOARD_PAR= AM_START, /* Default: 400 */ >> + NV_SI_RO_BOARD_I2C3_FREQ_KHZ =3D (14 * 8) + NV_BOARD_PAR= AM_START, /* Default: 400 */ >> + NV_SI_RO_BOARD_I2C9_FREQ_KHZ =3D (15 * 8) + NV_BOARD_PAR= AM_START, /* Default: 400 */ >> + NV_SI_RO_BOARD_2P_CFG =3D (16 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0xFFFFFF01 */ >> + NV_SI_RO_BOARD_S0_RCA0_CFG =3D (17 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_S0_RCA1_CFG =3D (18 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_S0_RCA2_CFG =3D (19 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000004 */ >> + NV_SI_RO_BOARD_S0_RCA3_CFG =3D (20 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000004 */ >> + NV_SI_RO_BOARD_S0_RCB0_LO_CFG =3D (21 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S0_RCB0_HI_CFG =3D (22 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S0_RCB1_LO_CFG =3D (23 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S0_RCB1_HI_CFG =3D (24 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S0_RCB2_LO_CFG =3D (25 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S0_RCB2_HI_CFG =3D (26 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_S0_RCB3_LO_CFG =3D (27 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_S0_RCB3_HI_CFG =3D (28 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCA0_CFG =3D (29 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_S1_RCA1_CFG =3D (30 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_S1_RCA2_CFG =3D (31 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S1_RCA3_CFG =3D (32 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00030003 */ >> + NV_SI_RO_BOARD_S1_RCB0_LO_CFG =3D (33 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_S1_RCB0_HI_CFG =3D (34 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCB1_LO_CFG =3D (35 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCB1_HI_CFG =3D (36 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_S1_RCB2_LO_CFG =3D (37 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCB2_HI_CFG =3D (38 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCB3_LO_CFG =3D (39 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_S1_RCB3_HI_CFG =3D (40 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00020002 */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_P0 =3D (41 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000001 */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_P1 =3D (42 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000002 */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_P2 =3D (43 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_P3 =3D (44 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0x00000004 */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_M1 =3D (45 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0xFFFFFFFF */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_M2 =3D (46 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0xFFFFFFFE */ >> + NV_SI_RO_BOARD_T_LTLM_DELTA_M3 =3D (47 * 8) + NV_BOARD_PAR= AM_START, /* Default: 0xFFFFFFFD */ >> + NV_SI_RO_BOARD_P_LM_PID_P =3D (48 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_P_LM_PID_I =3D (49 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD =3D (50 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD =3D (51 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_P_LM_PID_D =3D (52 * 8) + NV_BOARD_PAR= AM_START, >> + NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST =3D (53 * 8) + NV_BOARD_PAR= AM_START, >> + /* >> + * NV_SI_RO_BOARD_TPM_ALG_ID: 0=3DDefault to SHA256, 1=3DSHA1, 2=3DSH= A256 >> + * Any other value will lead to default digest. >> + */ >> + NV_SI_RO_BOARD_TPM_ALG_ID =3D (54 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000002 */ >> + NV_SI_RO_BOARD_DDR_SPEED_GRADE =3D (55 * 8) + NV_B= OARD_PARAM_START, /* Default: 3200 */ >> + NV_SI_RO_BOARD_DDR_S0_RTT_WR =3D (56 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x20020000 */ >> + NV_SI_RO_BOARD_DDR_S1_RTT_WR =3D (57 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x20020000 */ >> + NV_SI_RO_BOARD_DDR_S0_RTT_NOM =3D (58 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x31060177 */ >> + NV_SI_RO_BOARD_DDR_S1_RTT_NOM =3D (59 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x31060177 */ >> + NV_SI_RO_BOARD_DDR_S0_RTT_PARK =3D (60 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x30060070 */ >> + NV_SI_RO_BOARD_DDR_S1_RTT_PARK =3D (61 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x30060070 */ >> + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC =3D (62 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x000000 */ >> + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC =3D (63 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x000000 */ >> + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC =3D (64 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x000000 */ >> + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC =3D (65 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x000000 */ >> + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC =3D (66 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x044C0CCC */ >> + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC =3D (67 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x084C0CCC */ >> + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC =3D (68 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x04130333 */ >> + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC =3D (69 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x08130333 */ >> + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC =3D (70 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x01130333 */ >> + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC =3D (71 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x02230333 */ >> + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC =3D (72 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x01430333 */ >> + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC =3D (73 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x02830333 */ >> + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC =3D (74 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x055EDEED */ >> + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC =3D (75 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x0A5DEDDE */ >> + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC =3D (76 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x055B7BB7 */ >> + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC =3D (77 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x0A57B77B */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC =3D (78 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x5 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC =3D (79 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x90DD90 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC =3D (80 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x5 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC =3D (81 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x90DD90 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC =3D (82 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x5 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC =3D (83 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x90DD90 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC =3D (84 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x5 */ >> + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC =3D (85 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x90DD90 */ >> + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC =3D (86 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x24 */ >> + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC =3D (87 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x001A001A */ >> + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC =3D (88 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x50 */ >> + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC =3D (89 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00240020 */ >> + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT =3D (90 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x02800280 */ >> + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT =3D (91 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x90909090 */ >> + NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT =3D (92 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT =3D (93 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00C000C0 */ >> + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ =3D (94 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ =3D (95 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ =3D (96 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ =3D (97 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE =3D (98 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x02010201 */ >> + NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE =3D (99 * 8) + NV_B= OARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO =3D (100 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL =3D (101 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS =3D (102 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x01050106 */ >> + NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD =3D (103 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x5F4 */ >> + NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE =3D (104 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x0 */ >> + NV_SI_RO_BOARD_S0_PCIE_CLK_CFG =3D (105 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA4_CFG =3D (106 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S0_RCA5_CFG =3D (107 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S0_RCA6_CFG =3D (108 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S0_RCA7_CFG =3D (109 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020003 */ >> + NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET =3D (110 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET =3D (111 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET =3D (112 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET =3D (113 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET =3D (114 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET =3D (115 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET =3D (116 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET =3D (117 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET =3D (118 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET =3D (119 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET =3D (120 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET =3D (121 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET =3D (122 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET =3D (123 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET =3D (124 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET =3D (125 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET =3D (126 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET =3D (127 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET =3D (128 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET =3D (129 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET =3D (130 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET =3D (131 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET =3D (132 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET =3D (133 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET =3D (134 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET =3D (135 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET =3D (136 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET =3D (137 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET =3D (138 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET =3D (139 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET =3D (140 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET =3D (141 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_PCIE_CLK_CFG =3D (142 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA4_CFG =3D (143 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S1_RCA5_CFG =3D (144 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S1_RCA6_CFG =3D (145 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020202 */ >> + NV_SI_RO_BOARD_S1_RCA7_CFG =3D (146 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x02020003 */ >> + NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET =3D (147 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET =3D (148 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET =3D (149 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET =3D (150 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET =3D (151 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET =3D (152 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET =3D (153 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET =3D (154 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET =3D (155 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET =3D (156 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET =3D (157 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET =3D (158 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET =3D (159 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET =3D (160 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET =3D (161 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET =3D (162 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET =3D (163 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET =3D (164 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET =3D (165 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET =3D (166 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET =3D (167 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET =3D (168 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET =3D (169 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET =3D (170 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET =3D (171 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET =3D (172 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET =3D (173 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET =3D (174 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x57575757 */ >> + NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD =3D (175 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000003 */ >> + NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL =3D (176 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x000001A4 */ >> + NV_SI_RO_BOARD_SX_PHY_CFG_SETTING =3D (177 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_DDR_PHY_DC_CLK =3D (178 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00018000 */ >> + NV_SI_RO_BOARD_DDR_PHY_DC_DATA =3D (179 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x80018000 */ >> + NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET =3D (180 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET =3D (181 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET =3D (182 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET =3D (183 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET =3D (184 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET =3D (185 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET =3D (186 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET =3D (187 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD =3D (188 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00550055 */ >> + NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US =3D (189 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000064 */ >> + NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV =3D (190 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000005 */ >> + NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN =3D (191 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000001 */ >> + NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME =3D (192 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000002 */ >> + NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US =3D (193 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000005 */ >> + NV_SI_RO_BOARD_PCIE_AER_FW_FIRST =3D (194 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS =3D (195 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_TPM_DISABLE =3D (196 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN =3D (197 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN =3D (198 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN =3D (199 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_PCIE_HP_DISABLE =3D (200 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT =3D (201 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS =3D (202 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_CUST_SPM_LOCATION =3D (203 * 8) + NV_= BOARD_PARAM_START, >> + NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW =3D (204 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_SI_RO_BOARD_RAS_DDR_CE_TH1 =3D (205 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x000001F4 */ >> + NV_SI_RO_BOARD_RAS_DDR_CE_TH2 =3D (206 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00001388 */ >> + NV_SI_RO_BOARD_RAS_DDR_CE_THC =3D (207 * 8) + NV_= BOARD_PARAM_START, /* Default: 0x00000000 */ >> + NV_PMPRO_REGION4_LOAD_END =3D NV_SI_RO_BOARD_= RAS_DDR_CE_THC, >> + /* NOTE: Add before NV_BOARD_PARAM_MAX and increase its value */ >> + NV_BOARD_PARAM_MAX =3D (207 * 8) + NV_= BOARD_PARAM_START, >> +} NVPARAM; >> + >> +#endif /* NVPARAMDEF_H_ */