From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EE0DF20945040 for ; Wed, 5 Apr 2017 19:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491446845; x=1522982845; h=date:from:cc:sender:to:subject:message-id:mime-version; bh=+v9ERDM18L6UhRTX7zC18CIP+epKUv2w8Q+ytAI/4yc=; b=CC3OUpAGzWkZpDRgis2/7LFUGBtbW+rCtxiMQ02TKxYqFgokVvQs9XPb vLs7MrrLE4LF/TmTy0+KEaARqPcGKA==; Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Apr 2017 19:47:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,282,1488873600"; d="scan'208";a="244832639" Received: from shwdeopenpsi011.ccr.corp.intel.com (HELO SHWDEOPENPSI011.local) ([10.239.9.2]) by fmsmga004.fm.intel.com with SMTP; 05 Apr 2017 19:47:24 -0700 Date: Thu, 6 Apr 2017 10:47:25 +0800 From: lushifex CC: david.wei@intel.com; Sender: lushifex To: edk2-devel@lists.01.org Message-ID: X-Mailer: TortoiseGit MIME-Version: 1.0 Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Add SATA initialization. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 02:47:26 -0000 Content-Type: text/plain; Add additional SATA initialization code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex --- .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c | 3 + .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScSata.c | 91 +++++++++++++++++++++- 2 files changed, 93 insertions(+), 1 deletion(-) diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c index 9620dac..3fb37ea 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c @@ -660,6 +660,9 @@ ScOnEndOfDxe ( gBS->CloseEvent (Event); BxtSeries = GetBxtSeries (); + if (BxtSeries == BxtP) { + ConfigureSataDxe (mScPolicy); + } AcpiBaseAddr = (UINT16) PcdGet16 (PcdScAcpiIoPortBaseAddress); PmcBase = PMC_BASE_ADDRESS; FuncDisableReg = MmioRead32 (PmcBase + R_PMC_FUNC_DIS); diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScSata.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScSata.c index 63c2b88..c6d83e9 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScSata.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScSata.c @@ -1,7 +1,7 @@ /** @file Perform related functions for SC Sata in DXE phase. - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -15,4 +15,93 @@ #include +/** + Perform the remaining configuration on SC SATA to perform device detection + at end of Dxe, then set the SATA SPD and PxE corresponding, and set the Register Lock + + @param[in] ScPolicy The SC Policy instance + + @retval EFI_SUCCESS The function completed successfully + +**/ +EFI_STATUS +ConfigureSataDxe ( + IN SC_POLICY_HOB *ScPolicy + ) +{ + EFI_STATUS Status; + SC_SATA_CONFIG *SataConfig; + UINTN PciSataRegBase; + UINT16 SataPortsEnabled; + UINT32 DwordReg; + UINTN Index; + + DEBUG ((DEBUG_INFO, "ConfigureSataDxe() Start\n")); + Status = GetConfigBlock ((VOID *) ScPolicy, &gSataConfigGuid, (VOID *) &SataConfig); + ASSERT_EFI_ERROR (Status); + + // + // SATA PCS: Enable the port in any of below condition: + // i.) Hot plug is enabled + // ii.) A device is attached + // iii.) Test mode is enabled + // iv.) Configured as eSATA port + // + PciSataRegBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_SC, + PCI_DEVICE_NUMBER_SATA, + PCI_FUNCTION_NUMBER_SATA + ); + SataPortsEnabled = 0; + DwordReg = MmioRead32 (PciSataRegBase + 0x94); + DEBUG ((DEBUG_INFO, "PCS = 0x%x\n", DwordReg)); + for (Index = 0; Index < SC_MAX_SATA_PORTS; Index++) { + if ((SataConfig->PortSettings[Index].HotPlug == TRUE) || + (DwordReg & (BIT16 << Index)) || + (SataConfig->TestMode == TRUE) || + (SataConfig->PortSettings[Index].External == TRUE)) { + SataPortsEnabled |= (SataConfig->PortSettings[Index].Enable << Index); + } + } + DEBUG ((DEBUG_INFO, "SataPortsEnabled = 0x%x\n", SataPortsEnabled)); + + // + // MAP - Port Mapping Register + // PCI Offset: 90h - 93h + // Value [23:16] Port Disabled + // [7:0] Port Clock Disabled + // + MmioOr32 (PciSataRegBase + R_SATA_MAP, (UINT32) ((~SataPortsEnabled << N_SATA_MAP_SPD) & B_SATA_MAP_SPD)); + DEBUG ((DEBUG_INFO, "MAP = 0x%x\n", MmioRead32 (PciSataRegBase + R_SATA_MAP))); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PciSataRegBase + R_SATA_MAP), + 1, + (VOID *) (UINTN) (PciSataRegBase + R_SATA_MAP) + ); + + MmioOr16 (PciSataRegBase + 0x94, SataPortsEnabled); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint16, + (UINTN) (PciSataRegBase + 0x94), + 1, + (VOID *) (UINTN) (PciSataRegBase + 0x94) + ); + + // + // Step 14 + // Program SATA PCI offset 9Ch [31] to 1b + // + MmioOr32 ((UINTN) (PciSataRegBase + R_SATA_SATAGC), BIT31); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PciSataRegBase + R_SATA_SATAGC), + 1, + (VOID *) (UINTN) (PciSataRegBase + R_SATA_SATAGC) + ); + DEBUG ((DEBUG_INFO, "SATAGC = 0x%x\n", MmioRead32 (PciSataRegBase + R_SATA_SATAGC))); + DEBUG ((DEBUG_INFO, "ConfigureSataDxe() End\n")); + + return EFI_SUCCESS; +} -- 2.7.0.windows.1