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X-Microsoft-Antispam-Message-Info: B8eLU3Bl2ohQtudfswH72huAR7E0OTQaaDhUFLCZ8QCX5HITX0TgrbKxqEe44nSe2NoeG5E3+5YSi6nhUK6YpS/rhisZKuEW0qRWl5XhN9fXhuFsXT+xi1+UZfnfX+zBL+hUG4aePed2iuVUKHCA7TX55l+Bg2FfiPfyCTiE2mHC8RA0xf3Z5PjTXQc4AMD02NX8taVJEkHbucpEElMBQxeGdPWacdvHL+5o8IyjPPdWaFpCXdWBd/21JCWrbuKaPLTkaBkedbe83z67/vMGofKvvwC2dOWNSNrwet2bsIqZRVEdxV/SVJNVLlVgGoCcpOzMfW+3CggfGZ6vF3DV9dk7S3WAHQ/mh9OY1Efr0vgyOkcqL6hR3jRSJohxsRbq0MtrKff45cckj2kitE/l5QPUjn9IWROCgUXt1RY1pDaOxJh24lATXIaXnlsDu8nP82zY0C4+Ghy3sUtLJ2ivSwkNWS8qkutEWIIn64j3fD0YsBcxlnpxGppBjQGzXXnUgxT9nWjMl3JQ3WRsAawMQA== X-MS-Exchange-AntiSpam-MessageData: vcYYyKL6hGVyJszvqQjsX1ne20AeA7Vmjh/WxP2oZCPQSuzGIMwwoEobwNZXtOGMBzujxAM73yIefZ5ic8Ka1+mbrTxl4ezlkkyAiBKZwfs07TFG4zy66sU/0KFVjnqd300tyo3gKFxetxvNZRriYw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1bbd7beb-744b-4663-9246-08d7a9c645a1 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2020 23:02:13.5258 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HNQhGBo0nC8Z87GY0rcrfbNkdIKgr0hNY2bdTv9k7pIIPfG0LmM79yYbY+O9FSZxUA+ox5Jxh2/3YNxb5c5P/A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3930 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support an MSR_PROT NAE event. Parse the instruction that generated the #VC exception to determine whether it is RDMSR or WRMSR, setting the required register register values in the GHCB and creating the proper SW_EXIT_INFO1 value in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/AMDSevVcCommon.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c index 90541c9a0390..25bcc34218d7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c @@ -294,6 +294,51 @@ UnsupportedExit ( return Status; } +STATIC +UINT64 +MsrExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 = 0; + + switch (*(InstructionData->OpCodes + 1)) { + case 0x30: // WRMSR + ExitInfo1 = 1; + Ghcb->SaveArea.Rax = Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rdx = Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + /* Fallthrough */ + case 0x32: // RDMSR + Ghcb->SaveArea.Rcx = Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + break; + default: + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + Status = VmgExit (Ghcb, SvmExitMsr, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (!ExitInfo1) { + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rdx = Ghcb->SaveArea.Rdx; + } + + return 0; +} + #define IOIO_TYPE_STR (1 << 2) #define IOIO_TYPE_IN 1 #define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) @@ -558,6 +603,10 @@ DoVcCommon ( NaeExit = IoioExit; break; + case SvmExitMsr: + NaeExit = MsrExit; + break; + default: NaeExit = UnsupportedExit; } -- 2.17.1