From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (NAM10-DM6-obe.outbound.protection.outlook.com [40.107.93.78]) by mx.groups.io with SMTP id smtpd.web11.2033.1680850739223876688 for ; Thu, 06 Apr 2023 23:58:59 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amd.com header.s=selector1 header.b=et9z+xub; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.93.78, mailfrom: abdullateef.attar@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CBmP6qdoOR+26X87D21hQj5r63IitXb1+WtQfVmP1MetlCu8Kzv+H1j1TRvfhp9ckiGy2KWb7J9v1sOZrFFYzpTxnMAUxsAhflowbLLl6HErbEOXnyCVd61oLuWdQQpt1Et54GgM/nYurXiaGbhlOEyTj4fnAq7xKnDtsezzi5qQDMPx/Rew4/mHRuILU4xf9UZXn29Dr59DZkFax2v7BBorf8UswZVXqXlZA/lxPFH+txvP27AzdwgW1X/93wbqFJo8hoAblluDGatyfMCgZmpEk+2aYhOiJZTLuGzz8QWFV9uxu249ScSg+O8zEZNBvua7KETyNySEH5K6xEJeLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oU0Qpk8UCzx1Orz9PCT8+RmeL6lLxJORjr8kPFLjhJo=; b=jJzfvvJ6b3O0upjoOjByFs0dhcJTpgDJ9sur2lsuUZ3xexPtDeRM9S08uFv8gLKxSh+IvWDBs84rUw1xn3FcEnV95oZgP/P/BxcT1WIagsh1wRU6u8V6P4YY7Koml75O7cOCCSIjhHoypDeSgv5N6scQnEa4PoLP88dxi8smbAQXdcuo6z4xT0wQu/450HvXrNYTNZ/Vh78jlcJoyLmpYR8Xaw5vGgIiJyTPkf3EYF4WVcw5twF+D48180RdwH/eOwyx7neWDd6Yd+EyIIXdqe6xSE/bmziM6uEUUvwKvk/WNcc0pvk48BoC8lGzyRaa3tNj4eSDO2q+gTXo/paRcg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oU0Qpk8UCzx1Orz9PCT8+RmeL6lLxJORjr8kPFLjhJo=; b=et9z+xubfYU/U6+xkQTw/X97aQtws3asr9Q5yVoBPqzlBhqLLcn0VlPGnrasoCnrwaXx1yWVabKiNQpL4m79oqG/Xjjgq0QKTY3aWxLGIM8RSy9OTT+CuKCCOx5vSV3E+1c0UiY10ie5ZL3TaCtnJpHB+S5jc7GDmhwtBBsFIso= Received: from BN8PR12CA0008.namprd12.prod.outlook.com (2603:10b6:408:60::21) by DM4PR12MB7648.namprd12.prod.outlook.com (2603:10b6:8:104::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6277.34; Fri, 7 Apr 2023 06:58:54 +0000 Received: from BN8NAM11FT047.eop-nam11.prod.protection.outlook.com (2603:10b6:408:60:cafe::a) by BN8PR12CA0008.outlook.office365.com (2603:10b6:408:60::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6277.31 via Frontend Transport; Fri, 7 Apr 2023 06:58:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT047.mail.protection.outlook.com (10.13.177.220) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.19 via Frontend Transport; Fri, 7 Apr 2023 06:58:54 +0000 Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 7 Apr 2023 01:58:50 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 6 Apr 2023 23:58:29 -0700 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 7 Apr 2023 01:58:27 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [PATCH v7 7/8] UefiCpuPkg: Implements SmmSmramSaveStateLib for Intel Date: Fri, 7 Apr 2023 12:28:00 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT047:EE_|DM4PR12MB7648:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ae3b36a-88a8-4024-4ce8-08db37358cf8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iIUGFhGjfY23jo/5pvbKnFkaOrBgFg63w9rM1TSbzTiCn77dQd+T2vZRdRCxz8CzwWZJ3iPSnPuUjMXjW7gXrWZiw6KExBqYyqMcHyfLTc0sInrN5YktK3BqJTKzW7VQP5/REte44ch73GtZL6ySJOCaLH1OuLZJO01ha0/DtnbiOVu8FHCzeUzTqiASKcdCDoxbDpmJLP6QCjnbEGkH/KFoXGLb6bQAhh9ZQ8No/dypoLT440QiZqHbWj6sCcUOijQAxPJnuSay9GdGsukblwPuhU5KQuPEW79uKJFdgcLxeIKN0cEbGX1+v3opGehntmHalSAaQr/SEFs2SIffEOwiO8xkGCixVAFr27LN2kYcWe0QFfxwoMGhy5ImQVID0wzLnD6tDV2BUbUmmLlctF/OJdC3DxWpu3q/0fasiXQwZxF7v2eViPcACNxzjOmOocEMPFBiC5QDFNuaL3NSIZ5cQkh5zdtOQLx3owfI08DHmb1DvfNMgryO4RKAJBCu89K/T/hAl02Nt62xr6CKa0jgVIg6OIvEEN5MV158JYC+6wuCthd+NYgARLf60+BJxNqakVWYZwXzITRBhMDUbk56ajLGAOSe7ooSzJFz3OGNqAtoK4Pxqrq/9avQkUJhtNCEUMe+kIy4uLmEqlTFE5Jp96qRcHVz1S/786cGl9hRUwCf5QHNKwQrOcyuA9UgPgMWNv7k0nxoOV92rJ56thAAfOxN2CEk2kOcdvoXeEAVTsoYJ1oqtO0K82PO/o8K X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(39860400002)(136003)(346002)(376002)(451199021)(36840700001)(46966006)(40470700004)(36756003)(316002)(19627235002)(41300700001)(70586007)(70206006)(8676002)(6916009)(4326008)(966005)(7696005)(54906003)(478600001)(40480700001)(82310400005)(5660300002)(8936002)(2906002)(30864003)(36860700001)(356005)(82740400003)(81166007)(186003)(6666004)(26005)(426003)(336012)(2616005)(47076005)(83380400001)(40460700003)(213903007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2023 06:58:54.0465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ae3b36a-88a8-4024-4ce8-08db37358cf8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7648 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Implements SmmSmramSaveStateLib library interfaces to read and write save state registers for Intel processor family. Moves Intel and AMD common functionality to common area. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar --- UefiCpuPkg/UefiCpuPkg.dsc | 4 + .../IntelSmmSmramSaveStateLib.inf | 28 ++ .../SmmSmramSaveStateLib/SmramSaveState.h | 1 - .../SmmSmramSaveStateLib/AmdSmramSaveState.c | 32 -- .../IntelSmramSaveState.c | 359 ++++++++++++++++++ .../SmramSaveStateCommon.c | 116 +++++- 6 files changed, 503 insertions(+), 37 deletions(-) create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmramSa= veStateLib.inf create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmramSaveS= tate.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 043eb2dbc1b1..df555fdf32de 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -102,6 +102,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER] HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuE= xceptionHandlerLib.inf SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmram= SaveStateLib.inf + SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmr= amSaveStateLib.inf =20 [LibraryClasses.common.MM_STANDALONE] MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/Standalon= eMmServicesTableLib.inf @@ -170,6 +171,7 @@ [Components.IA32, Components.X64] FILE_GUID =3D D1D74FE9-7A4E-41D3-A0B3-67F13AD34D94 SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLibStm.inf + SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSm= mSmramSaveStateLib.inf } UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { @@ -177,6 +179,7 @@ [Components.IA32, Components.X64] SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeat= uresLib.inf SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/S= mmCpuPlatformHookLibNull.inf + SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmS= mramSaveStateLib.inf } UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf @@ -194,6 +197,7 @@ [Components.IA32, Components.X64] UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultR= eportLib/UnitTestResultReportLibConOut.inf } UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf + UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmramSaveStateLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf =20 [Components.X64] diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmramSaveState= Lib.inf b/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmramSaveStateLib= .inf new file mode 100644 index 000000000000..c9d438027b03 --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmmSmramSaveStateLib.inf @@ -0,0 +1,28 @@ +## @file +# SMM Smram save state service lib. +# +# This is SMM Smram save state service lib that provide service to read an= d +# save savestate area registers. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D IntelSmmSmramSaveStateLib + FILE_GUID =3D 37E8137B-9F74-4250-8951-7A970A3C39C0 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SmmSmramSaveStateLib + +[Sources] + SmramSaveState.h + SmramSaveStateCommon.c + IntelSmramSaveState.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h b/Uef= iCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h index 6c424e3e36e9..55d9d9f127c0 100644 --- a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h @@ -90,7 +90,6 @@ SmramSaveStateGetRegisterIndex ( =20 **/ EFI_STATUS -EFIAPI SmramSaveStateReadRegisterByIndex ( IN UINTN CpuIndex, IN UINTN RegisterIndex, diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c b/= UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c index 8fc4466f473e..e0acd6182320 100644 --- a/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c @@ -11,21 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include =20 -#define EFER_ADDRESS 0XC0000080ul #define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 =20 // Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_ST= ATE_LOOKUP_ENTRY #define SMM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field) =20 -// Table used by SmramSaveStateGetRegisterIndex() to convert an EFI_SMM_SA= VE_STATE_REGISTER -// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY -CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmSmramCpuRegisterRanges[] =3D = { - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_ST= ATE_REGISTER_LDTINFO), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_ST= ATE_REGISTER_RIP), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_ST= ATE_REGISTER_CR4), - { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_S= TATE_REGISTER)0, 0} -}; - // Lookup table used to retrieve the widths and offsets associated with ea= ch // supported EFI_SMM_SAVE_STATE_REGISTER value CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[] =3D { @@ -294,25 +284,3 @@ SmramSaveStateWriteRegister ( =20 return EFI_SUCCESS; } - -/** - Returns LMA value of the Processor. - - @param[in] VOID - - @retval UINT8 returns LMA bit value. -**/ -UINT8 -SmramSaveStateGetRegisterLma ( - VOID - ) -{ - UINT32 LMAValue; - - LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; - if (LMAValue) { - return EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; - } - - return EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; -} diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmramSaveState.c = b/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmramSaveState.c new file mode 100644 index 000000000000..ac6c43772f14 --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/IntelSmramSaveState.c @@ -0,0 +1,359 @@ +/** @file +Provides services to access SMRAM Save State Map + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmramSaveState.h" +#include +#include +#include + +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 +#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 +#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 +#define INTEL_SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 + +/// +/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_LOOKUP_ENTRY +/// +#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) + +/// +/// Lookup table used to retrieve the widths and offsets associated with e= ach +/// supported EFI_SMM_SAVE_STATE_REGISTER value +/// +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[] =3D { + { 0, 0, 0, 0, = 0, FALSE }, // Reserved + + // + // Internally defined CPU Save State Registers. Not defined in PI SMM CP= U Protocol. + // + { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), = 0, FALSE }, // SMM_SAVE_STATE_REGIST= ER_SMMREVID_INDEX =3D 1 + { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), = 0, FALSE }, // SMM_SAVE_STATE_REGIST= ER_IOMISC_INDEX =3D 2 + { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), = SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGIST= ER_IOMEMADDR_INDEX =3D 3 + + // + // CPU Save State registers defined in PI SMM CPU Protocol. + // + { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GDTBASE =3D 4 + { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_IDTBASE =3D 5 + { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTBASE =3D 6 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GDTLIMIT =3D 7 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_IDTLIMIT =3D 8 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTLIMIT =3D 9 + { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTINFO =3D 10 + + { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_ES =3D 20 + { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CS =3D 21 + { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_SS =3D 22 + { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DS =3D 23 + { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_FS =3D 24 + { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GS =3D 25 + { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTR_SEL =3D 26 + { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_TR_SEL =3D 27 + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), = SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR7 =3D 28 + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), = SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR6 =3D 29 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), = SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R8 =3D 30 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), = SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R9 =3D 31 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), = SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R10 =3D 32 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), = SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R11 =3D 33 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), = SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R12 =3D 34 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), = SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R13 =3D 35 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), = SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R14 =3D 36 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), = SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R15 =3D 37 + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), = SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RAX =3D 38 + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), = SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBX =3D 39 + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), = SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RCX =3D 40 + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), = SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDX =3D 41 + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), = SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSP =3D 42 + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), = SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBP =3D 43 + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), = SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSI =3D 44 + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), = SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDI =3D 45 + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), = SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RIP =3D 46 + + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), = SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RFLAGS =3D 51 + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), = SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR0 =3D 52 + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), = SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR3 =3D 53 + { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR4 =3D 54 +}; + +/// +/// Structure used to build a lookup table for the IOMisc width informatio= n +/// +typedef struct { + UINT8 Width; + EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; +} CPU_SMM_SAVE_STATE_IO_WIDTH; + +/// +/// Lookup table for the IOMisc width information +/// +STATIC CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] =3D { + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 0 + { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE =3D 1 + { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD =3D 2 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 3 + { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD =3D 4 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 5 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 6 + { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined =3D 7 +}; + +/// +/// Lookup table for the IOMisc type information +/// +STATIC CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] =3D { + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX =3D = 0 + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX =3D = 1 + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS =3D = 2 + EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS =3D = 3 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 4 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 5 + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS =3D = 6 + EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS =3D = 7 + EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D = 8 + EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D = 9 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 10 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 11 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 12 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 13 + (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 14 + (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined =3D = 15 +}; + +/** + Read an SMM Save State register on the target processor. If this functi= on + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The + value must be between 0 and the NumberOfCpus field= in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save stat= e. + @param[out] Buffer Upon return, this holds the CPU register value rea= d + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateReadRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + UINT32 SmmRevId; + SMRAM_SAVE_STATE_IOMISC IoMisc; + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; + + // + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { + // + // Only byte access is supported for this register + // + if (Width !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + *(UINT8 *)Buffer =3D SmramSaveStateGetRegisterLma (); + + return EFI_SUCCESS; + } + + // + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { + // + // Get SMM Revision ID + // + SmramSaveStateReadRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_S= MMREVID_INDEX, sizeof (SmmRevId), &SmmRevId); + + // + // See if the CPU supports the IOMisc register in the save state + // + if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) { + return EFI_NOT_FOUND; + } + + // + // Get the IOMisc register value + // + SmramSaveStateReadRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_I= OMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32); + + // + // Check for the SMI_FLAG in IOMisc + // + if (IoMisc.Bits.SmiFlag =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS. + // + if ((mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_SMM_SAVE_STATE_IO_TYPE_I= NPUT) && + (mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_SMM_SAVE_STATE_IO_TYPE_O= UTPUT)) + { + return EFI_NOT_FOUND; + } + + // + // Compute index for the I/O Length and I/O Type lookup tables + // + if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width =3D=3D 0) || (mSmmCpuIoT= ype[IoMisc.Bits.Type] =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + // + // Make sure the incoming buffer is large enough to hold IoInfo before= accessing + // + if (Width < sizeof (EFI_SMM_SAVE_STATE_IO_INFO)) { + return EFI_INVALID_PARAMETER; + } + + // + // Zero the IoInfo structure that will be returned in Buffer + // + IoInfo =3D (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); + + // + // Use lookup tables to help fill in all the fields of the IoInfo stru= cture + // + IoInfo->IoPort =3D (UINT16)IoMisc.Bits.Port; + IoInfo->IoWidth =3D mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth; + IoInfo->IoType =3D mSmmCpuIoType[IoMisc.Bits.Type]; + SmramSaveStateReadRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX,= mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData); + return EFI_SUCCESS; + } + + // + // Convert Register to a register lookup table index + // + return SmramSaveStateReadRegisterByIndex (CpuIndex, SmramSaveStateGetReg= isterIndex (Register), Width, Buffer); +} + +/** + Writes an SMM Save State register on the target processor. If this func= tion + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateWriteRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + UINTN RegisterIndex; + SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { + return EFI_SUCCESS; + } + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported + // + if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index + // + RegisterIndex =3D SmramSaveStateGetRegisterIndex (Register); + if (RegisterIndex =3D=3D 0) { + return EFI_NOT_FOUND; + } + + CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; + + // + // Do not write non-writable SaveState, because it will cause exception. + // + if (!mSmmSmramCpuWidthOffset[RegisterIndex].Writeable) { + return EFI_UNSUPPORTED; + } + + // + // Check CPU mode + // + if (SmramSaveStateGetRegisterLma () =3D=3D EFI_SMM_SAVE_STATE_REGISTER_= LMA_32BIT) { + // + // If 32-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write SMM State register + // + ASSERT (CpuSaveState !=3D NULL); + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterIndex= ].Offset32, Buffer, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not b= e accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write at most 4 of the lower bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterIndex= ].Offset64Lo, Buffer, MIN (4, Width)); + if (Width > 4) { + // + // Write at most 4 of the upper bytes of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterInd= ex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); + } + } + + return EFI_SUCCESS; +} diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c= b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c index 98e89f9eec3f..53025e12cff9 100644 --- a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c @@ -9,9 +9,24 @@ **/ =20 #include "SmramSaveState.h" +#include +#include =20 -extern CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmSmramCpuRegisterRanges= []; -extern CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[]; +#define CPUID_VERSION_INFO 0x01 +#define CPUID_EXTENDED_FUNCTION 0x80000000 +#define CPUID_EXTENDED_CPU_SIG 0x80000001 +#define EFER_ADDRESS 0XC0000080ul + +// Table used by SmramSaveStateGetRegisterIndex() to convert an EFI_SMM_SA= VE_STATE_REGISTER +// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmSmramCpuRegisterRanges[] =3D = { + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_ST= ATE_REGISTER_LDTINFO), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_ST= ATE_REGISTER_RIP), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_ST= ATE_REGISTER_CR4), + { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_S= TATE_REGISTER)0, 0} +}; + +extern CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[]; =20 /** Read information from the CPU save state. @@ -61,7 +76,6 @@ SmramSaveStateGetRegisterIndex ( =20 **/ EFI_STATUS -EFIAPI SmramSaveStateReadRegisterByIndex ( IN UINTN CpuIndex, IN UINTN RegisterIndex, @@ -112,7 +126,7 @@ SmramSaveStateReadRegisterByIndex ( // Write lower 32-bits of return buffer // CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mSmmSmramCpu= WidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width)); - if (Width >=3D 4) { + if (Width > 4) { // // Write upper 32-bits of return buffer // @@ -122,3 +136,97 @@ SmramSaveStateReadRegisterByIndex ( =20 return EFI_SUCCESS; } + +/** + Returns LMA value of the Processor. + + @param[in] VOID + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +IntelSmramSaveStateGetRegisterLma ( + VOID + ) +{ + UINT32 RegEax; + UINT32 RegEdx; + UINTN FamilyId; + UINTN ModelId; + UINT8 SmmSaveStateRegisterLma; + + // + // Retrieve CPU Family + // + AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + FamilyId =3D (RegEax >> 8) & 0xf; + ModelId =3D (RegEax >> 4) & 0xf; + if ((FamilyId =3D=3D 0x06) || (FamilyId =3D=3D 0x0f)) { + ModelId =3D ModelId | ((RegEax >> 12) & 0xf0); + } + + RegEdx =3D 0; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); + } + + // + // Determine the mode of the CPU at the time an SMI occurs + // Intel(R) 64 and IA-32 Architectures Software Developer's Manual + // Volume 3C, Section 34.4.1.1 + // + SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if ((RegEdx & BIT29) !=3D 0) { + SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + if (FamilyId =3D=3D 0x06) { + if ((ModelId =3D=3D 0x17) || (ModelId =3D=3D 0x0f) || (ModelId =3D=3D = 0x1c)) { + SmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + } + + return SmmSaveStateRegisterLma; +} + +/** + Returns LMA value of the Processor. + + @param[in] VOID + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +AmdSmramSaveStateGetRegisterLma ( + VOID + ) +{ + UINT32 LMAValue; + + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + if (LMAValue) { + return EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + return EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; +} + +/** + Returns LMA value of the Processor. + + @param[in] VOID + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +SmramSaveStateGetRegisterLma ( + VOID + ) +{ + if (StandardSignatureIsAuthenticAMD ()) { + return AmdSmramSaveStateGetRegisterLma (); + } + + return IntelSmramSaveStateGetRegisterLma (); +} --=20 2.25.1