From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 137B6210E3DD5 for ; Thu, 9 Aug 2018 05:02:29 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id b90-v6so2484417plb.0 for ; Thu, 09 Aug 2018 05:02:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=2v2sSls4pAlP8D8xL44RSQCTKtTQwwIlYFO3+SGTVyI=; b=cSP6QQDtz44fe9qnXyibWd8K1CHKWGhixVrH0oWQyzxJPrSqblBnWvH+STn1peDE9w Duukp2g0KhR1DVuATGIhg3zKrGN6oyra2cO+6GQ1ey+oGSskBN1IAfSVsGw7kmYAoJb4 znDebmeah2DcwAk5WvqNV/oqCm68wFN2/FqeY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=2v2sSls4pAlP8D8xL44RSQCTKtTQwwIlYFO3+SGTVyI=; b=MwIjbGc+NJArYjZ98GIMk+B1jRd5gTvCRburbe4EouyMWp5vhLqlswjhvZHVEfU2wD 8qpMYUX5/BUHVpV8AvhT+xx3sqHY1yZ+06ExqK5YEf/M0MW3N9fbC03ztGx6vkSMGRj/ Qk/j5bhOrwoB4cn/d5LGmZDlvdVY5ERNHUVud6RKi5FERRSjunZ8hMqT2S6wvlfkZolR zd9bMlCS8/nwjB8bHd+w9ge6xR9nGCxKPyiJicxqPyXU+dxmrZgcqDB6O7U4EJGOPW+l zgt64nslOGQE6a6xa9G75nG07u6wXwcUR2Z4jUFNVV4jT7+pOaH5U5ua4vR/7wLX1HpU WTuA== X-Gm-Message-State: AOUpUlHwyo7vK/HyQwNk6XbtWbRK4c+mlc9EiWys1XXS5qQicsYOmR99 vIIsiMvlGSz6Vdj673c0DqE7Uw== X-Google-Smtp-Source: AA+uWPzdYT74Q5kiBfJhvjnmIUD4Huh6iVo+8A9ls8kYHNvhPhmfeCxITzVf3I6tzHB+uG+I4GDYyQ== X-Received: by 2002:a17:902:9a83:: with SMTP id w3-v6mr1822247plp.75.1533816149748; Thu, 09 Aug 2018 05:02:29 -0700 (PDT) Received: from [10.199.0.182] ([64.64.108.224]) by smtp.gmail.com with ESMTPSA id q78-v6sm11848060pfi.185.2018.08.09.05.02.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Aug 2018 05:02:29 -0700 (PDT) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Heyi Guo References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-32-ming.huang@linaro.org> <20180804145813.3bvqznfqtinajuvm@bivouac.eciton.net> From: Ming Message-ID: Date: Thu, 9 Aug 2018 20:02:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180804145813.3bvqznfqtinajuvm@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v1 31/38] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Aug 2018 12:02:30 -0000 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit ÔÚ 8/4/2018 10:58 PM, Leif Lindholm дµÀ: > On Tue, Jul 24, 2018 at 03:09:15PM +0800, Ming Huang wrote: >> Add soem Lpc macro to LpcLib.h for D06. > > soem -> some > > I have no issue with this patch, but can you explain when these macros > are intended to be used? And if in this set, move this patch > immediately before the patch than needs it? These macros are used by HwPkg. Thanks. > > / > Leif > >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> Signed-off-by: Heyi Guo >> --- >> Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- >> 1 file changed, 49 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h >> index 236a52ba45..5cf08ccde1 100755 >> --- a/Silicon/Hisilicon/Include/Library/LpcLib.h >> +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h >> @@ -1,7 +1,7 @@ >> /** @file >> * >> -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. >> -* Copyright (c) 2016, Linaro Limited. All rights reserved. >> +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. >> +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. >> * >> * This program and the accompanying materials >> * are licensed and made available under the terms and conditions of the BSD License >> @@ -18,6 +18,53 @@ >> >> #include >> >> +#define PCIE_SUBSYS_IOMUX 0x201100000 >> +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) >> +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) >> +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) >> +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) >> +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) >> +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) >> +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) >> +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) >> + >> +#define IO_MGMT_SUBCTRL_BASE 0x201070000 >> +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) >> +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) >> +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) >> + >> + >> +#define LPCD06_BASE 0x201190000 >> +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) >> +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) >> +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) >> +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) >> +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) >> +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) >> +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) >> +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) >> +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) >> +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) >> +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) >> +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) >> +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) >> +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) >> +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) >> + >> +#define LPCD06_START_REG (LPCD06_BASE + 0x00) >> +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) >> +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) >> +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) >> +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) >> +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) >> +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) >> +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) >> + >> +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) >> +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) >> +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) >> + >> + >> #define PCIE_SUBSYS_IO_MUX 0xA0170000 >> #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) >> #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) >> -- >> 2.17.0 >>