From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.7950.1639147338712600394 for ; Fri, 10 Dec 2021 06:42:19 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.com header.s=intel header.b=PTpOWG9p; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: sebastien.boeuf@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639147338; x=1670683338; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VRK0kxNdCJqOqnhAhtpM6foeF+/ZQxZ6oZQor4WgPkk=; b=PTpOWG9pLniU1EUnORNU4NUFHtGT2dmxlFAbrv2vCDMVjnQoiBraPEov 4hRxXLhPjtNxbicRq4lANwBGx8IN7XAEILeNEno+ySp5JxYs4hoytieJ4 XFuEa3ACCy1FX5H4vl72wUGL8y0ebLrYGZWbs11+B6MVD0jGGluJDNQr1 RWMKO3w+T6+8T76C5e5+cy58BzmGXikUKZRW8kI6bcispgly3p2BGOZrj 3E5j9yscVwNM0WOZsbp36h4GWr7p7GJIBCQ8Q4uiEDqC9kXIJCRhBQ3fJ /gaeYV4Gx0M30anxaKWGgwoCcwIbM5VPnPtgpaq6+IXCsHz0IKizkutAP g==; X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="219043823" X-IronPort-AV: E=Sophos;i="5.88,195,1635231600"; d="scan'208";a="219043823" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2021 06:42:18 -0800 X-IronPort-AV: E=Sophos;i="5.88,195,1635231600"; d="scan'208";a="503951504" Received: from gmarti2-mobl1.amr.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.20.4]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2021 06:42:16 -0800 From: "Boeuf, Sebastien" To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH v7 1/5] OvmfPkg: Handle Cloud Hypervisor host bridge Date: Fri, 10 Dec 2021 15:41:54 +0100 Message-Id: X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sebastien Boeuf Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Reviewed-by: Gerd Hoffmann Reviewed-by: Jiewen Yao Signed-off-by: Rob Bradford Signed-off-by: Sebastien Boeuf --- OvmfPkg/Include/IndustryStandard/CloudHv.h | 36 +++++++++++++++++++ OvmfPkg/Include/OvmfPlatforms.h | 1 + .../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 3 ++ .../AcpiTimerLib/BaseRomAcpiTimerLib.c | 4 +++ .../Library/AcpiTimerLib/DxeAcpiTimerLib.c | 3 ++ .../PlatformBootManagerLib/BdsPlatform.c | 1 + .../ResetSystemLib/BaseResetShutdown.c | 3 ++ .../Library/ResetSystemLib/DxeResetShutdown.c | 13 +++++-- OvmfPkg/PlatformPei/MemDetect.c | 9 ++++- OvmfPkg/PlatformPei/Platform.c | 8 +++++ 10 files changed, 78 insertions(+), 3 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/CloudHv.h diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/I= ndustryStandard/CloudHv.h new file mode 100644 index 0000000000..1155335690 --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h @@ -0,0 +1,36 @@ +/** @file + Various defines related to Cloud Hypervisor + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __CLOUDHV_H__ +#define __CLOUDHV_H__ + +// +// Host Bridge Device ID +// +#define CLOUDHV_DEVICE_ID 0x0d57 + +// +// ACPI timer address +// +#define CLOUDHV_ACPI_TIMER_IO_ADDRESS 0xb008 + +// +// ACPI shutdown device address +// +#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS 0x03c0 + +// +// 32-bit MMIO memory hole base address +// +#define CLOUDHV_MMIO_HOLE_ADDRESS 0xc0000000 + +// +// 32-bit MMIO memory hole size +// +#define CLOUDHV_MMIO_HOLE_SIZE 0x38000000 + +#endif // __CLOUDHV_H__ diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatform= s.h index de5d7663b4..f613dd7e2d 100644 --- a/OvmfPkg/Include/OvmfPlatforms.h +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -16,6 +16,7 @@ #include #include #include +#include = // // OVMF Host Bridge DID Address diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Libr= ary/AcpiTimerLib/BaseAcpiTimerLib.c index 1d33c86313..6d1e1cb05e 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -55,6 +55,9 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/L= ibrary/AcpiTimerLib/BaseRomAcpiTimerLib.c index 54a288d52f..c771997a2a 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -53,6 +53,8 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, @@ -111,6 +113,8 @@ InternalAcpiGetTimerTick ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS); default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Libra= ry/AcpiTimerLib/DxeAcpiTimerLib.c index 01f28b2916..1158461874 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -50,6 +50,9 @@ AcpiTimerLibConstructor ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg= /Library/PlatformBootManagerLib/BdsPlatform.c index f73c59dfff..5feadc51d7 100644 --- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c @@ -1390,6 +1390,7 @@ PciAcpiInitialization ( PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H break; case MICROVM_PSEUDO_DEVICE_ID: + case CLOUDHV_DEVICE_ID: return; default: if (XenDetected ()) { diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/L= ibrary/ResetSystemLib/BaseResetShutdown.c index 29abd57fa7..c21d3c89cf 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c @@ -40,6 +40,9 @@ ResetShutdown ( case INTEL_Q35_MCH_DEVICE_ID: AcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5); + CpuDeadLoop (); default: ASSERT (FALSE); CpuDeadLoop (); diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Li= brary/ResetSystemLib/DxeResetShutdown.c index a0db8b50bf..31f01b82e4 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c @@ -16,6 +16,7 @@ #include // PIIX4_PMBA_VALUE = STATIC UINT16 mAcpiPmBaseAddress; +STATIC UINT16 mAcpiHwReducedSleepCtl; = EFI_STATUS EFIAPI @@ -34,6 +35,9 @@ DxeResetInit ( case INTEL_Q35_MCH_DEVICE_ID: mAcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + mAcpiHwReducedSleepCtl =3D CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS; + break; default: ASSERT (FALSE); CpuDeadLoop (); @@ -56,7 +60,12 @@ ResetShutdown ( VOID ) { - IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); - IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + if (mAcpiHwReducedSleepCtl) { + IoWrite8 (mAcpiHwReducedSleepCtl, 5 << 2 | 1 << 5); + } else { + IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); + IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + } + CpuDeadLoop (); } diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 738ed0c208..934d5c1965 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -16,6 +16,7 @@ Module Name: #include #include #include +#include #include #include = @@ -159,6 +160,12 @@ QemuUc32BaseInitialization ( return; } = + if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return; + } + ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); // // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one @@ -819,7 +826,7 @@ QemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs = to // cover it exactly. // - if (IsMtrrSupported ()) { + if (IsMtrrSupported () && (mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID)) { MtrrGetAllMtrrs (&MtrrSettings); = // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3000176efd..906f64615d 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -374,6 +374,14 @@ MiscInitialization ( ); ASSERT_RETURN_ERROR (PcdStatus); return; + case CLOUDHV_DEVICE_ID: + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); + PcdStatus =3D PcdSet16S ( + PcdOvmfHostBridgePciDevId, + CLOUDHV_DEVICE_ID + ); + ASSERT_RETURN_ERROR (PcdStatus); + return; default: DEBUG (( DEBUG_ERROR, -- = 2.30.2 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, = 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. 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