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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4027.namprd12.prod.outlook.com (2603:10b6:5:148::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.20; Tue, 24 Mar 2020 17:41:33 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2835.023; Tue, 24 Mar 2020 17:41:33 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v6 24/42] UefiCpuPkg/CpuExceptionHandler: Add support for DR7 Read/Write NAE events Date: Tue, 24 Mar 2020 12:40:38 -0500 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR06CA0025.namprd06.prod.outlook.com (2603:10b6:3:5d::11) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR06CA0025.namprd06.prod.outlook.com (2603:10b6:3:5d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.19 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: ddRsfb4jwMgogdgJJ0OJu7c4q66KtrXhmmOVoDBl4Oi8yiAO5uq5RbMPTvwVx1Sgb6dpsi7UOOs99IxNcu4WbC4Wz0yy1JOLpqt7ZU9YXGwCQ60E4H/lKeIwpaDnjxM7RH0S+Nio3D1ebZWZxBnRbVufa63Bl1UYA0w7/oDnKf16zIXCfAyGGvUj+nMM/B2LdHj7G2fjD/CCiV3q8J3XnuQBGxFvyLvwZBKOZhXid2ROlrjBX2DqOsIlfV5jLnNasK+/AMkXBwwkbOdbIdXboL5TGBg4mIwkJ7isMqyb6qMj5JQoxuYHGbFjeFxTmyoAtkrXSpmjDXbvXxeVs9KjdgbW0N+e5FeVUKjr4uSLqQTBdV8kjaMhlnoJBhgc5Zg4GBdBYX6FI9xAwS4QC2uT5g8i4Wqxg5ZTvgX97AD2mRnb1H5GMo7xcPSOHsy70bx7Ppn4J3cxL4r/hwSRLgY5HXoG6hN8OZsea913siWa0WcE5g0G4zQ/rT2DDkSs+Yup7cUoxNlcWfGQsmbYB000YP/rh4DUnLwWeubfvkxOD5X9qe/XIXopeReGdah8IAK2wxuwkhlVhEIEtknX1yoHzg== X-MS-Exchange-AntiSpam-MessageData: lPaUk+e5GUzY6ADSSISbJYOBVCaASibjXrSWpn3AKmfJVD/+6GA4Q9U6d2F0F3LaS88DTvP8Nlex1mgFt0cahy1lWCAvQRNQ2G80bl8IpzKla4jGL+jMnP1lIypXWCRyhbSR9iPy8PDwJ8KKjT3Zzg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 253c974c-da78-4718-ee73-08d7d01a979d X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2020 17:41:33.1859 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vQErKV3Z4SUetLC5MDfP3w5wGk5JS6CMke/rq2Agm/yxn6CnDZEqPKZReTPMc8T5WLTFrRq6mkQ7hAFeVCr3+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4027 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a DR7 read or write intercept generates a #VC exception. The #VC handler must provide special support to the guest for this. On a DR7 write, the #VC handler must cache the value and issue a VMGEXIT to notify the hypervisor of the write. However, the #VC handler must not actually set the value of the DR7 register. On a DR7 read, the #VC handler must return the cached value of the DR7 register to the guest. VMGEXIT is not invoked for a DR7 register read. To avoid exception recursion, a #VC exception will not try to read and push the actual debug registers into the EFI_SYSTEM_CONTEXT_X64 struct and instead push zeroes. The #VC exception handler does not make use of the debug registers from saved context. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 68 +++++++++++++++++++ .../X64/ExceptionHandlerAsm.nasm | 17 +++++ 2 files changed, 85 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 1fdbb122c35d..cca9481e8900 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -13,6 +13,12 @@ #define CR4_OSXSAVE (1 << 18) +#define DR7_RESET_VALUE 0x400 +typedef struct { + BOOLEAN Dr7Cached; + UINT64 Dr7; +} SEV_ES_PER_CPU_DATA; + typedef enum { LongMode64Bit = 0, LongModeCompat32Bit, @@ -1076,6 +1082,60 @@ RdtscExit ( return 0; } +STATIC +UINT64 +Dr7WriteExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext = &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + INTN *Register; + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + + /* Using a value of 0 for ExitInfo1 means RAX holds the value */ + Ghcb->SaveArea.Rax = *Register; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status = VmgExit (Ghcb, SvmExitDr7Write, 0, 0); + if (Status) { + return Status; + } + + SevEsData->Dr7 = *Register; + SevEsData->Dr7Cached = TRUE; + + return 0; +} + +STATIC +UINT64 +Dr7ReadExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext = &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + INTN *Register; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + *Register = (SevEsData->Dr7Cached) ? SevEsData->Dr7 : DR7_RESET_VALUE; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -1092,6 +1152,14 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitDr7Read: + NaeExit = Dr7ReadExit; + break; + + case SvmExitDr7Write: + NaeExit = Dr7WriteExit; + break; + case SvmExitRdtsc: NaeExit = RdtscExit; break; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 19198f273137..26cae56cc5cf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -225,6 +227,9 @@ HasErrorCode: push rax ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -237,7 +242,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp -- 2.17.1