From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 1E2F9740034 for ; Fri, 22 Mar 2024 05:02:15 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Kac8EAXo14nc/Rm9g0LMG2ANEK3BuOSpquHVi1BHgd0=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20240206; t=1711083734; v=1; b=eEbYoTD6JdLknwN36PeyLg5NMX6brZyL3mZp8jOBw4XwFTzmVaReQzcHD2RCA8YQ35pooTjF 1f5ZdDMzZuFzgX6k7Qd8lp4ilG4Vt9iavyuLtInTyZw8TQKGheb0igtqp4IM7/rNb4JrF/FMKvG AlHVmOh6ksEGJdJGolkU/X2z0ugK2PpDNrAXJI0KLH7aXZiF2x5zBtYXuU8jx2FL9Oy5h0sbp6M rm6esSffDKu1WzfYLhddepf1oLwa2F1aY1R67wQ32s9Ed6KWxoOE1YiO3U2xHVAGDnCTbHv82aZ Yb0/Ow8ij9Wc1TDY3rpMWud6hToQ2I/lTdfqUByBQX3mQ== X-Received: by 127.0.0.2 with SMTP id httYYY7687511xagZ6qqZzJK; Thu, 21 Mar 2024 22:02:14 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.5796.1711083733872517301 for ; Thu, 21 Mar 2024 22:02:13 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="23567503" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="23567503" X-Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2024 22:02:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="19231766" X-Received: from cbduggap-mobl.gar.corp.intel.com ([10.247.49.231]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2024 22:02:10 -0700 From: "cbduggap" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Chiu Chasel , Duggapu Chinni B Subject: [edk2-devel] [PATCH v5] IntelFsp2Pkg: Fsp T new ARCH UPD Support Date: Fri, 22 Mar 2024 10:31:46 +0530 Message-Id: In-Reply-To: <602812ed6f70bd983c30924dc6a3619e7a3bb1b5.1709108958.git.chinni.b.duggapu@intel.com> References: <602812ed6f70bd983c30924dc6a3619e7a3bb1b5.1709108958.git.chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 21 Mar 2024 22:02:14 -0700 Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: msrh5GHGEza8ysYd1QJz1i5Wx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=eEbYoTD6; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty Cc: Nate DeSimone Cc: Chiu Chasel Cc: Duggapu Chinni B Signed-off-by: Duggapu Chinni B --- IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 1 + IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 + .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryT.nasm | 62 ++++++++++++++--- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 +++ IntelFsp2Pkg/FspSecCore/SecFsp.c | 9 +++ IntelFsp2Pkg/FspSecCore/SecFsp.h | 1 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 69 +++++++++++++++---- IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +- IntelFsp2Pkg/Include/Library/FspPlatformLib.h | 13 ++++ .../Include/SaveRestoreSseAvxNasm.inc | 21 ++++++ .../BaseFspPlatformLib/FspPlatformMemory.c | 38 ++++++++++ .../SecRamInitData.c | 3 +- 14 files changed, 209 insertions(+), 27 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreM.inf index cb011f99f9..8cb0e6411f 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf @@ -60,6 +60,7 @@ FspSecPlatformLib=0D CpuLib=0D FspMultiPhaseLib=0D + FspPlatformLib=0D =0D [Pcd]=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreM.inf index 8029832235..ef19c6ae78 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -59,6 +59,7 @@ FspCommonLib=0D FspSecPlatformLib=0D CpuLib=0D + FspPlatformLib=0D =0D [Pcd]=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 15f8ecea83..5fa5c03569 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryM.nasm index 61ab4612a3..861cce4d01 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 900126b93b..f72da0d5a9 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison i= s >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -267,7 +268,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jae Fsp24UpdHeader=0D jmp Fsp22UpdHeader=0D =0D Fsp20UpdHeader:=0D @@ -405,7 +406,7 @@ CheckAddress: cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader1=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader1;=0D + jae Fsp24UpdHeader1;=0D jmp Fsp22UpdHeader1=0D =0D Fsp20UpdHeader1:=0D @@ -497,7 +498,8 @@ ASM_PFX(EstablishStackFsp): ; Enable FSP STACK=0D ;=0D mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + LOAD_TEMPORARY_RAM_SIZE ecx=0D + add esp, ecx=0D =0D push DATA_LEN_OF_MCUD ; Size of the data region=0D push 4455434Dh ; Signature of the data region 'MCUD'=0D @@ -506,7 +508,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2= =0D jb Fsp20UpdHeader2=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader2=0D + jae Fsp24UpdHeader2=0D jmp Fsp22UpdHeader2=0D =0D Fsp20UpdHeader2:=0D @@ -554,12 +556,13 @@ ContinueAfterUpdPush: ;=0D ; Set ECX/EDX to the BootLoader temporary memory range=0D ;=0D - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - mov edx, ecx=0D - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D + LOAD_TEMPORARY_RAM_SIZE ecx=0D + add edx, ecx=0D sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]=0D + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D =0D - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTemporary= RamSize, then error.=0D + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryRam= Size, then error.=0D jb EstablishStackFspSuccess=0D mov eax, 80000003h ;EFI_UNSUPPORTED=0D jmp EstablishStackFspExit=0D @@ -599,6 +602,47 @@ ASM_PFX(TempRamInitApi): CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D SAVE_ECX ; save UPD param to slot 3 in xmm= 6=0D =0D + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [edx]=0D + ;=0D + ; Read ARCH2 UPD input value.=0D + ;=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D +=0D + xor eax, eax=0D + mov ax, WORD [esi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov eax, 080000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + ;=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE ebx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE edx=0D +GotTemporaryRamSize:=0D + LOAD_ECX=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 016f943b43..4d6ec1e984 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -128,6 +128,17 @@ SXMMN xmm5, 1, eax=0D %endmacro=0D =0D +;=0D +; XMM5 slot 2 for TemporaryRamSize=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LXMMN xmm5, %1, 2=0D + %endmacro=0D +=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + SXMMN xmm5, 2, %1=0D + %endmacro=0D +=0D %macro ENABLE_SSE 0=0D ;=0D ; Initialize floating point units=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 11be1f97ca..281d39a24b 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -54,6 +54,7 @@ SecGetPlatformData ( UINT32 TopOfCar;=0D UINT32 *StackPtr;=0D UINT32 DwordSize;=0D + UINT32 TemporaryRamSize;=0D =0D FspPlatformData =3D &FspData->PlatformData;=0D =0D @@ -67,12 +68,20 @@ SecGetPlatformData ( FspPlatformData->MicrocodeRegionSize =3D 0;=0D FspPlatformData->CodeRegionBase =3D 0;=0D FspPlatformData->CodeRegionSize =3D 0;=0D + TemporaryRamSize =3D 0;=0D =0D //=0D // Pointer to the size field=0D //=0D TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamS= ize);=0D StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32));=0D + if ((*(StackPtr - 1) !=3D FSP_MCUD_SIGNATURE) && (FspData->FspInfoHeader= ->ImageAttribute & BIT4)) {=0D + ReadTemporaryRamSize (PcdGet32 (PcdTemporaryRamBase), &TemporaryRamSiz= e);=0D + if (TemporaryRamSize) {=0D + TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize;=0D + StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32));=0D + }=0D + }=0D =0D if (*(StackPtr - 1) =3D=3D FSP_MCUD_SIGNATURE) {=0D while (*StackPtr !=3D 0) {=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.h index 693af29f20..c05b46c750 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h @@ -17,6 +17,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D #define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D')=0D #define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0')=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 698bb063a7..8cd157f2c3 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -16,6 +16,7 @@ extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))=0D =0D ;=0D ; Following functions will be provided in PlatformSecLib=0D @@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is= >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D @@ -273,7 +275,7 @@ CheckAddress: cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D ; Is automatic size detection ?=0D @@ -337,8 +339,8 @@ ASM_PFX(EstablishStackFsp): ;=0D mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov esp, DWORD[rax]=0D - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add esp, DWORD[rax]=0D + LOAD_TEMPORARY_RAM_SIZE rax=0D + add esp, eax=0D =0D sub esp, 4=0D mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region=0D @@ -349,7 +351,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2= =0D jb ParamError1=0D cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jnb Fsp24UpdHeader=0D =0D ParamError1:=0D mov rax, 08000000000000002h=0D @@ -397,8 +399,8 @@ ContinueAfterUpdPush: ;=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov edx, [ecx]=0D - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add edx, [ecx]=0D + LOAD_TEMPORARY_RAM_SIZE rcx=0D + add edx, ecx=0D mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D sub edx, [ecx]=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D @@ -439,6 +441,14 @@ ASM_PFX(TempRamInitApi): ;=0D SAVE_BFV rbp=0D =0D + ;=0D + ; Save timestamp into YMM6=0D + ;=0D + rdtsc=0D + shl rdx, 32=0D + or rax, rdx=0D + SAVE_TS rax=0D +=0D ;=0D ; Save Input Parameter in YMM10=0D ;=0D @@ -455,14 +465,47 @@ ASM_PFX(TempRamInitApi): ParamValid:=0D SAVE_RCX=0D =0D + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [rdx]=0D ;=0D - ; Save timestamp into YMM6=0D + ; Read ARCH2 UPD input value.=0D ;=0D - rdtsc=0D - shl rdx, 32=0D - or rax, rdx=0D - SAVE_TS rax=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D +=0D + xor rax, rax=0D + mov ax, WORD [rsi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ; Only low-32 bits of rbx/rdx holds the temporary ram size.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE rbx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE rdx=0D =0D +GotTemporaryRamSize:=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 40e063e944..27d5ec3a3c 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -139,7 +139,7 @@ typedef struct { ///=0D typedef struct {=0D ///=0D - /// Revision of the structure is 2 for this version of the specification= .=0D + /// Revision of the structure is 3 for this version of the specification= .=0D ///=0D UINT8 Revision;=0D UINT8 Reserved[3];=0D @@ -152,7 +152,8 @@ typedef struct { /// occurring during FSP execution.=0D ///=0D EFI_PHYSICAL_ADDRESS FspDebugHandler;=0D - UINT8 Reserved1[16];=0D + UINT32 FspTemporaryRamSize;=0D + UINT8 Reserved1[12];=0D } FSPT_ARCH2_UPD;=0D =0D ///=0D diff --git a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/IntelFsp2Pkg/I= nclude/Library/FspPlatformLib.h index 081add6529..03eca5e1fc 100644 --- a/IntelFsp2Pkg/Include/Library/FspPlatformLib.h +++ b/IntelFsp2Pkg/Include/Library/FspPlatformLib.h @@ -121,4 +121,17 @@ FspTempRamExitDone2 ( IN EFI_STATUS Status=0D );=0D =0D +/**=0D + Calculate TemporaryRam Size using Base address=0D +=0D + @param[in] TemporaryRamBase the address of target memory=0D + @param[out] TemporaryRamSize the size of target memory=0D +**/=0D +VOID=0D +EFIAPI=0D +ReadTemporaryRamSize (=0D + IN UINT32 TemporaryRamBase,=0D + OUT UINT32 *TemporaryRamSize=0D + );=0D +=0D #endif=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 002a5a1412..2168564e6d 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -201,6 +201,27 @@ movq rcx, xmm5=0D %endmacro=0D =0D +;=0D +; Save TemporaryRamSize to YMM10[192:255]=0D +; arg 1:general purpose register which holds TemporaryRamSize=0D +; Modified: XMM5 and YMM10[192:255]=0D +;=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 1, %1=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore TemporaryRamSize from YMM10[192:255]=0D +; arg 1:general purpose register where to save TemporaryRamSize=0D +; Modified: XMM5 and %1=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + LXMMN xmm5, %1, 1=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c b/= IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c index 2573e4e421..4c5c1f824e 100644 --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c @@ -6,6 +6,7 @@ **/=0D =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -119,3 +120,40 @@ FspGetSystemMemorySize ( Hob.Raw =3D GET_NEXT_HOB (Hob);=0D }=0D }=0D +=0D +/**=0D + Calculate TemporaryRam Size using Base address=0D +=0D + @param[in] TemporaryRamBase the address of target memory=0D + @param[out] TemporaryRamSize the size of target memory=0D +**/=0D +VOID=0D +EFIAPI=0D +ReadTemporaryRamSize (=0D + IN UINT32 TemporaryRamBase,=0D + OUT UINT32 *TemporaryRamSize=0D + )=0D +{=0D + MSR_IA32_MTRRCAP_REGISTER Msr;=0D + UINT32 MsrNum;=0D + UINT32 MsrNumEnd;=0D +=0D + if (TemporaryRamBase =3D=3D 0) {=0D + return ;=0D + }=0D +=0D + *TemporaryRamSize =3D 0;=0D + Msr.Uint64 =3D AsmReadMsr64(MSR_IA32_MTRRCAP);=0D + MsrNumEnd =3D MSR_IA32_MTRR_PHYSBASE0 + (2 * (Msr.Bits.VCNT));=0D +=0D + for (MsrNum =3D MSR_IA32_MTRR_PHYSBASE0; MsrNum < MsrNumEnd; MsrNum +=3D= 2) {=0D + if ((AsmReadMsr64 (MsrNum+1) & BIT11) !=3D 0 ) {=0D + if (TemporaryRamBase =3D=3D (AsmReadMsr64 (MsrNum) & 0xFFFFF000)) {= =0D + *TemporaryRamSize =3D (~(AsmReadMsr64 (MsrNum+1) & 0xFFFFF000) + 1= );=0D + break;=0D + }=0D + }=0D + }=0D + return;=0D +}=0D +=0D diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index fb0d9a8683..316c2fa86a 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA F= sptUpdDataPtr =3D { },=0D 0x00000020,=0D 0x00000000,=0D + 0x00000000,=0D {=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D }=0D },=0D --=20 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117027): https://edk2.groups.io/g/devel/message/117027 Mute This Topic: https://groups.io/mt/105079990/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-