From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (NAM10-BN7-obe.outbound.protection.outlook.com [40.107.92.68]) by mx.groups.io with SMTP id smtpd.web11.2569.1686031688563237274 for ; Mon, 05 Jun 2023 23:08:08 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amd.com header.s=selector1 header.b=MygIspbe; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.92.68, mailfrom: abdullateef.attar@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mJuk3dkr67zJGN74SK24WTWKsSf75tLcZAG6RwN6bP/R0/+4UByZKo1PLjapPAoh3CFx718uLysS6esFhrBNSgDWPzvm0TFQRL0sI7/wdbJOiZfQTPtEMAb48WHOY0QrQi0RpWL5WzpoEmlSMA+wQQFfkzEtKc0P6mnGV8zWwoaSTBTjGWvDQm17Krd2aqTlmftM3mhhPRdA7MKSJm6VmPQ+uIMxcdZ95NOpLwJsIBnCQzlAwQeHIvnYlNVg6sf9XNaXjKtPhQ4Aq3VbBjj5kuY52hyRX6Y6bAPyU6xX9imKMgaACeNorK6EVKo22dItBPIgvQsJG2Wf3WDrpcVoTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0elUXQJX2AiUWnIxbtGgurgEcBYpsaeR4BzyXKzPTAc=; b=LjGZXfBMepG/gwAv6SubPABdjDHJ5wSLqzpDCZQWFDkNrjithfpx/PAL6nGis25ATXxSzRb62PLvKMFrdWQkRPK0dJiX/q49UKJD1YCK1gCumdkzcyAsRJEwGjUGAbeHjNFxtxBVmsZYq8ZK3qk8TBSF9HXk3VOL25K4ptUAKAX6/n9owMfZwMfFApUJswRhtA2IV4hKiEub3pf9Rs9q5TLR4sYs7bdjxc1jP5B95eOEHvrpDobxu6uW274LywJ+nxYkEVTuyouxVFaSpjOQvSnMf8sALBokfdHAWEr93AL6sDH3v9hmzJI/Hg1CxqD4kjeBMxDoctZ90M/13aZKiQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0elUXQJX2AiUWnIxbtGgurgEcBYpsaeR4BzyXKzPTAc=; b=MygIspbeoHs7QzhtrKYPnP5cASjGQnrg1eH0yoL+jMuHGUtpayPbjEuEM4anQirFvhGeEPHcHt69RnZuXyO789U8zoFagjCwaIPPPBJA6MlOvnq0kCLIHvkBVa1QKdXFAON8ObkA3fJQtL2MY89vgMl5j70L5VTYD8bTIZLkBso= Received: from BN9PR03CA0673.namprd03.prod.outlook.com (2603:10b6:408:10e::18) by DM4PR12MB7743.namprd12.prod.outlook.com (2603:10b6:8:101::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.33; Tue, 6 Jun 2023 06:08:05 +0000 Received: from BN8NAM11FT050.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10e:cafe::dd) by BN9PR03CA0673.outlook.office365.com (2603:10b6:408:10e::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.33 via Frontend Transport; Tue, 6 Jun 2023 06:08:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT050.mail.protection.outlook.com (10.13.177.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6455.33 via Frontend Transport; Tue, 6 Jun 2023 06:08:05 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Jun 2023 01:08:05 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Jun 2023 01:08:05 -0500 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 6 Jun 2023 01:08:03 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Abner Chang , Paul Grimes , Eric Dong , Ray Ni , Rahul Kumar Subject: [PATCH v14 4/8] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Date: Tue, 6 Jun 2023 11:37:24 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|DM4PR12MB7743:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a983a3f-b629-45b5-886a-08db665464d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: c5tkG9hOJpt1iunGdaUNIqG/phRvVsfbyyiIjSpOTnSVdJAMyQjRpMGLXSlUv+fNFY9mZ+ASmQVteACN0Ie7wN9CKPhSaLRCVzkoR1SsAVgHcxLS2F8WnRx65AGeBccTu5diZKyi4cQvc7AUY9FHsCVyURoCmwXn+CcGSPz1rsJ3Ouz9zoGicg9WUGXWU7f5/5IRmo+3ONy8xkFPZlM5G558PoejEE6Wa6NASv2+2V7hkQ/w95jvYEkP+OAz60iDnvV7FKL9kzkE40nfdnVhpBXoe5ax+2yhJTFuKr7Gx0I+xoLQJq0Tg+0mv4/8J0xjvGczgQqGxlDTeRjCRB/7AgBIpCTczOflw9qA9wd0cIXQvPADRwmoWZD2qCXCY0dZN4cOv07S19F+OAd4vruVdNv7RveQeYoCQBprIbKRYRodm+R5H64yXu49FSTN6PDF3V/1+2/m2b5WifJ2GZiaG0LuAccZsSK0yOsC1UClaqjvenwsOfv0KZi/kUsLxV8DypJTfXhh1W2ZRF6XX8awAG6TBcVIrPnIq0q73ysso5doHvZ02wV/d4gHtbrwo7HTYE9FjSmc3RTdja+DIqaGC/NqjkS8+/X43wHKUH1/DQPHAlD2oV7w8hesni0S3OQCWjT3Vmqxzt67azHu60uRBONUnM4OtVxnMkHzCEH6efAuhOAZCq+Bwm/Rkgu97cionFHqEcSTQxfijoQPPJAC8qaNyAqSYlCzpCsjvSUrSw/2BgsqRauKf6fALE/nwFLT X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(40470700004)(36840700001)(46966006)(478600001)(2906002)(30864003)(40460700003)(966005)(7696005)(36756003)(336012)(82310400005)(6666004)(2616005)(36860700001)(83380400001)(47076005)(426003)(26005)(186003)(82740400003)(356005)(81166007)(40480700001)(5660300002)(316002)(8676002)(8936002)(70586007)(70206006)(4326008)(6916009)(19627235002)(54906003)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2023 06:08:05.7328 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a983a3f-b629-45b5-886a-08db665464d1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7743 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 moves Intel-specific code to the arch-dependent file. Other processor families might have different implementation of these functions. Hence, moving out of the common file. Cc: Abner Chang Cc: Paul Grimes Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang Reviewed-by: Ray Ni --- .../IntelSmmCpuFeaturesLib.c | 128 ++++++++++++++++++ .../SmmCpuFeaturesLibCommon.c | 128 ------------------ 2 files changed, 128 insertions(+), 128 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index 1a2c706fa1f1..8f382b60266c 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -417,3 +417,131 @@ SmmCpuFeaturesSetSmmRegister ( AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); } } + +/** + This function updates the SMRAM save state on the currently executing CP= U + to resume execution at a specific address after an RSM instruction. Thi= s + function must evaluate the SMRAM save state to determine the execution m= ode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start + flag in the SMRAM save state must always be cleared. This function retu= rns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de + to signal that the SMBASE of each CPU has been updated before the defaul= t + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The index of the CPU to hook. The v= alue + must be between 0 and the NumberOfCp= us + field in the System Management Syste= m Table + (SMST). + @param[in] CpuState Pointer to SMRAM Save State Map for = the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to + 32-bit execution mode from 64-bit SM= M. + @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to + same execution mode as SMM. + + @retval 0 This function did modify the SMRAM save state. + @retval > 0 The original instruction pointer value from the SMRAM save = state + before it was replaced. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesHookReturnFromSmm ( + IN UINTN CpuIndex, + IN SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + return 0; +} + +/** + Read an SMM Save State register on the target processor. If this functi= on + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The + value must be between 0 and the NumberOfCpus field= in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save stat= e. + @param[out] Buffer Upon return, this holds the CPU register value rea= d + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. + +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesReadSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Writes an SMM Save State register on the target processor. If this func= tion + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesWriteSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Check to see if an SMM register is supported by a specified CPU. + + @param[in] CpuIndex The index of the CPU to check for SMM register supp= ort. + The value must be between 0 and the NumberOfCpus fi= eld + in the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to check for support. + + @retval TRUE The SMM register specified by RegName is supported by the= CPU + specified by CpuIndex. + @retval FALSE The SMM register specified by RegName is not supported by= the + CPU specified by CpuIndex. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesIsSmmRegisterSupported ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName =3D=3D SmmReg= FeatureControl)) { + return TRUE; + } + + return FALSE; +} diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c= b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index 5498fda38da4..cbf4b495185b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -17,49 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include "CpuFeaturesLib.h" =20 -/** - This function updates the SMRAM save state on the currently executing CP= U - to resume execution at a specific address after an RSM instruction. Thi= s - function must evaluate the SMRAM save state to determine the execution m= ode - the RSM instruction resumes and update the resume execution address with - either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start - flag in the SMRAM save state must always be cleared. This function retu= rns - the value of the instruction pointer from the SMRAM save state that was - replaced. If this function returns 0, then the SMRAM save state was not - modified. - - This function is called during the very first SMI on each CPU after - SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de - to signal that the SMBASE of each CPU has been updated before the defaul= t - SMBASE address is used for the first SMI to the next CPU. - - @param[in] CpuIndex The index of the CPU to hook. The v= alue - must be between 0 and the NumberOfCp= us - field in the System Management Syste= m Table - (SMST). - @param[in] CpuState Pointer to SMRAM Save State Map for = the - currently executing CPU. - @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to - 32-bit execution mode from 64-bit SM= M. - @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to - same execution mode as SMM. - - @retval 0 This function did modify the SMRAM save state. - @retval > 0 The original instruction pointer value from the SMRAM save = state - before it was replaced. -**/ -UINT64 -EFIAPI -SmmCpuFeaturesHookReturnFromSmm ( - IN UINTN CpuIndex, - IN SMRAM_SAVE_STATE_MAP *CpuState, - IN UINT64 NewInstructionPointer32, - IN UINT64 NewInstructionPointer - ) -{ - return 0; -} - /** Hook point in normal execution mode that allows the one CPU that was ele= cted as monarch during System Management Mode initialization to perform addit= ional @@ -90,91 +47,6 @@ SmmCpuFeaturesRendezvousExit ( { } =20 -/** - Check to see if an SMM register is supported by a specified CPU. - - @param[in] CpuIndex The index of the CPU to check for SMM register supp= ort. - The value must be between 0 and the NumberOfCpus fi= eld - in the System Management System Table (SMST). - @param[in] RegName Identifies the SMM register to check for support. - - @retval TRUE The SMM register specified by RegName is supported by the= CPU - specified by CpuIndex. - @retval FALSE The SMM register specified by RegName is not supported by= the - CPU specified by CpuIndex. -**/ -BOOLEAN -EFIAPI -SmmCpuFeaturesIsSmmRegisterSupported ( - IN UINTN CpuIndex, - IN SMM_REG_NAME RegName - ) -{ - if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName =3D=3D SmmReg= FeatureControl)) { - return TRUE; - } - - return FALSE; -} - -/** - Read an SMM Save State register on the target processor. If this functi= on - returns EFI_UNSUPPORTED, then the caller is responsible for reading the - SMM Save Sate register. - - @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The - value must be between 0 and the NumberOfCpus field= in - the System Management System Table (SMST). - @param[in] Register The SMM Save State register to read. - @param[in] Width The number of bytes to read from the CPU save stat= e. - @param[out] Buffer Upon return, this holds the CPU register value rea= d - from the save state. - - @retval EFI_SUCCESS The register was read from Save State. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. - -**/ -EFI_STATUS -EFIAPI -SmmCpuFeaturesReadSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - OUT VOID *Buffer - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Writes an SMM Save State register on the target processor. If this func= tion - returns EFI_UNSUPPORTED, then the caller is responsible for writing the - SMM Save Sate register. - - @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The - value must be between 0 and the NumberOfCpus field = in - the System Management System Table (SMST). - @param[in] Register The SMM Save State register to write. - @param[in] Width The number of bytes to write to the CPU save state. - @param[in] Buffer Upon entry, this holds the new CPU register value. - - @retval EFI_SUCCESS The register was written to Save State. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. -**/ -EFI_STATUS -EFIAPI -SmmCpuFeaturesWriteSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - IN CONST VOID *Buffer - ) -{ - return EFI_UNSUPPORTED; -} - /** This function is hook point called after the gEfiSmmReadyToLockProtocolG= uid notification is completely processed. --=20 2.25.1