From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2A71B1A1E56 for ; Tue, 13 Sep 2016 18:49:35 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP; 13 Sep 2016 18:49:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,331,1470726000"; d="scan'208";a="8103326" Received: from shwdeftian.ccr.corp.intel.com ([10.239.158.36]) by fmsmga006.fm.intel.com with ESMTP; 13 Sep 2016 18:49:33 -0700 From: Feng Tian To: star.zeng@intel.com Cc: edk2-devel@lists.01.org Date: Wed, 14 Sep 2016 09:49:19 +0800 Message-Id: X-Mailer: git-send-email 2.7.1.windows.2 Subject: [patch] MdeModulePkg/XhciPei: 1ms delay before accessing MMIO reg in reset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Sep 2016 01:49:35 -0000 Some XHCI HCs require to have 1ms delay before accessing any MMIO register in reset. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian --- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 1 + 1 file changed, 1 insertion(+) diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c index a58739f..cd5c5cd 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -407,6 +407,7 @@ XhcPeiResetHC ( } XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET); + MicroSecondDelay (1000); Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout); ON_EXIT: DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status)); -- 2.7.1.windows.2