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From: Jeremy Linton <jeremy.linton@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	edk2-devel@lists.01.org, liming.gao@intel.com,
	leif.lindholm@linaro.org, michael.d.kinney@intel.com
Subject: Re: [PATCH v5 4/4] MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases
Date: Wed, 5 Apr 2017 15:12:01 -0500	[thread overview]
Message-ID: <bacc1d44-ddfa-9d80-2743-76e0cf22208a@arm.com> (raw)
In-Reply-To: <1473429644-13480-5-git-send-email-ard.biesheuvel@linaro.org>

Hi,

On 09/09/2016 09:00 AM, Ard Biesheuvel wrote:
> The new accelerated ARM and AARCH64 implementations take advantage of
> features that are only available when the MMU and Dcache are on. So
> restrict the use of this library to the DXE phase or later.

I don't think this is sufficient because DC ZVA doesn't work against 
device memory/etc. That means that users have to somehow know the 
page/etc attributes of memory regions before they call SetMemXX() on them.

I think this is a problem because nowhere in the UEFI specs do I see 
such restrictions on those memory operations.

For a specific problematic example, the LcdGraphicsOutputBlt.c uses it 
for BltVideoFill() and the target of that is likely not regular cached 
video memory.



>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> ---
>  MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> index 64d11b09ef06..5ddc0cbc2d77 100644
> --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
> @@ -116,6 +116,15 @@ [Sources.X64]
>    X64/CopyMem.S
>    X64/IsZeroBuffer.nasm
>
> +[Defines.ARM, Defines.AARCH64]
> +  #
> +  # The ARM implementations of this library may perform unaligned accesses, and
> +  # may use DC ZVA instructions that are only allowed when the MMU and D-cache
> +  # are on. Since SEC, PEI_CORE and PEIM modules may execute with the MMU off,
> +  # omit them from the supported module types list for this library.
> +  #
> +  LIBRARY_CLASS = BaseMemoryLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +
>  [Sources.ARM]
>    Arm/ScanMem.S       |GCC
>    Arm/SetMem.S        |GCC
>



  parent reply	other threads:[~2017-04-05 20:12 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-09 14:00 [PATCH v5 0/4] MdePkg: add ARM/AARCH64 support to BaseMemoryLib Ard Biesheuvel
2016-09-09 14:00 ` [PATCH v5 1/4] MdePkg/BaseMemoryLib: widen aligned accesses to 32 or 64 bits Ard Biesheuvel
2016-09-09 14:00 ` [PATCH v5 2/4] MdePkg/BaseMemoryLibOptDxe: add accelerated ARM routines Ard Biesheuvel
2016-09-09 14:00 ` [PATCH v5 3/4] MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines Ard Biesheuvel
2016-09-09 14:00 ` [PATCH v5 4/4] MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases Ard Biesheuvel
2016-09-13 14:49   ` Ard Biesheuvel
2016-09-13 15:00     ` Gao, Liming
2017-04-05 20:12   ` Jeremy Linton [this message]
2017-04-05 20:34     ` Ard Biesheuvel
2017-04-05 21:28       ` Jeremy Linton
2017-04-05 21:55         ` Ard Biesheuvel
2017-04-06  9:35           ` Leif Lindholm
2017-04-06  9:43             ` Ard Biesheuvel
2017-04-06 10:16               ` Leif Lindholm

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