From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 302A221A6F108 for ; Wed, 5 Apr 2017 13:12:04 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09A862B; Wed, 5 Apr 2017 13:12:03 -0700 (PDT) Received: from [192.168.229.136] (u201426.usa.arm.com [10.118.28.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 82A683F23B; Wed, 5 Apr 2017 13:12:02 -0700 (PDT) To: Ard Biesheuvel , edk2-devel@lists.01.org, liming.gao@intel.com, leif.lindholm@linaro.org, michael.d.kinney@intel.com References: <1473429644-13480-1-git-send-email-ard.biesheuvel@linaro.org> <1473429644-13480-5-git-send-email-ard.biesheuvel@linaro.org> From: Jeremy Linton Message-ID: Date: Wed, 5 Apr 2017 15:12:01 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <1473429644-13480-5-git-send-email-ard.biesheuvel@linaro.org> Subject: Re: [PATCH v5 4/4] MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: disallow use in SEC & PEI phases X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Apr 2017 20:12:04 -0000 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Hi, On 09/09/2016 09:00 AM, Ard Biesheuvel wrote: > The new accelerated ARM and AARCH64 implementations take advantage of > features that are only available when the MMU and Dcache are on. So > restrict the use of this library to the DXE phase or later. I don't think this is sufficient because DC ZVA doesn't work against device memory/etc. That means that users have to somehow know the page/etc attributes of memory regions before they call SetMemXX() on them. I think this is a problem because nowhere in the UEFI specs do I see such restrictions on those memory operations. For a specific problematic example, the LcdGraphicsOutputBlt.c uses it for BltVideoFill() and the target of that is likely not regular cached video memory. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf > index 64d11b09ef06..5ddc0cbc2d77 100644 > --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf > +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf > @@ -116,6 +116,15 @@ [Sources.X64] > X64/CopyMem.S > X64/IsZeroBuffer.nasm > > +[Defines.ARM, Defines.AARCH64] > + # > + # The ARM implementations of this library may perform unaligned accesses, and > + # may use DC ZVA instructions that are only allowed when the MMU and D-cache > + # are on. Since SEC, PEI_CORE and PEIM modules may execute with the MMU off, > + # omit them from the supported module types list for this library. > + # > + LIBRARY_CLASS = BaseMemoryLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER UEFI_APPLICATION > + > [Sources.ARM] > Arm/ScanMem.S |GCC > Arm/SetMem.S |GCC >