From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DDD2F1A1E00 for ; Fri, 2 Sep 2016 03:44:36 -0700 (PDT) Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 72CF08123B; Fri, 2 Sep 2016 10:44:36 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-76.phx2.redhat.com [10.3.116.76]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u82AiY5x030253; Fri, 2 Sep 2016 06:44:35 -0400 To: Ard Biesheuvel , edk2-devel@ml01.01.org References: <1472666379-25426-1-git-send-email-ard.biesheuvel@linaro.org> <1472666379-25426-6-git-send-email-ard.biesheuvel@linaro.org> Cc: leif.lindholm@linaro.org From: Laszlo Ersek Message-ID: Date: Fri, 2 Sep 2016 12:44:34 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <1472666379-25426-6-git-send-email-ard.biesheuvel@linaro.org> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Fri, 02 Sep 2016 10:44:36 +0000 (UTC) Subject: Re: [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Sep 2016 10:44:37 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 08/31/16 19:59, Ard Biesheuvel wrote: > @@ -308,8 +329,21 @@ PciHostBridgeGetRootBridges ( > mRootBridge.Io.Limit = IoBase + IoSize - 1; > mRootBridge.Mem.Base = Mmio32Base; > mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1; > - mRootBridge.MemAbove4G.Base = MAX_UINT64; > - mRootBridge.MemAbove4G.Limit = 0; > + > + if (sizeof (UINTN) == sizeof (UINT64)) { > + mRootBridge.MemAbove4G.Base = Mmio64Base; > + mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1; > + mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; > + } else { > + // > + // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit > + // architecture such as ARM, we will not be able to access 64-bit MMIO > + // BARs unless they are allocated below 4 GB. So ignore the range above > + // 4 GB in this case. > + // > + mRootBridge.MemAbove4G.Base = MAX_UINT64; > + mRootBridge.MemAbove4G.Limit = 0; > + } > > // > // No separate ranges for prefetchable and non-prefetchable BARs Please further restrict the one assignment mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; (while keeping it in its current location) with the following condition: if (Mmio64Size > 0) { mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; } We should only set this bit if there's actually a 64-bit MMIO aperture. With that, Reviewed-by: Laszlo Ersek (No need to repost the series just because of this; you can implement the above on commit.) Thanks! Laszlo