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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AS8PR08MB5895.eurprd08.prod.outlook.com (2603:10a6:20b:298::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.28; Tue, 18 May 2021 14:42:58 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688%7]) with mapi id 15.20.4129.031; Tue, 18 May 2021 14:42:58 +0000 Subject: Re: [edk2-platforms][PATCH v2 4/6] Drivers/OpTee: Add Aarch32 SVC IDs for 32bit Arm targets To: Etienne Carriere , devel@edk2.groups.io Cc: Ard Biesheuvel , Ilias Apalodimas , Leif Lindholm , Sughosh Ganu , Thomas Abraham , nd@arm.com References: <20210517055047.30814-1-etienne.carriere@linaro.org> <20210517055047.30814-4-etienne.carriere@linaro.org> From: "Sami Mujawar" Message-ID: Date: Tue, 18 May 2021 15:42:57 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2021 14:43:12.3414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a2e799d-d7e4-40e7-b08c-08d91a0b4332 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1880 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-GB Hi Etienn, This patch looks good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 17/05/2021 06:50 AM, Etienne Carriere wrote: > Add SMCCC function IDs for RPMB read/write service on 32bit architectures. > Define generic SP_SVC_RPMB_READ/SP_SVC_RPMB_WRITE IDs for native target > architecture (32b or 64b). > > Changes OpTeeRpmbFvb.c to use architecture agnostic macro > ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ for 32b and 64b support. > > Cc: Ard Biesheuvel > Cc: Ilias Apalodimas > Cc: Leif Lindholm > Cc: Sami Mujawar > Signed-off-by: Etienne Carriere > --- > Changes since v1: > - Use _AARCH64 (resp. _AARCH32) suffix instead of _64 (resp. _32) in > the added macros. > --- > Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c | 2 +- > Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h | 16 ++++++++++++++-- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c > index 5197c95abd..6eb19bed0e 100644 > --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c > +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.c > @@ -68,7 +68,7 @@ ReadWriteRpmb ( > > ZeroMem (&SvcArgs, sizeof (SvcArgs)); > > - SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64; > + SvcArgs.Arg0 = ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ; > SvcArgs.Arg1 = mStorageId; > SvcArgs.Arg2 = 0; > SvcArgs.Arg3 = SvcAct; > diff --git a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h > index c17fc287ef..9c2a4ea6a5 100644 > --- a/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h > +++ b/Drivers/OpTee/OpteeRpmbPkg/OpTeeRpmbFvb.h > @@ -13,8 +13,20 @@ > contract between OP-TEE and EDK2. > For more details check core/arch/arm/include/kernel/stmm_sp.h in OP-TEE > **/ > -#define SP_SVC_RPMB_READ 0xC4000066 > -#define SP_SVC_RPMB_WRITE 0xC4000067 > +#define SP_SVC_RPMB_READ_AARCH64 0xC4000066 > +#define SP_SVC_RPMB_WRITE_AARCH64 0xC4000067 > + > +#define SP_SVC_RPMB_READ_AARCH32 0x84000066 > +#define SP_SVC_RPMB_WRITE_AARCH32 0x84000067 > + > +#ifdef MDE_CPU_AARCH64 > +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_AARCH64 > +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_AARCH64 > +#endif > +#ifdef MDE_CPU_ARM > +#define SP_SVC_RPMB_READ SP_SVC_RPMB_READ_AARCH32 > +#define SP_SVC_RPMB_WRITE SP_SVC_RPMB_WRITE_AARCH32 > +#endif > > #define FLASH_SIGNATURE SIGNATURE_32 ('r', 'p', 'm', 'b') > #define INSTANCE_FROM_FVB_THIS(a) CR (a, MEM_INSTANCE, FvbProtocol, \