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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2021 20:54:53.5482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d7a3fc8-1e6d-4ca0-5fcd-08d9b9c3d1a9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB4604 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-GB Hi Chandni, Thank you for this patch. I have a minor suggestion marked inline as [SAMI]. Otherwise this patch looks good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 04/12/2021 12:30 PM, Chandni Cherukuri wrote: > From: Anurag Koul > > A custom PCI Segment library is required to handle multiple PCIe > segments in Morello, as the base PCI Segment library doesn't allow > supporting more than a single PCIe segment. > > This custom platform-specific PCI Segment Library has been adapted > from MdePkg/BasePciSegmentLib. > > Signed-off-by: Anurag Koul > Signed-off-by: Chandni Cherukuri > --- > Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.inf | 30 + > Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c | 1405 ++++++++++++++++++++ > 2 files changed, 1435 insertions(+) > > diff --git a/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.inf b/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.inf > new file mode 100644 > index 000000000000..c37458cba826 > --- /dev/null > +++ b/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.inf > @@ -0,0 +1,30 @@ > +## @file > +# PCI Segment Library for Morello SoC with multiple RCs > +# > +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> +# Copyright (c) 2021, ARM Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = PciSegmentLib > + FILE_GUID = 5811c256-4d1f-11ec-81d3-0242ac130003 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciSegmentLib > + > +[Sources] > + PciSegmentLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + Platform/ARM/Morello/MorelloPlatform.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + IoLib > + PciLib > diff --git a/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c b/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c > new file mode 100644 > index 000000000000..41a998830710 > --- /dev/null > +++ b/Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c > @@ -0,0 +1,1405 @@ > +/** @file > + PCI Segment Library for Morello SoC with multiple RCs > + > + Having two distinct root complexes is not supported by the standard > + set of PciLib/PciExpressLib/PciSegmentLib, this PciSegmentLib > + reimplements the functionality to support multiple root ports under > + different PCIe segments. > + > + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
> + Copyright (c) 2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +typedef enum { > + PciCfgWidthUint8 = 0, > + PciCfgWidthUint16, > + PciCfgWidthUint32, > + PciCfgWidthMax > +} PCI_CFG_WIDTH; > + > +/** > + Assert the validity of a PCI Segment address. > + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 > + > + @param A The address to validate. > + @param M Additional bits to assert to be zero. > +**/ > +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \ > + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) > + > +/** > + Internal worker function to read a PCI configuration register. > + > + @param [in] Address The address that encodes the PCI Bus, Device, Function > + and Register. > + @param [in] Width The width of data to read > + > + @return The value read from the PCI configuration register. > +**/ > +STATIC > +UINT32 > +PciSegmentLibReadWorker ( > + IN UINT64 Address, > + IN PCI_CFG_WIDTH Width > + ) > +{ > + switch (Width) { > + case PciCfgWidthUint8: > + return PciRead8 (Address); > + case PciCfgWidthUint16: > + return PciRead16 (Address); > + case PciCfgWidthUint32: > + return PciRead32 (Address); > + default: > + ASSERT (FALSE); > + } > + > + return 0; > +} > + > +/** > + Internal worker function to write to a PCI configuration register. > + > + @param [in] Address The address that encodes the PCI Bus, Device, Function > + and Register. > + @param [in] Width The width of data to write > + @param [in] Data The value to write. > + > + @return The value written to the PCI configuration register. > +**/ > +STATIC > +UINT32 > +PciSegmentLibWriteWorker ( > + IN UINT64 Address, > + IN PCI_CFG_WIDTH Width, > + IN UINT32 Data > + ) > +{ > + switch (Width) { > + case PciCfgWidthUint8: > + PciWrite8 (Address, Data); > + break; > + case PciCfgWidthUint16: > + PciWrite16 (Address, Data); > + break; > + case PciCfgWidthUint32: > + PciWrite32 (Address, Data); > + break; > + default: > + ASSERT (FALSE); > + } > + > + return Data; > +} > + > +/** > + Reads an 8-bit PCI configuration register. > + > + Reads and returns the 8-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are > + serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, > + Device, Function and Register. > + > + @return The 8-bit PCI configuration register specified by the Address. > +**/ > +UINT8 > +EFIAPI > +PciSegmentRead8 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); > + > + return (UINT8)PciSegmentLibReadWorker (Address, PciCfgWidthUint8); > +} > + > +/** > + Writes an 8-bit PCI configuration register. > + > + Writes the 8-bit Value in the PCI configuration register specified by the > + Address. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, > + Device, Function, and Register. > + @param [in] Value The value to write. > + > + @return The value written to the PCI configuration register. > +**/ > +UINT8 > +EFIAPI > +PciSegmentWrite8 ( > + IN UINT64 Address, > + IN UINT8 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); > + > + return (UINT8)PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value); > +} > + > +/** > + Performs a bitwise OR of an 8-bit PCI configuration register with > + an 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > +**/ > +UINT8 > +EFIAPI > +PciSegmentOr8 ( > + IN UINT64 Address, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + (UINT8)(PciSegmentRead8 (Address) | OrData) > + ); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with > + an 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > + AndData, and writes the result to the 8-bit PCI configuration register > + specified by Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. If any reserved bits in Address are set, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > +**/ > +UINT8 > +EFIAPI > +PciSegmentAnd8 ( > + IN UINT64 Address, > + IN UINT8 AndData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + (UINT8)(PciSegmentRead8 (Address) & AndData) > + ); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with > + an 8-bit value, followed by a bitwise OR with another 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified > + by AndData, performs a bitwise OR between the result of the AND operation > + and the value specified by OrData, and writes the result to the 8-bit > + PCI configuration register specified by Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentAndThenOr8 ( > + IN UINT64 Address, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData) > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in an 8-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to read. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..7. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..7. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldRead8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 8-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..7. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..7. > + @param [in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldWrite8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 Value > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..7. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..7. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 8-bit register. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 8-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..7. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..7. > + @param [in] AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAnd8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 8-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..7. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..7. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAndThenOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldAndThenOr8 ( > + PciSegmentRead8 (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ) > + ); > +} > + > +/** > + Reads a 16-bit PCI configuration register. > + > + Reads and returns the 16-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + > + @return The 16-bit PCI configuration register specified by Address. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentRead16 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); > + > + return (UINT16)PciSegmentLibReadWorker (Address, PciCfgWidthUint16); > +} > + > +/** > + Writes a 16-bit PCI configuration register. > + > + Writes the 16-bit PCI configuration register specified by Address with the > + value specified by Value. Value is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] Value The value to write. > + > + @return The Value written is returned. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentWrite16 ( > + IN UINT64 Address, > + IN UINT16 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); > + > + return (UINT16)PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value); > +} > + > +/** > + Performs a bitwise OR of a 16-bit PCI configuration register with > + a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function and Register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentOr16 ( > + IN UINT64 Address, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + (UINT16)(PciSegmentRead16 (Address) | OrData) > + ); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with > + a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified > + by AndData, and writes the result to the 16-bit PCI configuration register > + specified by the Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAnd16 ( > + IN UINT64 Address, > + IN UINT16 AndData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + (UINT16)(PciSegmentRead16 (Address) & AndData) > + ); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit > + value, followed a bitwise OR with another 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > + AndData, performs a bitwise OR between the result of the AND operation and > + the value specified by OrData, and writes the result to the 16-bit PCI > + configuration register specified by the Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAndThenOr16 ( > + IN UINT64 Address, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData) > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 16-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to read. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..15. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..15. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldRead16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 16-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..15. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..15. > + @param [in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldWrite16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 Value > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified > + by OrData, and writes the result to the 16-bit PCI configuration register > + specified by the Address. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..15. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..15. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, > + and writes the result back to the bit field in the 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by the Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. The ordinal of the least significant bit in a > + byte is bit 0. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. The ordinal of the most significant bit in a > + byte is bit 7. > + @param [in] AndData The value to AND with the read value from the PCI > + configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAnd16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 16-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..15. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..15. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAndThenOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldAndThenOr16 ( > + PciSegmentRead16 (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ) > + ); > +} > + > +/** > + Reads a 32-bit PCI configuration register. > + > + Reads and returns the 32-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function and Register. > + > + @return The 32-bit PCI configuration register specified by Address. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentRead32 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); > + > + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); > +} > + > +/** > + Writes a 32-bit PCI configuration register. > + > + Writes the 32-bit PCI configuration register specified by Address with the > + value specified by Value. Value is returned. This function must guarantee > + that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] Value The value to write. > + > + @return The parameter of Value. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentWrite32 ( > + IN UINT64 Address, > + IN UINT32 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); > + > + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); > +} > + > +/** > + Performs a bitwise OR of a 32-bit PCI configuration register with a > + 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified > + by OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentOr32 ( > + IN UINT64 Address, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with > + a 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified > + by AndData, and writes the result to the 32-bit PCI configuration register > + specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAnd32 ( > + IN UINT64 Address, > + IN UINT32 AndData > + ) > +{ > + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with > + a 32-bit value, followed by a bitwise OR with another 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified > + by AndData, performs a bitwise OR between the result of the AND operation > + and the value specified by OrData, and writes the result to the 32-bit > + PCI configuration register specified by Address. > + > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param [in] Address The address that encodes the PCI Segment, Bus, Device, > + Function and Register. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAndThenOr32 ( > + IN UINT64 Address, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + (PciSegmentRead32 (Address) & AndData) | OrData > + ); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 32-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to read. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..31. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..31. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldRead32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 32-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..31. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..31. > + @param [in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldWrite32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 Value > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..31. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..31. > + @param [in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldOr32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 32-bit register. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified > + by AndData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register > + is returned. This function must guarantee that all PCI read and write > + operations are serialized. Extra left bits in AndData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and > + EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..31. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..31. > + @param [in] AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldAnd32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 32-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit > + and EndBit, then ASSERT(). > + > + @param [in] Address The PCI configuration register to write. > + @param [in] StartBit The ordinal of the least significant bit in the bit > + field. Range 0..31. > + @param [in] EndBit The ordinal of the most significant bit in the bit > + field. Range 0..31. > + @param [in] AndData The value to AND with the PCI configuration register. > + @param [in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldAndThenOr32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldAndThenOr32 ( > + PciSegmentRead32 (Address), > + StartBit, > + EndBit, > + AndData, > + OrData > + ) > + ); > +} > + > +/** > + Reads a range of PCI configuration registers into a caller supplied buffer. > + > + Reads the range of PCI configuration registers specified by StartAddress and > + Size into the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be read. Size is > + returned. When possible 32-bit PCI configuration read cycles are used to read > + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit > + and 16-bit PCI configuration read cycles may be used at the beginning and the > + end of the range. > + > + If any reserved bits in StartAddress are set, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param [in] StartAddress The starting address that encodes the PCI Segment, > + Bus, Device, Function and Register. > + @param [in] Size The size in bytes of the transfer. > + @param [out] Buffer The pointer to a buffer receiving the data read. > + > + @return Size > + > +**/ > +UINTN > +EFIAPI > +PciSegmentReadBuffer ( > + IN UINT64 StartAddress, > + IN UINTN Size, > + OUT VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return Size; [SAMI] I think it should be possible to return 0 from here. > + } > + > + ASSERT (Buffer != NULL); > + > + // Save Size for return > + ReturnValue = Size; > + > + if ((StartAddress & BIT0) != 0) { > + // Read a byte if StartAddress is byte aligned > + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8 *)Buffer + 1; > + } > + > + if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) { > + // Read a word if StartAddress is word aligned > + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // Read as many double words as possible > + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // Read the last remaining word if exist > + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // Read the last remaining byte if exist > + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); > + } > + > + return ReturnValue; > +} > + > +/** > + Copies the data in a caller supplied buffer to a specified range of PCI > + configuration space. > + > + Writes the range of PCI configuration registers specified by StartAddress and > + Size from the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be written. Size is > + returned. When possible 32-bit PCI configuration write cycles are used to > + write from StartAdress to StartAddress + Size. Due to alignment restrictions, > + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning > + and the end of the range. > + > + If any reserved bits in StartAddress are set, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param [in] StartAddress The starting address that encodes the PCI Segment, > + Bus, Device, Function and Register. > + @param [in] Size The size in bytes of the transfer. > + @param [in] Buffer The pointer to a buffer containing the data to write. > + > + @return The parameter of Size. > + > +**/ > +UINTN > +EFIAPI > +PciSegmentWriteBuffer ( > + IN UINT64 StartAddress, > + IN UINTN Size, > + IN VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return 0; > + } > + > + ASSERT (Buffer != NULL); > + > + // Save Size for return > + ReturnValue = Size; > + > + if ((StartAddress & BIT0) != 0) { > + // Write a byte if StartAddress is byte aligned > + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8 *)Buffer + 1; > + } > + > + if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) { > + // Write a word if StartAddress is word aligned > + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // Write as many double words as possible > + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // Write the last remaining word if exist > + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // Write the last remaining byte if exist > + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); > + } > + > + return ReturnValue; > +}