From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.12290.1673007644199874068 for ; Fri, 06 Jan 2023 04:20:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=QqaEBgRI; spf=pass (domain: redhat.com, ip: 170.10.129.124, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673007643; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+ET9j6UZmmYgy/XDwfe/8L9w46Xu8ACfbfO5X9GXZ3g=; b=QqaEBgRIktcISDNQu1NU+/dP2JTRkDhgm4P7BwuRCwsj1oLqOR26A9HfDa9gFJD3l47MYP LtM659WogYO0UfjkVFdEsz1YU7GDieQJwCeexhp08NyqJjQGI07HN0lLYbIpR1lS7f6Gj8 NYf8GXEYcXnuEAi3Z+TnaT2NqU13OKU= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-189-oZPjfi9dMXmKoxEqnVQyWA-1; Fri, 06 Jan 2023 07:20:40 -0500 X-MC-Unique: oZPjfi9dMXmKoxEqnVQyWA-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id F1E312A59556; Fri, 6 Jan 2023 12:20:39 +0000 (UTC) Received: from [10.39.192.26] (unknown [10.39.192.26]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D7032C15BAD; Fri, 6 Jan 2023 12:20:38 +0000 (UTC) Message-ID: Date: Fri, 6 Jan 2023 13:20:37 +0100 MIME-Version: 1.0 Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg:Fixed AsmRelocateApLoopStart and ensure allocated memory <4GB To: Gerd Hoffmann Cc: devel@edk2.groups.io, ray.ni@intel.com, "ardb@kernel.org" , "Xie, Yuanhao" , "thomas.lendacky@amd.com" References: <20230105062108.1796-1-yuanhao.xie@intel.com> <20230106080300.tsohpx24ddxjo5x4@sirius.home.kraxel.org> <28b1ecd3-631e-8f00-6495-acd9ec76037b@redhat.com> <236acf95-68b9-16c7-f34f-4a57c73a8137@redhat.com> <20230106111449.hirlrxwof2v5dc7i@sirius.home.kraxel.org> From: "Laszlo Ersek" In-Reply-To: <20230106111449.hirlrxwof2v5dc7i@sirius.home.kraxel.org> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/6/23 12:14, Gerd Hoffmann wrote: > Hi, > >> Now, there *is* one benefit I can imagine. For Intel maintainers, it may >> be difficult to maintain and to "route around" the SEV-related stuff in >> "X64/MpFuncs.nasm", in the long term. I can wholly accept that. So >> splitting and duplicating the assembly code for that purpose is >> justified. But then the commit message should state this, and not >> present "staying in 64-bit" as a benefit per se. >> >> Then the purpose is to ease the assembly code maintenance for Intel >> developers. Entirely justified goal in my view; nobody likes to work >> with complicated code they can't regression-test (and I presume Intel >> developers can't easily test the various SEV enablement levels in-house, >> on a range of AMD processors). > > Which is exactly why I suggested to catch the SEV case by checking the > PCD we have for that in C code. That'll also remove the confusion we > have right now wrt intel + amd processors. The special case we have to > worry about is SEV being active, not running on a AMD processor. In > case SEV is not active we'll just have the IA32 and X64 cases. Thanks for repeating your suggestion. It seems very plausible, on second reading. I guess I just couldn't grasp it enough the first time you proposed it, sorry. I'd be very interested to see this in actual code! Thanks! Laszlo