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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:07:56 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:56 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v5 29/42] OvmfPkg: Create GHCB pages for use during Pei and Dxe phase Date: Mon, 2 Mar 2020 17:07:00 -0600 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:07:55 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6466c5a1-0f9e-4b29-a5cf-08d7befe8b2f X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 033054F29A X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(376002)(366004)(136003)(346002)(396003)(39860400002)(199004)(189003)(66946007)(8936002)(54906003)(316002)(81156014)(81166006)(19627235002)(6486002)(6916009)(6666004)(66556008)(8676002)(4326008)(66476007)(52116002)(7696005)(2616005)(5660300002)(2906002)(36756003)(186003)(966005)(86362001)(478600001)(16526019)(26005)(956004);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR12MB4201;H:DM6PR12MB3163.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JTzGsYl2X1Y4M6WTO52whkFUVlMzPxp7AAZXlDZNy9IuCZPTf/fTlqiAjm//GcwJjSBuGlIFiCJl1aFmWva7QFYu5PYgW/AifAKVSM2aMjISvZFoUlhLsbBrsBqYtDnZ4/LjpnfgHpN9+pw2t12oeEFvt/Ylg0JeXrp7PFss6IhbXARLnoy95n91/03R0Vl2uii2ms0CebXC4wDzQ1MSZdm9pqKs2yqanqwm4fRCFW4NfwTm5tXSbio2+HFpPS81zYNgOLm1Nyvp2TDybcfzNQLOvvVZEbshfRF2yVlX9nC+hdj7Y8WXP4RYaJvMEIu6N6aRXhtm/iMK4gx9JNpXdE1/q94HsczXkKpgaWd6TgKxo7fFnAqck/Dg5ewQRbENaolaRvhP7Toz1kKGocuHiwMVheC9bzpg6fEGWeTw/mITW474JgWp99upySmxe9w7HJMqTwzZBuRP2uCOCI9XexUHa5K+YiqNKrP168H+7SOE0fD0uwLttUJ7sko4DEjN/eMq3IQRddiKepCngTZtHQ== X-MS-Exchange-AntiSpam-MessageData: 3g7E2cxN/+boz6FS7ZVtFhY4ofwX9dpBZdBmQxyoasrN7E/m/Vc8Yjf4M2VrU0siwJ00aLntfHtkbcfvIgJedPMzv/8huCwNgbhELF5fZr9uSHe4z3MTBkq55zl/U39xpSTS5TKQnRJRAmG2ExMOUw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6466c5a1-0f9e-4b29-a5cf-08d7befe8b2f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:56.4459 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kYHzpbH9OEDXfk2fX3C9TUeuLEQkd5zSSJ124V7F4EGz9/ZmTW+sUFeDHVdAHFgdsSE3uGFYNRGZr/LKJyBpYA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Allocate memory for the GHCB pages and the per-CPU variable pages during SEV initialization for use during Pei and Dxe phases. The GHCB page(s) must be shared pages, so clear the encryption mask from the current page table entries. Upon successful allocation, set the GHCB PCDs (PcdGhcbBase and PcdGhcbSize). The per-CPU variable page needs to be unique per AP. Using the page after the GHCB ensures that it is unique per AP. But, it also ends up being marked shared/unencrypted when it doesn't need to be. It is possible during PEI to mark only the GHCB pages as shared (and that is done), but DXE is not as easy. There needs to be a way to change the pagetables created for DXE using CreateIdentityMappingPageTables() before switching to them. The GHCB pages (one per vCPU) will be used by the PEI and DXE #VC exception handlers. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB associated with the vCPU in order to perform the requested function. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 2 ++ OvmfPkg/OvmfPkgIa32X64.dsc | 2 ++ OvmfPkg/OvmfPkgX64.dsc | 2 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 2 ++ OvmfPkg/PlatformPei/AmdSev.c | 38 ++++++++++++++++++++++++++++- 5 files changed, 45 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 6eb3817909f4..51d7acafdda3 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -568,6 +568,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index fa521321e2b3..764fa8c287a0 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -580,6 +580,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index dd6f86fa087d..b6e29e09db97 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -579,6 +579,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index f1c2024526c8..47fc7e9c65aa 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -100,6 +100,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 4dc5340caa7a..5f0946763507 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -10,12 +10,15 @@ // The package level header files this module uses // #include +#include #include #include #include +#include #include #include #include +#include #include #include @@ -32,7 +35,10 @@ AmdSevEsInitialize ( VOID ) { - RETURN_STATUS PcdStatus; + VOID *GhcbBase; + PHYSICAL_ADDRESS GhcbBasePa; + UINTN GhcbPageCount; + RETURN_STATUS PcdStatus, DecryptStatus; if (!MemEncryptSevEsIsEnabled ()) { return; @@ -40,6 +46,36 @@ AmdSevEsInitialize ( PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE); ASSERT_RETURN_ERROR (PcdStatus); + + // + // Allocate GHCB and per-CPU variable pages. + // + GhcbPageCount = mMaxCpuCount * 2; + GhcbBase = AllocatePages (GhcbPageCount); + ASSERT (GhcbBase != NULL); + + GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase; + + DecryptStatus = MemEncryptSevClearPageEncMask ( + 0, + GhcbBasePa, + GhcbPageCount, + TRUE + ); + ASSERT_RETURN_ERROR (DecryptStatus); + + ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount)); + + PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount)); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG ((DEBUG_INFO, + "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n", + (UINT64)GhcbPageCount, GhcbBase)); + + AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); } /** -- 2.17.1