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Wed, 26 Apr 2023 02:23:01 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Ard Biesheuvel , Jiewen Yao , Jordan Justen , "Abdul Lateef Attar" Subject: [PATCH v9 7/9] UefiCpuPkg: Implements MmSaveStateLib for Ovmf Date: Wed, 26 Apr 2023 12:52:25 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT058:EE_|MN2PR12MB4318:EE_ X-MS-Office365-Filtering-Correlation-Id: fdb802d9-e9b7-4205-4acb-08db46272891 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QaLizssI1xnjrfmG7KvdUsXN5VxdvAGNQf6CD/awdQ05HwuLCVN1m9s2S42hpH/chUE2IuoTUCoKp4oyNEp1kQwHAsshJTTxP/7rS5IDXVihNnEAefj/gfXLwx6nj2FkFlvsi3hACKkpD9kEWEaR/0Be6e5g6fx7+oKTs7LdG7+vq+XcdsSFcmW4w41okIHaEnBk+6VVfkohRS5GxqzzKJDRB9EOzAr0E5Vw9HkclaIw5aXCaCO9DZHcc4dnRRQQVclkXWEvX09943UOF8n/NFw0Y1qykqock6m4dSp97xESZ1aROiJlTinfN9O49ycF48buiGPC1Mcr28GrhUjbiHbj7560OGtUgmG+rSxZF4Bf0XiITEZiXJhkm+4URreZsyC0+k5B/xbwLJPNYfTR1siBLrySvA7moZUYppXz1YgAKnGJlULm0zw/sdt5WGtCHYtYyitXD5n7m4lByiwEn/VsWp6ytLoABPDZvHgLcQi07t/xNNhlzm7Pj9fl7REjEx++RU4fK5sMY0YBwoAS8D5YUxkihJpBwzhMxiypczqY/vzgmZLHuRPY+F+LKfCEWzottGoIF1ep/G9qBDW6rNE5XtazT2XABidaXM1Tm4yxETLgJWK3iZtr33wNiQ9b4BxQ8wr8fTQNW/gW7iF8/CH371eqC3n0969JaWC7c2B4/jniuXSpGG/SoyP7mj9ympo2wKzvHoTt4l+ki6IDEIi3WhiGRt9xnquA94HwpX8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(6029001)(4636009)(346002)(396003)(136003)(376002)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(30864003)(966005)(2906002)(7696005)(19627235002)(336012)(36860700001)(47076005)(83380400001)(36756003)(82310400005)(40460700003)(426003)(70586007)(8936002)(316002)(478600001)(26005)(6666004)(2616005)(70206006)(41300700001)(6916009)(186003)(4326008)(40480700001)(82740400003)(81166007)(356005)(54906003)(8676002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2023 07:23:40.0555 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdb802d9-e9b7-4205-4acb-08db46272891 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4318 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Implements MmSaveStateLib library interfaces to read and write save state registers for Ovmf/Qemu. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Signed-off-by: Abdul Lateef Attar --- UefiCpuPkg/UefiCpuPkg.dsc | 10 + .../MmSaveStateLib/OvmfMmSaveStateLib.inf | 29 + .../Library/MmSaveStateLib/OvmfMmSaveState.c | 612 ++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 4 files changed, 652 insertions(+) create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.in= f create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveState.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index cc681b6b5b07..8ca04968c550 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -179,6 +179,15 @@ [Components.IA32, Components.X64] SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/S= mmCpuPlatformHookLibNull.inf MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.i= nf } + + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + FILE_GUID =3D 8734325E-DEAD-4742-A582-EC6E0E1CDE2B + + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/S= mmCpuPlatformHookLibNull.inf + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.= inf + } + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf @@ -196,6 +205,7 @@ [Components.IA32, Components.X64] } UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf + UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf =20 [Components.X64] diff --git a/UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.inf b/Uef= iCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.inf new file mode 100644 index 000000000000..68f5813db21e --- /dev/null +++ b/UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveStateLib.inf @@ -0,0 +1,29 @@ +## @file +# MM Smram save state service lib. +# +# This is MM Smram save state service lib that provide service to read and +# save savestate area registers. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D OvmfMmSaveStateLib + FILE_GUID =3D 689676f1-6da9-4169-b8bd-be4437e68c36 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MmSaveStateLib + +[Sources] + MmSaveState.h + MmSaveStateCommon.c + OvmfMmSaveState.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveState.c b/UefiCpuP= kg/Library/MmSaveStateLib/OvmfMmSaveState.c new file mode 100644 index 000000000000..19b5f0399fff --- /dev/null +++ b/UefiCpuPkg/Library/MmSaveStateLib/OvmfMmSaveState.c @@ -0,0 +1,612 @@ +/** @file +Provides services to access SMRAM Save State Map + +Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MmSaveState.h" +#include +#include + +/// +/// Macro used to simplify the lookup table entries of type +/// CPU_MM_SAVE_STATE_LOOKUP_ENTRY +/// +#define MM_CPU_OFFSET(Field) OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field) + +/// +/// Lookup table used to retrieve the widths and offsets associated with e= ach +/// supported EFI_MM_SAVE_STATE_REGISTER value +/// +CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY mCpuWidthOffset[] =3D { + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + 0, // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // Reserved + + // + // CPU Save State registers defined in PI SMM CPU Protocol. + // + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo + MM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_GDTBASE =3D 4 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._IDTRBase), // Offset64Lo + MM_CPU_OFFSET (x64._IDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_IDTBASE =3D 5 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._LDTRBase), // Offset64Lo + MM_CPU_OFFSET (x64._LDTRBase) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_LDTBASE =3D 6 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._GDTRLimit), // Offset64Lo + MM_CPU_OFFSET (x64._GDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT =3D 7 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._IDTRLimit), // Offset64Lo + MM_CPU_OFFSET (x64._IDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT =3D 8 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._LDTRLimit), // Offset64Lo + MM_CPU_OFFSET (x64._LDTRLimit) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT =3D 9 + + { + 0, // Width32 + 0, // Width64 + 0, // Offset32 + 0, // Offset64Lo + 0 + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_LDTINFO =3D 10 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._ES), // Offset32 + MM_CPU_OFFSET (x64._ES), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_ES =3D 20 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._CS), // Offset32 + MM_CPU_OFFSET (x64._CS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_CS =3D 21 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._SS), // Offset32 + MM_CPU_OFFSET (x64._SS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_SS =3D 22 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._DS), // Offset32 + MM_CPU_OFFSET (x64._DS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_DS =3D 23 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._FS), // Offset32 + MM_CPU_OFFSET (x64._FS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_FS =3D 24 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._GS), // Offset32 + MM_CPU_OFFSET (x64._GS), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_GS =3D 25 + + { + 0, // Width32 + 4, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._LDTR), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL =3D 26 + + { + 4, // Width32 + 4, // Width64 + MM_CPU_OFFSET (x86._TR), // Offset32 + MM_CPU_OFFSET (x64._TR), // Offset64Lo + 0, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_TR_SEL =3D 27 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._DR7), // Offset32 + MM_CPU_OFFSET (x64._DR7), // Offset64Lo + MM_CPU_OFFSET (x64._DR7) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_DR7 =3D 28 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._DR6), // Offset32 + MM_CPU_OFFSET (x64._DR6), // Offset64Lo + MM_CPU_OFFSET (x64._DR6) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_DR6 =3D 29 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R8), // Offset64Lo + MM_CPU_OFFSET (x64._R8) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R8 =3D 30 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R9), // Offset64Lo + MM_CPU_OFFSET (x64._R9) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R9 =3D 31 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R10), // Offset64Lo + MM_CPU_OFFSET (x64._R10) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R10 =3D 32 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R11), // Offset64Lo + MM_CPU_OFFSET (x64._R11) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R11 =3D 33 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R12), // Offset64Lo + MM_CPU_OFFSET (x64._R12) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R12 =3D 34 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R13), // Offset64Lo + MM_CPU_OFFSET (x64._R13) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R13 =3D 35 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R14), // Offset64Lo + MM_CPU_OFFSET (x64._R14) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R14 =3D 36 + + { + 0, // Width32 + 8, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._R15), // Offset64Lo + MM_CPU_OFFSET (x64._R15) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_R15 =3D 37 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EAX), // Offset32 + MM_CPU_OFFSET (x64._RAX), // Offset64Lo + MM_CPU_OFFSET (x64._RAX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RAX =3D 38 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EBX), // Offset32 + MM_CPU_OFFSET (x64._RBX), // Offset64Lo + MM_CPU_OFFSET (x64._RBX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RBX =3D 39 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._ECX), // Offset32 + MM_CPU_OFFSET (x64._RCX), // Offset64Lo + MM_CPU_OFFSET (x64._RCX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RCX =3D 40 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EDX), // Offset32 + MM_CPU_OFFSET (x64._RDX), // Offset64Lo + MM_CPU_OFFSET (x64._RDX) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RDX =3D 41 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._ESP), // Offset32 + MM_CPU_OFFSET (x64._RSP), // Offset64Lo + MM_CPU_OFFSET (x64._RSP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RSP =3D 42 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EBP), // Offset32 + MM_CPU_OFFSET (x64._RBP), // Offset64Lo + MM_CPU_OFFSET (x64._RBP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RBP =3D 43 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._ESI), // Offset32 + MM_CPU_OFFSET (x64._RSI), // Offset64Lo + MM_CPU_OFFSET (x64._RSI) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RSI =3D 44 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EDI), // Offset32 + MM_CPU_OFFSET (x64._RDI), // Offset64Lo + MM_CPU_OFFSET (x64._RDI) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RDI =3D 45 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EIP), // Offset32 + MM_CPU_OFFSET (x64._RIP), // Offset64Lo + MM_CPU_OFFSET (x64._RIP) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RIP =3D 46 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._EFLAGS), // Offset32 + MM_CPU_OFFSET (x64._RFLAGS), // Offset64Lo + MM_CPU_OFFSET (x64._RFLAGS) + 4, // Offset64Hi + TRUE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_RFLAGS =3D 51 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._CR0), // Offset32 + MM_CPU_OFFSET (x64._CR0), // Offset64Lo + MM_CPU_OFFSET (x64._CR0) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_CR0 =3D 52 + + { + 4, // Width32 + 8, // Width64 + MM_CPU_OFFSET (x86._CR3), // Offset32 + MM_CPU_OFFSET (x64._CR3), // Offset64Lo + MM_CPU_OFFSET (x64._CR3) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_CR3 =3D 53 + + { + 0, // Width32 + 4, // Width64 + 0, // Offset32 + MM_CPU_OFFSET (x64._CR4), // Offset64Lo + MM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi + FALSE // Writeable + }, // EFI_MM_SAVE_STATE_REGISTER_CR4 =3D 54 +}; + +/** + Read a save state register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + MM Save State register. + + @param[in] CpuIndex The index of the CPU to read the Save State regist= er. + The value must be between 0 and the NumberOfCpus f= ield in + the System Management System Table (SMST). + @param[in] Register The MM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save stat= e. + @param[out] Buffer Upon return, this holds the CPU register value rea= d + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +MmSaveStateReadRegister ( + IN UINTN CpuIndex, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + UINTN RegisterIndex; + QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Check for special EFI_MM_SAVE_STATE_REGISTER_LMA + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA) { + // + // Only byte access is supported for this register + // + if (Width !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuI= ndex]; + + // + // Check CPU mode + // + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + *(UINT8 *)Buffer =3D 32; + } else { + *(UINT8 *)Buffer =3D 64; + } + + return EFI_SUCCESS; + } + + // + // Check for special EFI_MM_SAVE_STATE_REGISTER_IO + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index. Let + // PiSmmCpuDxeSmm implement other special registers (currently + // there is only EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID). + // + RegisterIndex =3D MmSaveStateGetRegisterIndex (Register); + if (RegisterIndex =3D=3D 0) { + return (Register < EFI_MM_SAVE_STATE_REGISTER_IO ? + EFI_NOT_FOUND : + EFI_UNSUPPORTED); + } + + return MmSaveStateReadRegisterByIndex (CpuIndex, RegisterIndex, Width, B= uffer); +} + +/** + Writes a save state register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + MM save state register. + + @param[in] CpuIndex The index of the CPU to write the MM Save State. T= he + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] Register The MM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +MmSaveStateWriteRegister ( + IN UINTN CpuIndex, + IN EFI_MM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + UINTN RegisterIndex; + QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_LMA) { + return EFI_SUCCESS; + } + + // + // Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported + // + if (Register =3D=3D EFI_MM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index. Let + // PiSmmCpuDxeSmm implement other special registers (currently + // there is only EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID). + // + RegisterIndex =3D MmSaveStateGetRegisterIndex (Register); + if (RegisterIndex =3D=3D 0) { + return (Register < EFI_MM_SAVE_STATE_REGISTER_IO ? + EFI_NOT_FOUND : + EFI_UNSUPPORTED); + } + + CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; + + // + // Do not write non-writable SaveState, because it will cause exception. + // + if (!mCpuWidthOffset[RegisterIndex].Writeable) { + return EFI_UNSUPPORTED; + } + + // + // Check CPU mode + // + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + // + // If 32-bit mode width is zero, then the specified register can not b= e + // accessed + // + if (mCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified + // register can not be accessed + // + if (Width > mCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write SMM State register + // + ASSERT (CpuSaveState !=3D NULL); + CopyMem ( + (UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset32, + Buffer, + Width + ); + } else { + // + // If 64-bit mode width is zero, then the specified register can not b= e + // accessed + // + if (mCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified + // register can not be accessed + // + if (Width > mCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write lower 32-bits of SMM State register + // + CopyMem ( + (UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Lo, + Buffer, + MIN (4, Width) + ); + if (Width >=3D 4) { + // + // Write upper 32-bits of SMM State register + // + CopyMem ( + (UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, + (UINT8 *)Buffer + 4, + Width - 4 + ); + } + } + + return EFI_SUCCESS; +} + +/** + Returns LMA value of the Processor. + + @param[in] CpuIndex Specifies the zero-based index of the CPU save sta= te. + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +EFIAPI +MmSaveStateGetRegisterLma ( + IN UINTN CpuIndex + ) +{ + QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; + + if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { + return EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT; + } + + return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT; +} diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml index c2280aedf5ce..b7b7a65ac352 100644 --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml @@ -44,6 +44,7 @@ "AcceptableDependencies": [ "MdePkg/MdePkg.dec", "MdeModulePkg/MdeModulePkg.dec", + "OvmfPkg/OvmfPkg.dec", "UefiCpuPkg/UefiCpuPkg.dec" ], # For host based unit tests --=20 2.25.1