From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 602AB7803D8 for ; Fri, 5 Jan 2024 13:52:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=2jG+hbahrM2XY8L93A8o1SRzusV47WqerSpeQduBsv4=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1704462753; v=1; b=pdmWQxHc7pTgitH5blAr5PVaUwySeibOUbly2rKk5ixOvNXZxvGQlGHT2+14Dy+AcyLU1Ufp xkq/Ol9mBEqI9LACn6BdQdLZ1NiJxWIL3Xk9JxIR9RTai7fq/1204eb+KYlrxXeEMPc3vxFln+D mabAmL8AIXcNGhc+hE4OQMQY= X-Received: by 127.0.0.2 with SMTP id RJDWYY7687511xSjf3el8GxA; Fri, 05 Jan 2024 05:52:33 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web10.23769.1704462752353645055 for ; Fri, 05 Jan 2024 05:52:32 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-588-hN2s8efpNXqO4fM6Mq3boQ-1; Fri, 05 Jan 2024 08:52:26 -0500 X-MC-Unique: hN2s8efpNXqO4fM6Mq3boQ-1 X-Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 395BC884341; Fri, 5 Jan 2024 13:52:26 +0000 (UTC) X-Received: from [10.39.193.6] (unknown [10.39.193.6]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 519483C25; Fri, 5 Jan 2024 13:52:25 +0000 (UTC) Message-ID: Date: Fri, 5 Jan 2024 14:52:24 +0100 MIME-Version: 1.0 Subject: Re: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc To: Sunil V L Cc: devel@edk2.groups.io, Gerd Hoffmann , Rahul Kumar , Ray Ni , Andrei Warkentin References: <20240103135849.127251-1-sunilvl@ventanamicro.com> <20240103135849.127251-4-sunilvl@ventanamicro.com> From: "Laszlo Ersek" In-Reply-To: X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: GEFkxiI9cZJ6Xd40Mb4ybFfpx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=pdmWQxHc; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On 1/4/24 16:46, Sunil V L wrote: > On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote: >> On 1/3/24 14:58, Sunil V L wrote: >>> Sstc extension allows to program the timer and receive the interrupt >>> without using an SBI call. This reduces the latency to generate the tim= er >>> interrupt. So, detect whether Sstc extension is supported and use the >>> stimecmp register directly to program the timer interrupt. >>> >>> Cc: Gerd Hoffmann >>> Cc: Rahul Kumar >>> Cc: Laszlo Ersek >>> Cc: Ray Ni >>> Cc: Andrei Warkentin >>> Signed-off-by: Sunil V L >>> --- >>> .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + >>> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 ++ >>> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +++++++++++++++++-- >>> 3 files changed, 31 insertions(+), 2 deletions(-) >>> >>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/Uef= iCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> index aba660186dc0..f2a2cf12caef 100644 >>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> @@ -41,6 +41,7 @@ [Sources.RISCV64] >>> Timer.c >>> =20 >>> [Pcd] >>> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUM= ES >>> gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUM= ES >>> =20 >>> [Protocols] >>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTime= rDxeRiscV64/Timer.h >>> index 9b3542230cb5..5e5071b3f0b2 100644 >>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> @@ -26,6 +26,8 @@ >>> // >>> #define DEFAULT_TIMER_TICK_DURATION 100000 >>> =20 >>> +#define RISCV_CPU_FEATURE_SSTC_BITMASK 0x2 >> >> (1) Not a bug by any means, but BIT1 might read more idiomatic. >> > I misunderstood your comment. Will use BIT1 instead of 0x2. OK then :) -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113285): https://edk2.groups.io/g/devel/message/113285 Mute This Topic: https://groups.io/mt/103501843/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-