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Subject: Re: [edk2-devel] [PATCH v2 14/17] Silicon/Ampere: Update ArmPlatformLib to work with changed ARM_CORE_INFO
To: Leif Lindholm <quic_llindhol@quicinc.com>, devel@edk2.groups.io
CC: Rebecca Cran <rebecca@nuviainc.com>,
 Ard Biesheuvel <ardb+tianocore@kernel.org>,
 Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>,
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 Graeme Gregory <graeme@nuviainc.com>, Radoslaw Biernacki <rad@semihalf.com>,
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References: <20211216220800.9628-1-rebecca@nuviainc.com>
 <20211216220800.9628-15-rebecca@nuviainc.com>
 <e655c8d4-7a05-5ca1-e31d-b221c5b6ced9@os.amperecomputing.com>
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From: "Nhi Pham" <nhi@os.amperecomputing.com>
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Hi Leif,

On 25/03/2022 23:30, Leif Lindholm wrote:
> Hi Nhi,
>
> On Sun, Dec 19, 2021 at 10:35:41 +0700, Nhi Pham via groups.io wrote:
>> Hi Rebecca,
>>
>> Leif is merging the rest of Altra port to the edk2-platforms which has S=
RAT
>> ACPI table consuming the CPU Core Info table. Therefore, we will need to=
 fix
>> the SRAT too. I would defer the fix until the Altra port is fully merged=
.
>>
>> On 17/12/2021 05:07, Rebecca Cran wrote:
>>> The ARM_CORE_INFO struct has been updated so the MPIDR is now a single
>>> field instead of separate cluster/core fields. Update ArmPlatformLib.
>>>
>>> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
>>> ---
>>>    Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.=
c | 5 ++---
>>>    1 file changed, 2 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPl=
atformLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatf=
ormLib.c
>>> index 5b4be0e55516..f2ec923d6f8d 100644
>>> --- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformL=
ib.c
>>> +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformL=
ib.c
>>> @@ -108,9 +108,8 @@ PrePeiCoreGetMpCoreInfo (
>>>        }
>>>        SocketId =3D SOCKET_ID (Index);
>>>        ClusterId =3D CLUSTER_ID (Index);
>>> -    mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].ClusterId =3D S=
ocketId;
>>> -    mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].CoreId =3D
>>> -      (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM);
>>> +    mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].Mpidr =3D GET_M=
PID (
>>> +      SocketId, (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER=
_CPM));
>> For Ampere Altra, the correct MPIDR encoding is SocketId << 32 | Cluster=
Id
>> << 16 | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM) << 8
>>
>> It would be the same what
>> Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiMadt.c (not availabl=
e
>> yet - being merged in) is describing.
> This patch already got merged, so if you feel it is wrong, could you
> submit a fix please?
>
> The next patch for me to push from your set otherwise also requires
> some changes. My na=C3=AFve attempt would look something like:
>
> diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c b=
/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
> index 906b771a250c..d5bc732b08bb 100644
> --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
> +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiSrat.c
> @@ -7,6 +7,7 @@
>   **/
>  =20
>   #include <Guid/ArmMpCoreInfo.h>
> +#include <Library/ArmLib.h>
>   #include "AcpiPlatform.h"
>  =20
>   EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER SRATTableHeaderTempl=
ate =3D {
> @@ -119,6 +120,7 @@ SratAddGiccAffinity (
>     UINTN               Count, NumNode, Idx;
>     UINT32              AcpiProcessorUid;
>     UINT8               Socket;
> +  UINT8               Core;
>     UINT8               Cpm;
>  =20
>     for (Idx =3D 0; Idx < gST->NumberOfTableEntries; Idx++) {
> @@ -137,14 +139,14 @@ SratAddGiccAffinity (
>     NumNode =3D 0;
>     while (Count !=3D ArmProcessorTable->NumberOfEntries) {
>       for (Idx =3D 0; Idx < ArmProcessorTable->NumberOfEntries; Idx++ ) {
> -      Socket =3D ArmCoreInfoTable[Idx].ClusterId;
> -      Cpm =3D (ArmCoreInfoTable[Idx].CoreId >> PLATFORM_CPM_UID_BIT_OFFS=
ET);
> +      Socket =3D GET_MPIDR_AFF1 (ArmCoreInfoTable[Idx].Mpidr);
> +      Core   =3D GET_MPIDR_AFF0 (ArmCoreInfoTable[Idx].Mpidr);
> +      Cpm =3D Core >> PLATFORM_CPM_UID_BIT_OFFSET;
>         if (CpuGetSubNumNode (Socket, Cpm) !=3D NumNode) {
>           /* We add nodes based on ProximityDomain order */
>           continue;
>         }
> -      AcpiProcessorUid =3D (ArmCoreInfoTable[Idx].ClusterId << PLATFORM_=
SOCKET_UID_BIT_OFFSET) +
> -                         ArmCoreInfoTable[Idx].CoreId;
> +      AcpiProcessorUid =3D (Socket << PLATFORM_SOCKET_UID_BIT_OFFSET) + =
Core;
>         ZeroMem ((VOID *)&SratGiccAffinity[Count], sizeof (SratGiccAffini=
ty[Count]));
>         SratGiccAffinity[Count].AcpiProcessorUid =3D AcpiProcessorUid;
>         SratGiccAffinity[Count].Flags =3D 1;
>
> Would you be happy for me to fold that into
> "AmpereAltraPkg, JadePkg: Add ACPI support", or would you be able to
> submit a v6 of that patch only?
>
> Best Regards,
>
> Leif

Thanks much for the patch. The MPIDR decoding matches with Rebecca's=20
update for the ArmPlatformLib earlier and the ARM_CORE_INFO is just=20
consumed in the AcpiSrat.c. So, that is good for now. Please help fold=20
that into the ACPI patch when merging the rest of the Mt. Jade support=20
patchset.

In the future, I will follow up with a patch that makes the=20
representation of MPIDR in the ARM_CORE_INFO the same as in MADT table.

Thanks,

Nhi