From: "Nhi Pham" <nhi@os.amperecomputing.com>
To: Leif Lindholm <leif@nuviainc.com>
Cc: devel@edk2.groups.io, patches@amperecomputing.com,
vunguyen@os.amperecomputing.com,
Thang Nguyen <thang@os.amperecomputing.com>,
Chuong Tran <chuong@os.amperecomputing.com>,
Phong Vo <phong@os.amperecomputing.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: Re: [edk2-platforms][PATCH v4 16/31] AmpereAltraPkg: Add PciSegmentLib library instance
Date: Wed, 3 Nov 2021 16:35:03 +0700 [thread overview]
Message-ID: <c1fc4beb-a9a6-2dc8-dbc8-dcded62a3da4@os.amperecomputing.com> (raw)
In-Reply-To: <20211026125337.2r3yapa5uuimtc7o@leviathan>
Thanks, Leif.
Will fix all of them.
Best regards,
Nhi
On 26/10/2021 19:53, Leif Lindholm wrote:
> On Fri, Oct 22, 2021 at 13:17:54 +0700, Nhi Pham wrote:
>> From: Vu Nguyen <vunguyen@os.amperecomputing.com>
>>
>> Provides functions to handle the PCIe configuration requests. The target
>> Root Complex is selected based on the segment number parsed from the input
>> address.
>>
>> Cc: Thang Nguyen <thang@os.amperecomputing.com>
>> Cc: Chuong Tran <chuong@os.amperecomputing.com>
>> Cc: Phong Vo <phong@os.amperecomputing.com>
>> Cc: Leif Lindholm <leif@nuviainc.com>
>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
>> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
>>
>> Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
>> ---
>> Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc | 1 +
>> Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf | 32 +
>> Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c | 1573 ++++++++++++++++++++
>> 3 files changed, 1606 insertions(+)
>>
>> diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
>> index 3b576df24073..1dee436f97b4 100644
>> --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
>> +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc
>> @@ -226,6 +226,7 @@ [LibraryClasses.common.DXE_DRIVER]
>> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
>> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>> PciHostBridgeLib|Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> + PciSegmentLib|Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
>>
>> [LibraryClasses.common.UEFI_APPLICATION]
>> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCustomDecompressLib.inf
>> diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
>> new file mode 100644
>> index 000000000000..ca564997e609
>> --- /dev/null
>> +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLibPci.inf
>> @@ -0,0 +1,32 @@
>> +## @file
>> +#
>> +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
>> +#
>> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001B
>> + BASE_NAME = PciSegmentLibPci
>> + FILE_GUID = 0AF5E76D-D31E-492B-AE69-A7B441FF62D9
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = PciSegmentLib
>> +
>> +[Sources]
>> + PciSegmentLib.c
>> +
>> +[Packages]
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
>> +
>> +[LibraryClasses]
>> + BaseLib
>> + DebugLib
>> + HobLib
>> + IoLib
>> +
>> +[Guids]
>> + gRootComplexInfoHobGuid
>> diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
>> new file mode 100644
>> index 000000000000..854f50f953be
>> --- /dev/null
>> +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c
>> @@ -0,0 +1,1573 @@
>> +/** @file
>> +
>> + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
>> +
>> + SPDX-License-Identifier: BSD-2-Clause-Patent
>> +
>> +**/
>> +
>> +#include <PiDxe.h>
>> +
>> +#include <Guid/RootComplexInfoHob.h>
>> +#include <Library/BaseLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/HobLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PciSegmentLib.h>
>> +
>> +#include <Platform/Ac01.h>
>> +
>> +#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
>> +#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
>> +#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
>> +#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
>> +#define GET_REG_NUM(Address) ((Address) & 0xFFF)
>> +
>> +/**
>> + Assert the validity of a PCI Segment address.
>> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63.
>> +
>> + @param A The address to validate.
>> + @param M Additional bits to assert to be zero.
>> +
>> +**/
>> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
>> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
>> +
>> +/**
>> + Convert the PCI Segment library address to PCI library address.
>> +
>> + @param A The address to convert.
>> +**/
>> +#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN)(UINT32)A)
>> +
>> +/**
>> + Get the MCFG Base from input Address.
>> +**/
>> +UINTN
>> +GetMmcfgBase (
>> + IN UINTN Address
>> + )
>> +{
>> + AC01_ROOT_COMPLEX *RootComplexList;
>> + UINTN Idx;
>> + VOID *Hob;
>> +
>> + Hob = GetFirstGuidHob (&gRootComplexInfoHobGuid);
>> + if (Hob == NULL) {
>> + return 0;
>> + }
>> +
>> + RootComplexList = (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob);
>> +
>> + for (Idx = 0; Idx < AC01_PCIE_MAX_ROOT_COMPLEX; Idx++) {
>> + if (RootComplexList[Idx].Logical == GET_SEG_NUM (Address)) {
>> + return RootComplexList[Idx].MmcfgBase;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + Register a PCI device so PCI configuration registers may be accessed after
>> + SetVirtualAddressMap().
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Bus, Device, Function and
>> + Register.
>> +
>> + @retval RETURN_SUCCESS The PCI device was registered for runtime access.
>> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
>> + after ExitBootServices().
>> + @retval RETURN_UNSUPPORTED The resources required to access the PCI device
>> + at runtime could not be mapped.
>> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
>> + complete the registration.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +PciSegmentRegisterForRuntimeAccess (
>> + IN UINTN Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> + return RETURN_UNSUPPORTED;
>> +}
>> +
>> +/**
>> + Reads an 8-bit PCI configuration register.
>> +
>> + Reads and returns the 8-bit PCI configuration register specified by Address.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> +
>> + @return The 8-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentRead8 (
>> + IN UINT64 Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> +
>> + UINTN CfgBase;
>> + UINT8 Value;
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFF);
>> +
>> + UINT64 AlignedAddr = CfgBase & ~0x3;
>> + UINT32 Val32 = MmioRead32 (AlignedAddr);
>> + switch (CfgBase & 0x3) {
>> + case 3:
>> + Value = Val32 >> 24;
>> + break;
>> +
>> + case 2:
>> + Value = Val32 >> 16;
>> + break;
>> +
>> + case 1:
>> + Value = Val32 >> 8;
>> + break;
>> +
>> + case 0:
>> + default:
>> + Value = Val32;
>> + break;
>> + }
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG RD8: 0x%p value: 0x%02X (0x%08llX 0x%08X)\n",
>> + CfgBase,
>> + Value,
>> + AlignedAddr,
>> + Val32
>> + ));
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Writes an 8-bit PCI configuration register.
>> +
>> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
>> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentWrite8 (
>> + IN UINT64 Address,
>> + IN UINT8 Value
>> + )
>> +{
>> + UINT32 Val32;
>> + UINT64 AlignedAddr;
>> + UINTN CfgBase;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFF);
>> +
>> + AlignedAddr = CfgBase & ~0x3;
>> + Val32 = MmioRead32 (AlignedAddr);
>> +
>> + switch (CfgBase & 0x3) {
>> + case 0:
>> + Val32 &= ~0xFF;
>> + Val32 |= Value;
>> + break;
>> +
>> + case 1:
>> + Val32 &= ~0xFF00;
>> + Val32 |= (UINT32)Value << 8;
>> + break;
>> +
>> + case 2:
>> + Val32 &= ~0xFF0000;
>> + Val32 |= (UINT32)Value << 16;
>> + break;
>> +
>> + case 3:
>> + default:
>> + Val32 &= ~0xFF000000;
>> + Val32 |= (UINT32)Value << 24;
>> + break;
>> + }
>> + MmioWrite32 (AlignedAddr, Val32);
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG WR8: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
>> + CfgBase,
>> + Value,
>> + AlignedAddr,
>> + MmioRead32 ((UINT64)AlignedAddr)
>> + ));
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address,
>> + performs a bitwise OR between the read result and the value specified by OrData,
>> + and writes the result to the 8-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentOr8 (
>> + IN UINT64 Address,
>> + IN UINT8 OrData
>> + )
>> +{
>> + return PciSegmentWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + and writes the result to the 8-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentAnd8 (
>> + IN UINT64 Address,
>> + IN UINT8 AndData
>> + )
>> +{
>> + return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
>> + followed a bitwise OR with another 8-bit value.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
>> + and writes the result to the 8-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentAndThenOr8 (
>> + IN UINT64 Address,
>> + IN UINT8 AndData,
>> + IN UINT8 OrData
>> + )
>> +{
>> + return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));
>> +}
>> +
>> +/**
>> + Reads a bit field of a PCI configuration register.
>> +
>> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
>> + specified by the StartBit and the EndBit. The value of the bit field is
>> + returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 7, then ASSERT().
>> + If EndBit is greater than 7, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to read.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..7.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..7.
>> +
>> + @return The value of the bit field read from the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentBitFieldRead8 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit
>> + )
>> +{
>> + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
>> +}
>> +
>> +/**
>> + Writes a bit field to a PCI configuration register.
>> +
>> + Writes Value to the bit field of the PCI configuration register. The bit
>> + field is specified by the StartBit and the EndBit. All other bits in the
>> + destination PCI configuration register are preserved. The new value of the
>> + 8-bit register is returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 7, then ASSERT().
>> + If EndBit is greater than 7, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..7.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..7.
>> + @param Value New value of the bit field.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentBitFieldWrite8 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT8 Value
>> + )
>> +{
>> + return PciSegmentWrite8 (
>> + Address,
>> + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
>> + writes the result back to the bit field in the 8-bit port.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address, performs a
>> + bitwise OR between the read result and the value specified by
>> + OrData, and writes the result to the 8-bit PCI configuration register
>> + specified by Address. The value written to the PCI configuration register is
>> + returned. This function must guarantee that all PCI read and write operations
>> + are serialized. Extra left bits in OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 7, then ASSERT().
>> + If EndBit is greater than 7, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..7.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..7.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentBitFieldOr8 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT8 OrData
>> + )
>> +{
>> + return PciSegmentWrite8 (
>> + Address,
>> + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
>> + AND, and writes the result back to the bit field in the 8-bit register.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address, performs a
>> + bitwise AND between the read result and the value specified by AndData, and
>> + writes the result to the 8-bit PCI configuration register specified by
>> + Address. The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are
>> + serialized. Extra left bits in AndData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 7, then ASSERT().
>> + If EndBit is greater than 7, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..7.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..7.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentBitFieldAnd8 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT8 AndData
>> + )
>> +{
>> + return PciSegmentWrite8 (
>> + Address,
>> + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
>> + bitwise OR, and writes the result back to the bit field in the 8-bit port.
>> +
>> + Reads the 8-bit PCI configuration register specified by Address, performs a
>> + bitwise AND followed by a bitwise OR between the read result and
>> + the value specified by AndData, and writes the result to the 8-bit PCI
>> + configuration register specified by Address. The value written to the PCI
>> + configuration register is returned. This function must guarantee that all PCI
>> + read and write operations are serialized. Extra left bits in both AndData and
>> + OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 7, then ASSERT().
>> + If EndBit is greater than 7, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..7.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..7.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the result of the AND operation.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentBitFieldAndThenOr8 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT8 AndData,
>> + IN UINT8 OrData
>> + )
>> +{
>> + return PciSegmentWrite8 (
>> + Address,
>> + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a 16-bit PCI configuration register.
>> +
>> + Reads and returns the 16-bit PCI configuration register specified by Address.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> +
>> + @return The 16-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentRead16 (
>> + IN UINT64 Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> +
>> + UINTN CfgBase;
>> + UINT16 Value;
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFE);
>> + UINT64 AlignedAddr = CfgBase & ~0x3;
>> + UINT32 RegC, Reg18;
>> + UINT8 MfHt, Primary = 0, Sec = 0, Sub = 0;
> MfHt is not a proper CamelCase name.
>
>> + UINT32 Val32;
>> +
>> + if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
>> + Value = MmioRead32 (CfgBase);
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG16 RD: B%X|D%X 0x%p value: 0x%08X\n",
>> + GET_BUS_NUM (CfgBase),
>> + GET_DEV_NUM (CfgBase),
>> + CfgBase,
>> + Value
>> + ));
>> +
>> + if (Value != 0xffff) {
>> + RegC = MmioRead32 (CfgBase + 0xC);
>> + DEBUG ((DEBUG_INFO, " Peek PCIE MfHt RD: 0x%p value: 0x%08X\n", CfgBase + 0xc, RegC));
>> + MfHt = RegC >> 16;
>> + DEBUG ((DEBUG_INFO, " Peek RD8 MfHt=0x%02X\n", MfHt));
>> +
>> + if ((MfHt & 0x7F)!= 0) { /* Type 1 header */
>> + Reg18 = MmioRead32 (CfgBase + 0x18);
>> + Primary = Reg18; Sec = Reg18 >> 8; Sub = Reg18 >> 16;
>> + DEBUG ((
>> + DEBUG_INFO,
>> + " Bus Peek PCIE Sub:%01X Sec:%01X Primary:%01X RD: 0x%p value: 0x%08X\n",
>> + Sub,
>> + Sec,
>> + Primary,
>> + CfgBase + 0x18,
>> + Reg18
>> + ));
>> + }
>> +
>> + if ((MfHt == 0) || (Primary != 0)) { /* QS RPs Primary Bus is 0b */
>> + Value = 0xffff;
>> + DEBUG ((
>> + DEBUG_INFO,
>> + " Skip RD16 B%X|D%X PCIE CFG RD: 0x%p return 0xffff\n",
>> + GET_BUS_NUM (CfgBase),
>> + GET_DEV_NUM (CfgBase),
>> + CfgBase
>> + ));
>> + return 0;
>> + }
>> + }
>> + }
>> +
>> + Val32 = MmioRead32 (AlignedAddr);
>> + switch (CfgBase & 0x3) {
>> + case 2:
>> + Value = Val32 >> 16;
>> + break;
>> +
>> + case 0:
>> + default:
>> + Value = Val32;
>> + break;
>> + }
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG RD16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
>> + CfgBase,
>> + Value,
>> + AlignedAddr,
>> + Val32
>> + ));
>> +
>> + if (GET_REG_NUM (Address) == 0xAE && Value == 0xFFFF) {
>> + DEBUG ((DEBUG_ERROR, "PANIC due to PCIE link issue - Addr 0x%llx\n", Address));
>> + // Loop forever waiting for failsafe/watch dog time out
>> + CpuDeadLoop ();
>> + }
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Writes a 16-bit PCI configuration register.
>> +
>> + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
>> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The parameter of Value.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentWrite16 (
>> + IN UINT64 Address,
>> + IN UINT16 Value
>> + )
>> +{
>> + UINT32 Val32;
>> + UINT64 AlignedAddr;
>> + UINTN CfgBase;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFE);
>> +
>> + AlignedAddr = CfgBase & ~0x3;
>> + Val32 = MmioRead32 (AlignedAddr);
>> +
>> + switch (CfgBase & 0x3) {
>> + case 2:
>> + Val32 &= ~0xFFFF0000;
>> + Val32 |= (UINT32)Value << 16;
>> + break;
>> +
>> + case 0:
>> + default:
>> + Val32 &= ~0xFFFF;
>> + Val32 |= Value;
>> + break;
>> + }
>> + MmioWrite32 (AlignedAddr, Val32);
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG WR16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
>> + CfgBase,
>> + Value,
>> + AlignedAddr,
>> + MmioRead32 (AlignedAddr)
>> + ));
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Performs a bitwise OR of a 16-bit PCI configuration register with
>> + a 16-bit value.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address, performs a
>> + bitwise OR between the read result and the value specified by OrData, and
>> + writes the result to the 16-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned. This function
>> + must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function and
>> + Register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentOr16 (
>> + IN UINT64 Address,
>> + IN UINT16 OrData
>> + )
>> +{
>> + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + and writes the result to the 16-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentAnd16 (
>> + IN UINT64 Address,
>> + IN UINT16 AndData
>> + )
>> +{
>> + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
>> + followed a bitwise OR with another 16-bit value.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
>> + and writes the result to the 16-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentAndThenOr16 (
>> + IN UINT64 Address,
>> + IN UINT16 AndData,
>> + IN UINT16 OrData
>> + )
>> +{
>> + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
>> +}
>> +
>> +/**
>> + Reads a bit field of a PCI configuration register.
>> +
>> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
>> + specified by the StartBit and the EndBit. The value of the bit field is
>> + returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> + If StartBit is greater than 15, then ASSERT().
>> + If EndBit is greater than 15, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to read.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..15.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..15.
>> +
>> + @return The value of the bit field read from the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentBitFieldRead16 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit
>> + )
>> +{
>> + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
>> +}
>> +
>> +/**
>> + Writes a bit field to a PCI configuration register.
>> +
>> + Writes Value to the bit field of the PCI configuration register. The bit
>> + field is specified by the StartBit and the EndBit. All other bits in the
>> + destination PCI configuration register are preserved. The new value of the
>> + 16-bit register is returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> + If StartBit is greater than 15, then ASSERT().
>> + If EndBit is greater than 15, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..15.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..15.
>> + @param Value New value of the bit field.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentBitFieldWrite16 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT16 Value
>> + )
>> +{
>> + return PciSegmentWrite16 (
>> + Address,
>> + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
>> + the result back to the bit field in the 16-bit port.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address, performs a
>> + bitwise OR between the read result and the value specified by
>> + OrData, and writes the result to the 16-bit PCI configuration register
>> + specified by Address. The value written to the PCI configuration register is
>> + returned. This function must guarantee that all PCI read and write operations
>> + are serialized. Extra left bits in OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> + If StartBit is greater than 15, then ASSERT().
>> + If EndBit is greater than 15, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..15.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..15.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentBitFieldOr16 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT16 OrData
>> + )
>> +{
>> + return PciSegmentWrite16 (
>> + Address,
>> + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
>> + AND, writes the result back to the bit field in the 16-bit register.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address, performs a
>> + bitwise AND between the read result and the value specified by AndData, and
>> + writes the result to the 16-bit PCI configuration register specified by
>> + Address. The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are
>> + serialized. Extra left bits in AndData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> + If StartBit is greater than 15, then ASSERT().
>> + If EndBit is greater than 15, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..15.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..15.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentBitFieldAnd16 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT16 AndData
>> + )
>> +{
>> + return PciSegmentWrite16 (
>> + Address,
>> + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
>> + bitwise OR, and writes the result back to the bit field in the
>> + 16-bit port.
>> +
>> + Reads the 16-bit PCI configuration register specified by Address, performs a
>> + bitwise AND followed by a bitwise OR between the read result and
>> + the value specified by AndData, and writes the result to the 16-bit PCI
>> + configuration register specified by Address. The value written to the PCI
>> + configuration register is returned. This function must guarantee that all PCI
>> + read and write operations are serialized. Extra left bits in both AndData and
>> + OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 15, then ASSERT().
>> + If EndBit is greater than 15, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..15.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..15.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the result of the AND operation.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentBitFieldAndThenOr16 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT16 AndData,
>> + IN UINT16 OrData
>> + )
>> +{
>> + return PciSegmentWrite16 (
>> + Address,
>> + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a 32-bit PCI configuration register.
>> +
>> + Reads and returns the 32-bit PCI configuration register specified by Address.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> +
>> + @return The 32-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentRead32 (
>> + IN UINT64 Address
>> + )
>> +{
>> + UINT32 RegC, Reg18;
>> + UINT32 Value;
>> + UINT8 MfHt, Ht, Primary = 0, Sec = 0, Sub = 0;
> And neither is Ht.
>
> /
> Leif
>
>> + UINTN CfgBase;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFC);
>> +
>> + if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
>> + Value = MmioRead32 (CfgBase);
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG RD32: B%X|D%X 0x%p value: 0x%08X\n",
>> + GET_BUS_NUM (CfgBase),
>> + GET_DEV_NUM (CfgBase),
>> + CfgBase,
>> + Value
>> + ));
>> +
>> + if (Value != 0xffffffff) {
>> + RegC = MmioRead32 (CfgBase + 0xC);
>> + DEBUG ((DEBUG_INFO, "Peek PCIE MfHt RD32: 0x%p value: 0x%08X\n", CfgBase + 0xc, RegC));
>> + MfHt = RegC >> 16;
>> + DEBUG ((DEBUG_INFO, " Peek RD8 MfHt=0x%02X\n", MfHt));
>> +
>> + Ht = MfHt & 0x7F;
>> + if (Ht != 0) { /* Type 1 header */
>> + Reg18 = MmioRead32 (CfgBase + 0x18);
>> + Primary = Reg18; Sec = Reg18 >> 8; Sub = Reg18 >> 16;
>> + DEBUG ((
>> + DEBUG_INFO,
>> + " Bus Peek PCIE Sub:%01X Sec:%01X Primary:%01X RD32: 0x%p value: 0x%08X\n",
>> + Sub,
>> + Sec,
>> + Primary,
>> + CfgBase + 0x18,
>> + Reg18
>> + ));
>> + }
>> + if ((Ht == 0) || (Primary != 0)) { /* Ampere Altra RPs Primary Bus is 0b */
>> + Value = 0xffffffff;
>> + DEBUG ((
>> + DEBUG_INFO,
>> + " Skip RD32 B%X|D%X PCIE CFG RD32: 0x%p return 0xffffffff\n",
>> + GET_BUS_NUM (CfgBase),
>> + GET_DEV_NUM (CfgBase),
>> + CfgBase
>> + ));
>> + }
>> + }
>> + } else {
>> + Value = MmioRead32 (CfgBase);
>> + }
>> +
>> + DEBUG ((DEBUG_INFO, "PCIE CFG RD32: 0x%p value: 0x%08X\n", CfgBase, Value));
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Writes a 32-bit PCI configuration register.
>> +
>> + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
>> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The parameter of Value.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentWrite32 (
>> + IN UINT64 Address,
>> + IN UINT32 Value
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> +
>> + UINTN CfgBase;
>> +
>> + CfgBase = GetMmcfgBase (Address) + (Address & 0x0FFFFFFC);
>> + MmioWrite32 (CfgBase, Value);
>> + DEBUG ((
>> + DEBUG_INFO,
>> + "PCIE CFG WR32: 0x%p value: 0x%08X (0x%08X)\n",
>> + CfgBase,
>> + Value,
>> + MmioRead32 (CfgBase)
>> + ));
>> +
>> + return Value;
>> +}
>> +
>> +/**
>> + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
>> +
>> + Reads the 32-bit PCI configuration register specified by Address,
>> + performs a bitwise OR between the read result and the value specified by OrData,
>> + and writes the result to the 32-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentOr32 (
>> + IN UINT64 Address,
>> + IN UINT32 OrData
>> + )
>> +{
>> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
>> +
>> + Reads the 32-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + and writes the result to the 32-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentAnd32 (
>> + IN UINT64 Address,
>> + IN UINT32 AndData
>> + )
>> +{
>> + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
>> +}
>> +
>> +/**
>> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
>> + followed a bitwise OR with another 32-bit value.
>> +
>> + Reads the 32-bit PCI configuration register specified by Address,
>> + performs a bitwise AND between the read result and the value specified by AndData,
>> + performs a bitwise OR between the result of the AND operation and the value specified by OrData,
>> + and writes the result to the 32-bit PCI configuration register specified by Address.
>> + The value written to the PCI configuration register is returned.
>> + This function must guarantee that all PCI read and write operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentAndThenOr32 (
>> + IN UINT64 Address,
>> + IN UINT32 AndData,
>> + IN UINT32 OrData
>> + )
>> +{
>> + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
>> +}
>> +
>> +/**
>> + Reads a bit field of a PCI configuration register.
>> +
>> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
>> + specified by the StartBit and the EndBit. The value of the bit field is
>> + returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> + If StartBit is greater than 31, then ASSERT().
>> + If EndBit is greater than 31, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to read.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..31.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..31.
>> +
>> + @return The value of the bit field read from the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentBitFieldRead32 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit
>> + )
>> +{
>> + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
>> +}
>> +
>> +/**
>> + Writes a bit field to a PCI configuration register.
>> +
>> + Writes Value to the bit field of the PCI configuration register. The bit
>> + field is specified by the StartBit and the EndBit. All other bits in the
>> + destination PCI configuration register are preserved. The new value of the
>> + 32-bit register is returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> + If StartBit is greater than 31, then ASSERT().
>> + If EndBit is greater than 31, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..31.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..31.
>> + @param Value New value of the bit field.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentBitFieldWrite32 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT32 Value
>> + )
>> +{
>> + return PciSegmentWrite32 (
>> + Address,
>> + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
>> + writes the result back to the bit field in the 32-bit port.
>> +
>> + Reads the 32-bit PCI configuration register specified by Address, performs a
>> + bitwise OR between the read result and the value specified by
>> + OrData, and writes the result to the 32-bit PCI configuration register
>> + specified by Address. The value written to the PCI configuration register is
>> + returned. This function must guarantee that all PCI read and write operations
>> + are serialized. Extra left bits in OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 31, then ASSERT().
>> + If EndBit is greater than 31, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..31.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..31.
>> + @param OrData The value to OR with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentBitFieldOr32 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT32 OrData
>> + )
>> +{
>> + return PciSegmentWrite32 (
>> + Address,
>> + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
>> + AND, and writes the result back to the bit field in the 32-bit register.
>> +
>> +
>> + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
>> + AND between the read result and the value specified by AndData, and writes the result
>> + to the 32-bit PCI configuration register specified by Address. The value written to
>> + the PCI configuration register is returned. This function must guarantee that all PCI
>> + read and write operations are serialized. Extra left bits in AndData are stripped.
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> + If StartBit is greater than 31, then ASSERT().
>> + If EndBit is greater than 31, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..31.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..31.
>> + @param AndData The value to AND with the PCI configuration register.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentBitFieldAnd32 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT32 AndData
>> + )
>> +{
>> + return PciSegmentWrite32 (
>> + Address,
>> + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
>> + bitwise OR, and writes the result back to the bit field in the
>> + 32-bit port.
>> +
>> + Reads the 32-bit PCI configuration register specified by Address, performs a
>> + bitwise AND followed by a bitwise OR between the read result and
>> + the value specified by AndData, and writes the result to the 32-bit PCI
>> + configuration register specified by Address. The value written to the PCI
>> + configuration register is returned. This function must guarantee that all PCI
>> + read and write operations are serialized. Extra left bits in both AndData and
>> + OrData are stripped.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If StartBit is greater than 31, then ASSERT().
>> + If EndBit is greater than 31, then ASSERT().
>> + If EndBit is less than StartBit, then ASSERT().
>> + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
>> +
>> + @param Address PCI configuration register to write.
>> + @param StartBit The ordinal of the least significant bit in the bit field.
>> + Range 0..31.
>> + @param EndBit The ordinal of the most significant bit in the bit field.
>> + Range 0..31.
>> + @param AndData The value to AND with the PCI configuration register.
>> + @param OrData The value to OR with the result of the AND operation.
>> +
>> + @return The value written back to the PCI configuration register.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentBitFieldAndThenOr32 (
>> + IN UINT64 Address,
>> + IN UINTN StartBit,
>> + IN UINTN EndBit,
>> + IN UINT32 AndData,
>> + IN UINT32 OrData
>> + )
>> +{
>> + return PciSegmentWrite32 (
>> + Address,
>> + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
>> + );
>> +}
>> +
>> +/**
>> + Reads a range of PCI configuration registers into a caller supplied buffer.
>> +
>> + Reads the range of PCI configuration registers specified by StartAddress and
>> + Size into the buffer specified by Buffer. This function only allows the PCI
>> + configuration registers from a single PCI function to be read. Size is
>> + returned. When possible 32-bit PCI configuration read cycles are used to read
>> + from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
>> + and 16-bit PCI configuration read cycles may be used at the beginning and the
>> + end of the range.
>> +
>> + If any reserved bits in StartAddress are set, then ASSERT().
>> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> + If Size > 0 and Buffer is NULL, then ASSERT().
>> +
>> + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
>> + Function and Register.
>> + @param Size Size in bytes of the transfer.
>> + @param Buffer Pointer to a buffer receiving the data read.
>> +
>> + @return Size
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +PciSegmentReadBuffer (
>> + IN UINT64 StartAddress,
>> + IN UINTN Size,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + UINTN ReturnValue;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
>> + ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
>> +
>> + if (Size == 0) {
>> + return Size;
>> + }
>> +
>> + ASSERT (Buffer != NULL);
>> +
>> + //
>> + // Save Size for return
>> + //
>> + ReturnValue = Size;
>> +
>> + if ((StartAddress & BIT0) != 0) {
>> + //
>> + // Read a byte if StartAddress is byte aligned
>> + //
>> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>> + StartAddress += sizeof (UINT8);
>> + Size -= sizeof (UINT8);
>> + Buffer = (UINT8 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> + //
>> + // Read a word if StartAddress is word aligned
>> + //
>> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16 *)Buffer + 1;
>> + }
>> +
>> + while (Size >= sizeof (UINT32)) {
>> + //
>> + // Read as many double words as possible
>> + //
>> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
>> + StartAddress += sizeof (UINT32);
>> + Size -= sizeof (UINT32);
>> + Buffer = (UINT32 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT16)) {
>> + //
>> + // Read the last remaining word if exist
>> + //
>> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT8)) {
>> + //
>> + // Read the last remaining byte if exist
>> + //
>> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>> + }
>> +
>> + return ReturnValue;
>> +}
>> +
>> +/**
>> + Copies the data in a caller supplied buffer to a specified range of PCI
>> + configuration space.
>> +
>> + Writes the range of PCI configuration registers specified by StartAddress and
>> + Size from the buffer specified by Buffer. This function only allows the PCI
>> + configuration registers from a single PCI function to be written. Size is
>> + returned. When possible 32-bit PCI configuration write cycles are used to
>> + write from StartAddress to StartAddress + Size. Due to alignment restrictions,
>> + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
>> + and the end of the range.
>> +
>> + If any reserved bits in StartAddress are set, then ASSERT().
>> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> + If Size > 0 and Buffer is NULL, then ASSERT().
>> +
>> + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
>> + Function and Register.
>> + @param Size Size in bytes of the transfer.
>> + @param Buffer Pointer to a buffer containing the data to write.
>> +
>> + @return The parameter of Size.
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +PciSegmentWriteBuffer (
>> + IN UINT64 StartAddress,
>> + IN UINTN Size,
>> + IN VOID *Buffer
>> + )
>> +{
>> + UINTN ReturnValue;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
>> + ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
>> +
>> + if (Size == 0) {
>> + return Size;
>> + }
>> +
>> + ASSERT (Buffer != NULL);
>> +
>> + //
>> + // Save Size for return
>> + //
>> + ReturnValue = Size;
>> +
>> + if ((StartAddress & BIT0) != 0) {
>> + //
>> + // Write a byte if StartAddress is byte aligned
>> + //
>> + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
>> + StartAddress += sizeof (UINT8);
>> + Size -= sizeof (UINT8);
>> + Buffer = (UINT8 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> + //
>> + // Write a word if StartAddress is word aligned
>> + //
>> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16 *)Buffer + 1;
>> + }
>> +
>> + while (Size >= sizeof (UINT32)) {
>> + //
>> + // Write as many double words as possible
>> + //
>> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
>> + StartAddress += sizeof (UINT32);
>> + Size -= sizeof (UINT32);
>> + Buffer = (UINT32 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT16)) {
>> + //
>> + // Write the last remaining word if exist
>> + //
>> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16 *)Buffer + 1;
>> + }
>> +
>> + if (Size >= sizeof (UINT8)) {
>> + //
>> + // Write the last remaining byte if exist
>> + //
>> + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
>> + }
>> +
>> + return ReturnValue;
>> +}
>> --
>> 2.17.1
>>
next prev parent reply other threads:[~2021-11-03 9:40 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 6:17 [edk2-platforms][PATCH v4 00/31] Add new Ampere Mt. Jade platform Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 01/31] Ampere: Initial support for Ampere Altra processor and " Nhi Pham
2021-10-26 11:14 ` Leif Lindholm
2021-11-03 9:31 ` Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 02/31] AmpereAltraPkg: Add FlashLib library instance Nhi Pham
2021-10-26 11:25 ` Leif Lindholm
2021-11-03 9:32 ` Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 03/31] AmpereAltraPkg: Add FailSafe and WDT support Nhi Pham
2021-10-26 12:15 ` Leif Lindholm
2021-11-03 9:35 ` Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 04/31] AmpereAltraPkg: Add DwI2cLib library instance Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 05/31] AmpereAltraPkg: Add DwGpioLib " Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 06/31] JadePkg: Implement RealTimeClockLib for PCF85063 Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 07/31] AmpereAltraPkg: Add BootProgress support Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 08/31] AmpereAltraPkg: Support UEFI non-volatile variable Nhi Pham
2021-10-26 12:21 ` Leif Lindholm
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 09/31] AmpereSiliconPkg: Add PlatformManagerUiLib library instance Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 10/31] AmpereAltraPkg, JadePkg: Add ACPI support Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 11/31] AmpereAltraPkg: Add Root Complex HOB data structures Nhi Pham
2021-10-26 12:23 ` Leif Lindholm
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 12/31] AmpereAltraPkg: Add Ac01PcieLib library instance Nhi Pham
2021-10-26 12:45 ` Leif Lindholm
2021-11-03 9:33 ` Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 13/31] JadePkg: Add BoardPcieLib " Nhi Pham
2021-10-26 12:46 ` Leif Lindholm
2021-11-03 9:33 ` Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 14/31] AmpereAltraPkg: Add driver to initialize PCIe Root Complex Nhi Pham
2021-10-26 12:49 ` Leif Lindholm
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 15/31] AmpereAltraPkg: Add PciHostBridgeLib library instance Nhi Pham
2021-10-26 12:49 ` Leif Lindholm
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 16/31] AmpereAltraPkg: Add PciSegmentLib " Nhi Pham
2021-10-26 12:53 ` Leif Lindholm
2021-11-03 9:35 ` Nhi Pham [this message]
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 17/31] JadePkg: Enable PciHostBridgeDxe driver Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 18/31] JadePkg: Add PciPlatformDxe driver Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 19/31] JadePkg: Add ACPI tables to support PCIe Nhi Pham
2021-10-26 12:54 ` Leif Lindholm
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 20/31] JadePkg: Add ASpeed GOP driver Nhi Pham
2021-10-22 6:17 ` [edk2-platforms][PATCH v4 21/31] AmpereAltraPkg: Add Random Number Generator Support Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 22/31] JadePkg: Add SMBIOS tables support Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 23/31] AmpereAltraPkg: Add DebugInfoPei module Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 24/31] AmpereAltraPkg: Add configuration screen for PCIe Nhi Pham
2021-10-26 12:56 ` Leif Lindholm
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 25/31] Ampere: Utilize the PCIe User setting Nhi Pham
2021-10-26 12:57 ` Leif Lindholm
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 26/31] AmpereAltraPkg: Add platform info screen Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 27/31] AmpereAltraPkg: Add configuration screen for Memory Nhi Pham
2021-10-26 12:58 ` Leif Lindholm
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 28/31] AmpereAltraPkg: Add configuration screen for CPU Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 29/31] AmpereAltraPkg: Add configuration screen for ACPI Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 30/31] AmpereAltraPkg: Add configuration screen for RAS Nhi Pham
2021-10-22 6:18 ` [edk2-platforms][PATCH v4 31/31] AmpereAltraPkg: Add configuration screen for Watchdog timer Nhi Pham
2021-10-26 13:03 ` Leif Lindholm
2021-11-03 9:36 ` Nhi Pham
2021-10-26 13:08 ` [edk2-platforms][PATCH v4 00/31] Add new Ampere Mt. Jade platform Leif Lindholm
2021-11-03 9:37 ` Nhi Pham
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