From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B1EF2AC1198 for ; Tue, 6 Feb 2024 13:33:44 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=poyx31X5ypYjoL/6Mm3tcTZSumuiTFaha3dRoeqjH7o=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1707226423; v=1; b=JNo3IWIDqC9yA0XppxdVeHNz3uNehZldIIjEDEz1k3ZSvz0+GW3qyiGxV9Lc5BmiuGBa0b0J EeRYD8sLnxbE4E6XdnY6gKIOsmwEcEqQy78vWbxYlY8w3X1UY0EKOHEqIn7GIFyo2hCr9gu8CPg W/2eVleMnXiOIVSn0suM7zdk= X-Received: by 127.0.0.2 with SMTP id qqsgYY7687511xe7XuTjyM2u; Tue, 06 Feb 2024 05:33:43 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web11.21389.1707226422724633961 for ; Tue, 06 Feb 2024 05:33:42 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-173-nY9ll90GPSGEB14HTpLEVA-1; Tue, 06 Feb 2024 08:33:38 -0500 X-MC-Unique: nY9ll90GPSGEB14HTpLEVA-1 X-Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 821F285A596; Tue, 6 Feb 2024 13:33:38 +0000 (UTC) X-Received: from [10.39.195.129] (unknown [10.39.195.129]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9744B1C060AF; Tue, 6 Feb 2024 13:33:37 +0000 (UTC) Message-ID: Date: Tue, 6 Feb 2024 14:33:36 +0100 MIME-Version: 1.0 Subject: Re: [edk2-devel] [PATCH 3/3] UefiCpuPkg/PiSmmCpuDxeSmm:Map SMRAM in 4K page granularity To: Dun Tan , devel@edk2.groups.io Cc: Ray Ni , Rahul Kumar , Gerd Hoffmann References: <20240205140345.1437-1-dun.tan@intel.com> <20240205140345.1437-4-dun.tan@intel.com> From: "Laszlo Ersek" In-Reply-To: <20240205140345.1437-4-dun.tan@intel.com> X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 8jncx6IUsYqwAKRezceXUlcyx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=JNo3IWID; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On 2/5/24 15:03, Dun Tan wrote: > This patch is to map SMRAM in 4K page granularity > during SMM page table initialization(SmmInitPageTable) > so as to avoid the SMRAM paging-structure layout > change when SMI happens (PerformRemainingTasks). > The reason is to avoid the Paging-Structure change > impact to the multiple Processors. Refer SDM section > "4.10.4" & "4.10.5". >=20 > Currently, SMM BSP needs to update the SMRAM range > paging attribute in smm page table according to the > SmmMemoryAttributesTable when SMM ready to lock > happens. If the SMRAM range is not 4k mapped in page > table, the page table update process may split 1G/2M > paging entries to 4k ones.Meanwhile, all APs are still > running in SMI, which might access the affected > linear-address range between the time of modification > and the time of invalidation access. That will be > a potential problem leading exception happens. Is this originally a bug from commit 717fb60443fb ("UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.", 2016-11-17)? Laszlo >=20 > Signed-off-by: Dun Tan > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Rahul Kumar > Cc: Gerd Hoffmann > --- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 116 +++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++------------------------ > 1 file changed, 92 insertions(+), 24 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpu= Pkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index 12f3c0b8e8..0012d63674 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -1647,49 +1647,115 @@ EdkiiSmmClearMemoryAttributes ( > } > =20 > /** > - Create page table based on input PagingMode and PhysicalAddressBits in= smm. > - > - @param[in] PagingMode The paging mode. > - @param[in] PhysicalAddressBits The bits of physical address to m= ap. > + Create page table based on input PagingMode, LinearAddress and Length. > =20 > - @retval PageTable Address > + @param[in, out] PageTable The pointer to the page table. > + @param[in] PagingMode The paging mode. > + @param[in] LinearAddress The start of the linear address r= ange. > + @param[in] Length The length of the linear address = range. > =20 > **/ > -UINTN > -GenSmmPageTable ( > - IN PAGING_MODE PagingMode, > - IN UINT8 PhysicalAddressBits > +VOID > +GenPageTable ( > + IN OUT UINTN *PageTable, > + IN PAGING_MODE PagingMode, > + IN UINT64 LinearAddress, > + IN UINT64 Length > ) > { > + RETURN_STATUS Status; > UINTN PageTableBufferSize; > - UINTN PageTable; > VOID *PageTableBuffer; > IA32_MAP_ATTRIBUTE MapAttribute; > IA32_MAP_ATTRIBUTE MapMask; > - RETURN_STATUS Status; > - UINTN GuardPage; > - UINTN Index; > - UINT64 Length; > =20 > - Length =3D LShiftU64 (1, PhysicalAddressBits= ); > - PageTable =3D 0; > - PageTableBufferSize =3D 0; > MapMask.Uint64 =3D MAX_UINT64; > - MapAttribute.Uint64 =3D mAddressEncMask; > + MapAttribute.Uint64 =3D mAddressEncMask|LinearAddress; > MapAttribute.Bits.Present =3D 1; > MapAttribute.Bits.ReadWrite =3D 1; > MapAttribute.Bits.UserSupervisor =3D 1; > MapAttribute.Bits.Accessed =3D 1; > MapAttribute.Bits.Dirty =3D 1; > + PageTableBufferSize =3D 0; > + > + Status =3D PageTableMap ( > + PageTable, > + PagingMode, > + NULL, > + &PageTableBufferSize, > + LinearAddress, > + Length, > + &MapAttribute, > + &MapMask, > + NULL > + ); > + if (Status =3D=3D RETURN_BUFFER_TOO_SMALL) { > + DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial = SMM page table\n", PageTableBufferSize)); > + PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (Page= TableBufferSize)); > + ASSERT (PageTableBuffer !=3D NULL); > + Status =3D PageTableMap ( > + PageTable, > + PagingMode, > + PageTableBuffer, > + &PageTableBufferSize, > + LinearAddress, > + Length, > + &MapAttribute, > + &MapMask, > + NULL > + ); > + } > =20 > - Status =3D PageTableMap (&PageTable, PagingMode, NULL, &PageTableBuffe= rSize, 0, Length, &MapAttribute, &MapMask, NULL); > - ASSERT (Status =3D=3D RETURN_BUFFER_TOO_SMALL); > - DEBUG ((DEBUG_INFO, "GenSMMPageTable: 0x%x bytes needed for initial SM= M page table\n", PageTableBufferSize)); > - PageTableBuffer =3D AllocatePageTableMemory (EFI_SIZE_TO_PAGES (PageTa= bleBufferSize)); > - ASSERT (PageTableBuffer !=3D NULL); > - Status =3D PageTableMap (&PageTable, PagingMode, PageTableBuffer, &Pag= eTableBufferSize, 0, Length, &MapAttribute, &MapMask, NULL); > ASSERT (Status =3D=3D RETURN_SUCCESS); > ASSERT (PageTableBufferSize =3D=3D 0); > +} > + > +/** > + Create page table based on input PagingMode and PhysicalAddressBits in= smm. > + > + @param[in] PagingMode The paging mode. > + @param[in] PhysicalAddressBits The bits of physical address to m= ap. > + > + @retval PageTable Address > + > +**/ > +UINTN > +GenSmmPageTable ( > + IN PAGING_MODE PagingMode, > + IN UINT8 PhysicalAddressBits > + ) > +{ > + UINTN PageTable; > + RETURN_STATUS Status; > + UINTN GuardPage; > + UINTN Index; > + UINT64 Length; > + PAGING_MODE SmramPagingMode; > + > + PageTable =3D 0; > + Length =3D LShiftU64 (1, PhysicalAddressBits); > + ASSERT (Length > mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize); > + > + if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { > + SmramPagingMode =3D m5LevelPagingNeeded ? Paging5Level4KB : Paging4L= evel4KB; > + } else { > + SmramPagingMode =3D PagingPae4KB; > + } > + > + GenPageTable (&PageTable, PagingMode, 0, mCpuHotPlugData.SmrrBase); > + > + // > + // Map smram range in 4K page granularity to avoid subsequent page spl= it when smm ready to lock. > + // If BSP are splitting the 1G/2M paging entries to 512 2M/4K paging e= ntries, and all APs are > + // still running in SMI at the same time, which might access the affec= ted linear-address range > + // between the time of modification and the time of invalidation acces= s. That will be a potential > + // problem leading exception happen. > + // > + ASSERT (mCpuHotPlugData.SmrrBase % SIZE_4KB =3D=3D 0); > + ASSERT (mCpuHotPlugData.SmrrSize % SIZE_4KB =3D=3D 0); > + GenPageTable (&PageTable, SmramPagingMode, mCpuHotPlugData.SmrrBase, m= CpuHotPlugData.SmrrSize); > + > + GenPageTable (&PageTable, PagingMode, mCpuHotPlugData.SmrrBase + mCpuH= otPlugData.SmrrSize, Length - mCpuHotPlugData.SmrrBase - mCpuHotPlugData.Sm= rrSize); > =20 > if (FeaturePcdGet (PcdCpuSmmStackGuard)) { > // > @@ -1698,6 +1764,7 @@ GenSmmPageTable ( > for (Index =3D 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.Number= OfCpus; Index++) { > GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE + Index * (mSmmSt= ackSize + mSmmShadowStackSize); > Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, = GuardPage, SIZE_4KB, EFI_MEMORY_RP, TRUE, NULL); > + ASSERT (Status =3D=3D RETURN_SUCCESS); > } > } > =20 > @@ -1706,6 +1773,7 @@ GenSmmPageTable ( > // Mark [0, 4k] as non-present > // > Status =3D ConvertMemoryPageAttributes (PageTable, PagingMode, 0, SI= ZE_4KB, EFI_MEMORY_RP, TRUE, NULL); > + ASSERT (Status =3D=3D RETURN_SUCCESS); > } > =20 > return (UINTN)PageTable; -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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