From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web08.7926.1646141385262100108 for ; Tue, 01 Mar 2022 05:29:49 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=jwk+m9cB; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: sebastien.boeuf@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646141389; x=1677677389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QRcczaVQ1OVSKWW8KyVtQ7sTUOQZ/mh3YOSCxEwoYXY=; b=jwk+m9cBiMmbqCaDySCnAUAAvh9QsPYKbi/YFbXTAGFqZWeOY99BeTO6 T9sZXhrrcBx8Q0roDR+qrcBqGSoqFE7R0GZ/EePXgNR6AQrivW8BGMWw4 3h4iqJ6qmQRvlzKPqgfkglA3kzhaiVMuAa6nzNIxWRgTx3fcj/ktxomI0 RGjca5Xv/Wws4mwNMy9ZxOvFcngkwOYc+MFb0mbb9lapjiM4ZQU2x1qF1 H0VG9g119o/wDhmZVjo0yZE7nhZx50w5EVHo8VvTrRALrLDrVgHdKcSXa ITls3WNJyz6q6+myg6ylMWbxrZZCDXDdy+o06XFFczDb0tIsZsLvHvvM0 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="233099391" X-IronPort-AV: E=Sophos;i="5.90,146,1643702400"; d="scan'208";a="233099391" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 05:29:48 -0800 X-IronPort-AV: E=Sophos;i="5.90,146,1643702400"; d="scan'208";a="550711846" Received: from jashipm-mobl.amr.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.27.150]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 05:29:47 -0800 From: "Boeuf, Sebastien" To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH v5 4/7] OvmfPkg: Generate CloudHv as a PVH ELF binary Date: Tue, 1 Mar 2022 14:29:14 +0100 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sebastien Boeuf Following the model from the Xen target, CloudHv is generated as a PVH ELF binary to take advantage of the PVH specification, which requires less emulation from the VMM. The fdf include file CloudHvElfHeader.fdf.inc has been generated from the following commands: $ gcc -D PVH64 -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c $ ./elf_gen 4194304 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc Signed-off-by: Sebastien Boeuf --- OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc | 54 ++++++++++++++++++++++++ OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 37 ++++------------ OvmfPkg/VarStore.fdf.inc | 1 + 4 files changed, 64 insertions(+), 30 deletions(-) create mode 100644 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc diff --git a/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc b/OvmfPkg/CloudHv/Clo= udHvElfHeader.fdf.inc new file mode 100644 index 0000000000..8377e30bdc --- /dev/null +++ b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc @@ -0,0 +1,54 @@ +## @file +# FDF include file that defines a PVH ELF header. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DATA =3D { + # ELF file header + 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, + 0xd0, 0xff, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, # hdr.e_entry + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x0= 2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + # ELF Program segment headers + # - Load segment + 0x01, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + # - ELFNOTE segment + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + # XEN_ELFNOTE_PHYS32_ENTRY + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, + 0x58, 0x65, 0x6e, 0x00, + 0xd0, 0xff, 0x4f, 0x00 +} diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 3172100310..b4d855d80f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -631,7 +631,7 @@ # ##########################################################################= ###### [Components] - OvmfPkg/ResetVector/ResetVector.inf + OvmfPkg/XenResetVector/XenResetVector.inf = # # SEC Phase modules diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf index ce3302c6d6..282bcf8634 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -14,8 +14,8 @@ !include OvmfPkg/OvmfPkgDefines.fdf.inc = # -# Build the variable store and the firmware code as one unified flash devi= ce -# image. +# This will allow the flash device image to be recognize as an ELF, with f= irst +# an ELF headers, then the firmware code. # [FD.CLOUDHV] BaseAddress =3D $(FW_BASE_ADDRESS) @@ -24,38 +24,17 @@ ErasePolarity =3D 1 BlockSize =3D $(BLOCK_SIZE) NumBlocks =3D $(FW_BLOCKS) = -!include OvmfPkg/VarStore.fdf.inc - -$(VARS_SIZE)|$(FVMAIN_SIZE) -FV =3D FVMAIN_COMPACT - -$(SECFV_OFFSET)|$(SECFV_SIZE) -FV =3D SECFV - # -# Build the variable store and the firmware code as separate flash device -# images. +# Leaving 4kiB for the PVH ELF header. This is more than enough. # -[FD.CLOUDHV_VARS] -BaseAddress =3D $(FW_BASE_ADDRESS) -Size =3D $(VARS_SIZE) -ErasePolarity =3D 1 -BlockSize =3D $(BLOCK_SIZE) -NumBlocks =3D $(VARS_BLOCKS) - -!include OvmfPkg/VarStore.fdf.inc +0x00000000|0x00001000 = -[FD.CLOUDHV_CODE] -BaseAddress =3D $(CODE_BASE_ADDRESS) -Size =3D $(CODE_SIZE) -ErasePolarity =3D 1 -BlockSize =3D $(BLOCK_SIZE) -NumBlocks =3D $(CODE_BLOCKS) +!include CloudHvElfHeader.fdf.inc = -0x00000000|$(FVMAIN_SIZE) +0x00001000|$(FVMAIN_SIZE) FV =3D FVMAIN_COMPACT = -$(FVMAIN_SIZE)|$(SECFV_SIZE) +$(SECFV_OFFSET)|$(SECFV_SIZE) FV =3D SECFV = ##########################################################################= ###### @@ -142,7 +121,7 @@ READ_LOCK_STATUS =3D TRUE # INF OvmfPkg/Sec/SecMain.inf = -INF RuleOverride=3DRESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf +INF RuleOverride=3DRESET_VECTOR OvmfPkg/XenResetVector/XenResetVector.inf = ##########################################################################= ###### [FV.PEIFV] diff --git a/OvmfPkg/VarStore.fdf.inc b/OvmfPkg/VarStore.fdf.inc index a1e524e393..a1cbc74fbb 100644 --- a/OvmfPkg/VarStore.fdf.inc +++ b/OvmfPkg/VarStore.fdf.inc @@ -15,6 +15,7 @@ 0x00000000|0x00040000 !endif #NV_VARIABLE_STORE + DATA =3D { ## This is the EFI_FIRMWARE_VOLUME_HEADER # ZeroVector [] -- = 2.32.0 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, = 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. 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