From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BAAE7210FCF40 for ; Thu, 23 Aug 2018 00:40:23 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id m4-v6so1634582pgv.12 for ; Thu, 23 Aug 2018 00:40:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=QEIwWYw6/xaNcSIkXBfmwthYvRRasvlnHyO0x3x7rgo=; b=j/Q/aUHoXTTwvl+G5UcRAKzxjOjGJvYXnKaEX0BbUfb9NtX/TY4NmiiCZ5zKFcK9Bw JmG7CTq04Eo6L4o7q2ohNtKZEFQMyrkR2mLGmM4ugC2C+SWKJEV8oFI6dmLfpGkAQ1F0 6u6IsitHrl7zRNumXFYeqJdSCYhL6UdH+kdPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=QEIwWYw6/xaNcSIkXBfmwthYvRRasvlnHyO0x3x7rgo=; b=KW24FHnGF5/vku20qrinj/JPy5jT3lSkaIRVwBKlPA0M8AtQqlTw9ktBZsAbkt3YZ1 PeBpIWOayVzusGd6Dkl+LjvPOHwI+NNx/LpzG+z8T6H6kYnqM+jWbqpwaAzG+zK9e8wU nfjMtfZNf1CObjlc1vbzNUXa49sPDzfLGulbX0YLNa9+q6xEFHz4lFSehVxmWOP0f2u/ BTV/ENw18Ce79S4FfmWZQsQcApOI99BMyLSFSbcp/xDDNyWT6RoKCR/vB8jLwsKma2c5 EUlLGJVG2etpgkzQWyoBlLQoU9HV582JIxLiCu7xDV8edLYkvCJ5aGU60l4BtQ3HRkbw Oo4A== X-Gm-Message-State: AOUpUlHsZ3wiFEpnyOXxtscjRy4FwTf5u7XUd678QAJrRo2hgC7+ydyt lrf4ZOKHLigZqnT2xuDpDmDNvQ== X-Google-Smtp-Source: AA+uWPyrzFf5JWk+Wh0cFzQWWNVr9tZh3t0epVNg3bRMGSjAwi772RW1hZz5m010cxp5jWqiYetlhQ== X-Received: by 2002:a65:478b:: with SMTP id e11-v6mr10871234pgs.98.1535010023345; Thu, 23 Aug 2018 00:40:23 -0700 (PDT) Received: from [10.84.0.214] ([64.64.108.140]) by smtp.gmail.com with ESMTPSA id d19-v6sm5100484pgi.50.2018.08.23.00.40.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Aug 2018 00:40:22 -0700 (PDT) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org References: <20180814080903.50466-1-ming.huang@linaro.org> <20180814080903.50466-36-ming.huang@linaro.org> <20180822153336.mllu5y6fr72surxn@bivouac.eciton.net> From: Ming Message-ID: Date: Thu, 23 Aug 2018 15:39:57 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20180822153336.mllu5y6fr72surxn@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v2 35/43] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2018 07:40:23 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 8/22/2018 11:33 PM, Leif Lindholm wrote: > On Tue, Aug 14, 2018 at 04:08:55PM +0800, Ming Huang wrote: >> Add some Lpc macro to LpcLib.h for D06. >> > > Unaddressed feedback from v1: > > I have no issue with this patch, but can you explain when these macros > are intended to be used? And if in this set, move this patch > immediately before the patch than needs it? These macros are not used in edk2-platforms, used in HwPkg/LpcLib. > > Again, this patch is not D06 specific, and the subject should reflect that. > > / > Leif > >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- >> 1 file changed, 49 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h >> index 236a52ba45..5cf08ccde1 100755 >> --- a/Silicon/Hisilicon/Include/Library/LpcLib.h >> +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h >> @@ -1,7 +1,7 @@ >> /** @file >> * >> -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. >> -* Copyright (c) 2016, Linaro Limited. All rights reserved. >> +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. >> +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. >> * >> * This program and the accompanying materials >> * are licensed and made available under the terms and conditions of the BSD License >> @@ -18,6 +18,53 @@ >> >> #include >> >> +#define PCIE_SUBSYS_IOMUX 0x201100000 >> +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) >> +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) >> +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) >> +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) >> +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) >> +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) >> +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) >> +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) >> + >> +#define IO_MGMT_SUBCTRL_BASE 0x201070000 >> +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) >> +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) >> +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) >> + >> + >> +#define LPCD06_BASE 0x201190000 >> +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) >> +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) >> +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) >> +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) >> +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) >> +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) >> +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) >> +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) >> +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) >> +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) >> +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) >> +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) >> +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) >> +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) >> +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) >> + >> +#define LPCD06_START_REG (LPCD06_BASE + 0x00) >> +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) >> +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) >> +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) >> +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) >> +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) >> +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) >> +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) >> + >> +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) >> +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) >> +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) >> + >> + >> #define PCIE_SUBSYS_IO_MUX 0xA0170000 >> #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) >> #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) >> -- >> 2.17.0 >>