From: "Ard Biesheuvel" <ard.biesheuvel@arm.com>
To: Sami Mujawar <sami.mujawar@arm.com>, devel@edk2.groups.io
Cc: leif@nuviainc.com, michael.d.kinney@intel.com,
liming.gao@intel.com, Alexandru.Elisei@arm.com,
Andre.Przywara@arm.com, Matteo.Carlini@arm.com,
Laura.Moretta@arm.com, nd@arm.com
Subject: Re: [PATCH v1 02/11] MdePkg: Add NULL implementation for PCILib
Date: Thu, 14 May 2020 11:23:57 +0200 [thread overview]
Message-ID: <c66cde6e-cf87-ce9e-136e-13e7bcf456c3@arm.com> (raw)
In-Reply-To: <20200514084019.71368-3-sami.mujawar@arm.com>
On 5/14/20 10:40 AM, Sami Mujawar wrote:
> On some platforms the Serial 16550 UART is interfaced
> over PCI. To support such platforms the Serial 16550
> driver links with PciLib.
>
> For platforms that do not interface the Serial 16550
> UART over PCI, the driver still needs to link with a
> PciLib library. Linking to the full implementation of
> the PCI library may not be possible during the early
> firmware boot stage.
>
> To facilitate early firmware logs over the serial port
> this patch introduces a NULL PCI library implementation.
>
> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
> ---
> MdePkg/Library/PciLibNull/PciLibNull.c | 1213 ++++++++++++++++++++
> MdePkg/Library/PciLibNull/PciLibNull.inf | 25 +
> 2 files changed, 1238 insertions(+)
>
> diff --git a/MdePkg/Library/PciLibNull/PciLibNull.c b/MdePkg/Library/PciLibNull/PciLibNull.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..c186ca9f86e5a0c860472b80209aae9b958a95d7
> --- /dev/null
> +++ b/MdePkg/Library/PciLibNull/PciLibNull.c
> @@ -0,0 +1,1213 @@
> +/** @file
> + Provides a NULL implementation of PCI services used to access
> + PCI Configuration Space.
> +
> + Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + Registers a PCI device so PCI configuration registers may be accessed after
> + SetVirtualAddressMap().
> +
> + Registers the PCI device specified by Address so all the PCI configuration
> + registers associated with that PCI device may be accessed after
> + SetVirtualAddressMap() is called.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @retval RETURN_SUCCESS The PCI device was registered for runtime
> + access.
> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
> + after ExitBootServices().
> + @retval RETURN_UNSUPPORTED The resources required to access the PCI
> + device at runtime could not be mapped.
> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> + complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciRegisterForRuntimeAccess (
> + IN UINTN Address
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return The read value from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciRead8 (
> + IN UINTN Address
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned. This function must guarantee
> + that all PCI read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise OR of an 8-bit PCI configuration register with
> + an 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciOr8 (
> + IN UINTN Address,
> + IN UINT8 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> + value.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciAnd8 (
> + IN UINTN Address,
> + IN UINT8 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
> + value, followed by a bitwise OR with another 8-bit value.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and
> + the value specified by OrData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciAndThenOr8 (
> + IN UINTN Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in an 8-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciBitFieldRead8 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 8-bit register is returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciBitFieldWrite8 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 8-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciBitFieldOr8 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 8-bit register.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 8-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciBitFieldAnd8 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 8-bit port.
> +
> + Reads the 8-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 8-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If StartBit is greater than 7, then ASSERT().
> + If EndBit is greater than 7, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..7.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..7.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciBitFieldAndThenOr8 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return The read value from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciRead16 (
> + IN UINTN Address
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned. This function must guarantee
> + that all PCI read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise OR of a 16-bit PCI configuration register with
> + a 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> + value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 16-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
> + value, followed a bitwise OR with another 16-bit value.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and
> + the value specified by OrData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 16-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciBitFieldRead16 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 16-bit register is returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciBitFieldWrite16 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 16-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciBitFieldOr16 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 16-bit register.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 16-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciBitFieldAnd16 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 16-bit port.
> +
> + Reads the 16-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 16-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> + If StartBit is greater than 15, then ASSERT().
> + If EndBit is greater than 15, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..15.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..15.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciBitFieldAndThenOr16 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> +
> + @return The read value from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciRead32 (
> + IN UINTN Address
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value. Value is returned. This function must guarantee
> + that all PCI read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise OR of a 32-bit PCI configuration register with
> + a 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> + value.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 32-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
> + value, followed a bitwise OR with another 32-bit value.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData,
> + performs a bitwise OR between the result of the AND operation and
> + the value specified by OrData, and writes the result to the 32-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address Address that encodes the PCI Bus, Device, Function and
> + Register.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field of a PCI configuration register.
> +
> + Reads the bit field in a 32-bit PCI configuration register. The bit field is
> + specified by the StartBit and the EndBit. The value of the bit field is
> + returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> +
> + @param Address PCI configuration register to read.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> +
> + @return The value of the bit field read from the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciBitFieldRead32 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a bit field to a PCI configuration register.
> +
> + Writes Value to the bit field of the PCI configuration register. The bit
> + field is specified by the StartBit and the EndBit. All other bits in the
> + destination PCI configuration register are preserved. The new value of the
> + 32-bit register is returned.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If Value is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param Value New value of the bit field.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciBitFieldWrite32 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 Value
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
> + writes the result back to the bit field in the 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise OR between the read result and the value specified by
> + OrData, and writes the result to the 32-bit PCI configuration register
> + specified by Address. The value written to the PCI configuration register is
> + returned. This function must guarantee that all PCI read and write operations
> + are serialized. Extra left bits in OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param OrData The value to OR with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciBitFieldOr32 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
> + AND, and writes the result back to the bit field in the 32-bit register.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND between the read result and the value specified by AndData, and
> + writes the result to the 32-bit PCI configuration register specified by
> + Address. The value written to the PCI configuration register is returned.
> + This function must guarantee that all PCI read and write operations are
> + serialized. Extra left bits in AndData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciBitFieldAnd32 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
> + bitwise OR, and writes the result back to the bit field in the
> + 32-bit port.
> +
> + Reads the 32-bit PCI configuration register specified by Address, performs a
> + bitwise AND followed by a bitwise OR between the read result and
> + the value specified by AndData, and writes the result to the 32-bit PCI
> + configuration register specified by Address. The value written to the PCI
> + configuration register is returned. This function must guarantee that all PCI
> + read and write operations are serialized. Extra left bits in both AndData and
> + OrData are stripped.
> +
> + If Address > 0x0FFFFFFF, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> + If StartBit is greater than 31, then ASSERT().
> + If EndBit is greater than 31, then ASSERT().
> + If EndBit is less than StartBit, then ASSERT().
> + If AndData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> + If OrData is larger than the bitmask value range specified by
> + StartBit and EndBit, then ASSERT().
> +
> + @param Address PCI configuration register to write.
> + @param StartBit The ordinal of the least significant bit in the bit field.
> + Range 0..31.
> + @param EndBit The ordinal of the most significant bit in the bit field.
> + Range 0..31.
> + @param AndData The value to AND with the PCI configuration register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the PCI configuration register.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciBitFieldAndThenOr32 (
> + IN UINTN Address,
> + IN UINTN StartBit,
> + IN UINTN EndBit,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned. When possible 32-bit PCI configuration read cycles are used to read
> + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
> + and 16-bit PCI configuration read cycles may be used at the beginning and the
> + end of the range.
> +
> + If StartAddress > 0x0FFFFFFF, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress Starting address that encodes the PCI Bus, Device,
> + Function and Register.
> + @param Size Size in bytes of the transfer.
> + @param Buffer Pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciReadBuffer (
> + IN UINTN StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned. When possible 32-bit PCI configuration write cycles are used to
> + write from StartAdress to StartAddress + Size. Due to alignment restrictions,
> + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
> + and the end of the range.
> +
> + If StartAddress > 0x0FFFFFFF, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress Starting address that encodes the PCI Bus, Device,
> + Function and Register.
> + @param Size Size in bytes of the transfer.
> + @param Buffer Pointer to a buffer containing the data to write.
> +
> + @return Size written to StartAddress.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciWriteBuffer (
> + IN UINTN StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + DEBUG ((DEBUG_ERROR, "ERROR: Function %a is not implemented\n", __func__));
> + ASSERT (FALSE);
> + return 0;
> +}
> diff --git a/MdePkg/Library/PciLibNull/PciLibNull.inf b/MdePkg/Library/PciLibNull/PciLibNull.inf
> new file mode 100644
> index 0000000000000000000000000000000000000000..1778b4025e550939a6d13c5cc466567ce99ebaa5
> --- /dev/null
> +++ b/MdePkg/Library/PciLibNull/PciLibNull.inf
> @@ -0,0 +1,25 @@
> +#/** @file
> +#
> +# Null implementation of Pcilib
> +#
> +# Copyright (c) 2019, ARM Limited. All rights reserved.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001B
> + BASE_NAME = PciLibNull
> + FILE_GUID = C2E95ECC-9A39-4293-9F52-4C82BA370952
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciLib
> +
> +
> +[Sources]
> + PciLibNull.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> +
>
next prev parent reply other threads:[~2020-05-14 9:24 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-14 8:40 [PATCH v2 00/11] Kvmtool guest firmware support for Arm Sami Mujawar
2020-05-14 8:40 ` [PATCH v2 01/11] PcAtChipsetPkg: Add MMIO Support to RTC driver Sami Mujawar
2020-05-14 9:24 ` Ard Biesheuvel
2020-05-15 10:50 ` André Przywara
2020-05-27 0:37 ` [edk2-devel] " Guomin Jiang
2020-05-14 8:40 ` [PATCH v1 02/11] MdePkg: Add NULL implementation for PCILib Sami Mujawar
2020-05-14 9:23 ` Ard Biesheuvel [this message]
2020-05-14 16:21 ` Michael D Kinney
2020-05-14 8:40 ` [PATCH v1 03/11] MdePkg: Base Memory Lib instance using MMIO Sami Mujawar
2020-05-14 9:22 ` Ard Biesheuvel
2020-05-14 17:21 ` Ard Biesheuvel
2020-05-14 16:33 ` [edk2-devel] " Michael D Kinney
2020-05-14 8:40 ` [PATCH v1 04/11] ArmPlatformPkg: Use MMIO to read device memory Sami Mujawar
2020-05-14 8:40 ` [PATCH v1 05/11] ArmPlatformPkg: Dynamic flash variable base Sami Mujawar
2020-05-14 9:24 ` Ard Biesheuvel
2020-05-27 11:48 ` [edk2-devel] " Philippe Mathieu-Daudé
2020-05-14 8:40 ` [PATCH v2 06/11] ArmVirtPkg: Add kvmtool platform driver Sami Mujawar
2020-05-14 9:29 ` Ard Biesheuvel
2020-05-14 12:12 ` [edk2-devel] " Laszlo Ersek
2020-05-14 12:17 ` Ard Biesheuvel
2020-05-14 16:05 ` Laszlo Ersek
2020-05-14 17:25 ` Ard Biesheuvel
2020-05-15 7:28 ` Laszlo Ersek
2020-05-14 12:20 ` Laszlo Ersek
2020-05-14 8:40 ` [PATCH v1 07/11] ArmVirtPkg: kvmtool platform memory map Sami Mujawar
2020-05-14 9:30 ` Ard Biesheuvel
2020-05-14 12:15 ` [edk2-devel] " Laszlo Ersek
2020-05-14 8:40 ` [PATCH v1 08/11] ArmVirtPkg: Add Kvmtool NOR flash lib Sami Mujawar
2020-05-14 9:32 ` Ard Biesheuvel
2020-05-14 12:17 ` [edk2-devel] " Laszlo Ersek
2020-05-27 11:59 ` Philippe Mathieu-Daudé
2020-06-04 6:30 ` Philippe Mathieu-Daudé
2020-06-04 15:00 ` Sami Mujawar
2020-05-14 8:40 ` [PATCH v2 09/11] ArmVirtPkg: Support for kvmtool emulated platform Sami Mujawar
2020-05-14 9:56 ` Ard Biesheuvel
2020-05-14 12:24 ` [edk2-devel] " Laszlo Ersek
2020-05-14 8:40 ` [PATCH v1 10/11] ArmVirtPkg: Link NorFlashDxe with BaseMemoryLibMmio Sami Mujawar
2020-05-14 12:28 ` [edk2-devel] " Laszlo Ersek
2020-05-14 8:40 ` [PATCH v1 11/11] Maintainer.txt: Add Kvmtool emulated plat maintainer Sami Mujawar
2020-05-14 12:31 ` [edk2-devel] " Laszlo Ersek
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