From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.groups.io with SMTP id smtpd.web10.13931.1605643352327962711 for ; Tue, 17 Nov 2020 12:02:32 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=iA+VbZ/Y; spf=pass (domain: redhat.com, ip: 216.205.24.124, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1605643351; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sgN2ZA22E+BNP7WpZhwniZapzCHIrdzXZZ6ecpQ5O/o=; b=iA+VbZ/YzqHiQYWLDliKTa82FuXJaUuLQfM3P8/yoCWlVuWOlYB5BCPVMUmlGfMI1vz5w+ bbT9PfrZmgmB00kgcpObq6NmUoWfD+EoHB4CRhACymiDQ5m9xw3TEwjWZXxxkstgb1TrUl YfaKSrwzIdEZa+G63yZz8cCeSzq3jWE= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-331-JVlE1GA6O8-D3dno5ZsoAg-1; Tue, 17 Nov 2020 15:02:27 -0500 X-MC-Unique: JVlE1GA6O8-D3dno5ZsoAg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 9C7311009464; Tue, 17 Nov 2020 20:02:25 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-112-97.ams2.redhat.com [10.36.112.97]) by smtp.corp.redhat.com (Postfix) with ESMTP id 39E365C1CF; Tue, 17 Nov 2020 20:02:24 +0000 (UTC) Subject: Re: [PATCH v8 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address To: Sheng Wei , devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Jiewen Yao References: <20201116031833.14324-1-w.sheng@intel.com> From: "Laszlo Ersek" Message-ID: Date: Tue, 17 Nov 2020 21:02:23 +0100 MIME-Version: 1.0 In-Reply-To: <20201116031833.14324-1-w.sheng@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/16/20 04:18, Sheng Wei wrote: > When trying to get page table base, if mInternalCr3 is zero, it will use > the page table from CR3, and reflect the page table depth by CR4 LA57 bit. > If mInternalCr3 is non zero, it will use the page table from mInternalCr3 > and reflect the page table depth of mInternalCr3 at same time. > In the case of X64, we use m5LevelPagingNeeded to reflect the depth of > the page table. And in the case of IA32, it will not the page table depth > information. > > This patch is a bug fix when enable CET feature with 5 level paging. > The SMM page tables are allocated / initialized in PiCpuSmmEntry(). > When CET is enabled, PiCpuSmmEntry() must further modify the attribute of > shadow stack pages. This page table is not set to CR3 in PiCpuSmmEntry(). > So the page table base address is set to mInternalCr3 for modifty the > page table attribute. It could not use CR4 LA57 bit to reflect the > page table depth for mInternalCr3. > So we create a architecture-specific implementation GetPageTable() with > 2 output parameters. One parameter is used to output the page table > address. Another parameter is used to reflect if it is 5 level paging > or not. > > Correct the Cr3 typo > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015 > > Signed-off-by: Sheng Wei > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Rahul Kumar > Cc: Jiewen Yao > > Sheng Wei (2): > UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo > UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table > address > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 26 ++++++++++++- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 13 ++++--- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 35 +++++------------- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 43 ++++++++++++++++++---- > 4 files changed, 77 insertions(+), 40 deletions(-) > series Reviewed-by: Laszlo Ersek The 2nd patch needs an ACK from Eric or Ray; then we can merge this series. (It is a bugfix so it can go in even during the hard feature freeze. But we should merge it as soon as we can.) Thanks, Laszlo