From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smarthost01a.ixn.mail.zen.net.uk (smarthost01a.ixn.mail.zen.net.uk [212.23.1.20]) by mx.groups.io with SMTP id smtpd.web08.3263.1645120294166437103 for ; Thu, 17 Feb 2022 09:51:35 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=permerror, err=parse error for token &{10 18 sdn.klaviyomail.com}: permanent DNS error (domain: starlabs.systems, ip: 212.23.1.20, mailfrom: sean@starlabs.systems) Received: from [217.155.46.38] (helo=sean-StarBook.lan) by smarthost01a.ixn.mail.zen.net.uk with esmtp (Exim 4.90_1) (envelope-from ) id 1nKkwE-0004pV-Bv; Thu, 17 Feb 2022 17:51:30 +0000 From: "Sean Rhodes" To: devel@edk2.groups.io Cc: guo.dong@intel.com, Patrick Rudolph , Ray Ni , Maurice Ma , Benjamin You Subject: [PATCH 1/2] UefiPayloadPkg: Add i801 SMBus controller DXE Date: Thu, 17 Feb 2022 17:51:26 +0000 Message-Id: X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Originating-smarthost01a-IP: [217.155.46.38] Feedback-ID: 217.155.46.38 Content-Transfer-Encoding: quoted-printable From: Patrick Rudolph Implement a subset of the gEfiSmbusHcProtocolGuid using a generic PCI i801 SMBus controller. Cc: Guo Dong Cc: Ray Ni Cc: Maurice Ma Cc: Benjamin You Signed-off-by: Patrick Rudolph --- .../Library/BrotliCustomDecompressLib/brotli | 2 +- UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.c | 556 ++++++++++++++++++ UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.h | 17 + UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf | 45 ++ UefiPayloadPkg/UefiPayloadPkg.dsc | 7 + UefiPayloadPkg/UefiPayloadPkg.fdf | 5 + 6 files changed, 631 insertions(+), 1 deletion(-) create mode 100644 UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.c create mode 100644 UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.h create mode 100644 UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf diff --git a/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli b/MdeMod= ulePkg/Library/BrotliCustomDecompressLib/brotli index f4153a09f8..666c3280cc 160000 --- a/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli +++ b/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli @@ -1 +1 @@ -Subproject commit f4153a09f87cbb9c826d8fc12c74642bb2d879ea +Subproject commit 666c3280cc11dc433c303d79a83d4ffbdd12cc8d diff --git a/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.c b/UefiPayloadPkg/SmbusD= xe/SMBusi801Dxe.c new file mode 100644 index 0000000000..7bf7b893ad --- /dev/null +++ b/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.c @@ -0,0 +1,556 @@ +/** @file=0D + Implementation for a generic i801 SMBus driver.=0D +=0D +Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +=0D +**/=0D +=0D +#include "SMBusi801Dxe.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_HANDLE mDriverHandle =3D NULL;=0D +UINT32 PciDevice =3D 0;=0D +=0D +/* SMBus register offsets. */=0D +#define SMBHSTSTAT 0x0=0D +#define SMBHSTCTL 0x2=0D +#define SMBHSTCMD 0x3=0D +#define SMBXMITADD 0x4=0D +#define SMBHSTDAT0 0x5=0D +#define SMBHSTDAT1 0x6=0D +#define SMBBLKDAT 0x7=0D +#define SMBTRNSADD 0x9=0D +#define SMBSLVDATA 0xa=0D +#define SMLINK_PIN_CTL 0xe=0D +#define SMBUS_PIN_CTL 0xf=0D +#define SMBSLVCMD 0x11=0D +=0D +/* I801 command constants */=0D +#define I801_QUICK (0 << 2)=0D +#define I801_BYTE (1 << 2)=0D +#define I801_BYTE_DATA (2 << 2)=0D +#define I801_WORD_DATA (3 << 2)=0D +#define I801_PROCESS_CALL (4 << 2)=0D +#define I801_BLOCK_DATA (5 << 2)=0D +#define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */=0D +=0D +/* I801 Host Control register bits */=0D +#define SMBHSTCNT_INTREN (1 << 0)=0D +#define SMBHSTCNT_KILL (1 << 1)=0D +#define SMBHSTCNT_LAST_BYTE (1 << 5)=0D +#define SMBHSTCNT_START (1 << 6)=0D +#define SMBHSTCNT_PEC_EN (1 << 7) /* ICH3 and later */=0D +=0D +/* I801 Hosts Status register bits */=0D +#define SMBHSTSTS_BYTE_DONE (1 << 7)=0D +#define SMBHSTSTS_INUSE_STS (1 << 6)=0D +#define SMBHSTSTS_SMBALERT_STS (1 << 5)=0D +#define SMBHSTSTS_FAILED (1 << 4)=0D +#define SMBHSTSTS_BUS_ERR (1 << 3)=0D +#define SMBHSTSTS_DEV_ERR (1 << 2)=0D +#define SMBHSTSTS_INTR (1 << 1)=0D +#define SMBHSTSTS_HOST_BUSY (1 << 0)=0D +=0D +/* For SMBXMITADD register. */=0D +#define XMIT_WRITE(dev) (((dev) << 1) | 0)=0D +#define XMIT_READ(dev) (((dev) << 1) | 1)=0D +=0D +STATIC=0D +UINT16=0D +EFIAPI=0D +SmbusGetSMBaseAddress (=0D + IN VOID=0D + )=0D +{=0D + UINT16 Cmd;=0D + UINT32 Reg32;=0D + UINT16 IoBase;=0D +=0D + IoBase =3D 0;=0D + //=0D + // Test if I/O decoding is enabled=0D + //=0D + Cmd =3D PciRead16 (PciDevice + 0x4);=0D + if (!(Cmd & 1)) {=0D + goto CloseAndReturn;=0D + }=0D +=0D + //=0D + // Test if BAR0 is I/O bar and enabled=0D + //=0D + Reg32 =3D PciRead16 (PciDevice + 0x20);=0D + if (!(Reg32 & 1) || !(Reg32 & 0xfffc) || ((Reg32 & 0xfffc) =3D=3D 0xfffc= )) {=0D + goto CloseAndReturn;=0D + }=0D +=0D + IoBase =3D Reg32 & 0xfffc;=0D +=0D +CloseAndReturn:=0D + return IoBase;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +SmbusSetupCommand (=0D + IN UINT16 IoBase,=0D + IN UINT8 Ctrl,=0D + IN UINT8 Xmitadd=0D + )=0D +{=0D + UINTN Loops =3D 10000;=0D + UINT8 host_busy;=0D +=0D + do {=0D + MicroSecondDelay (100);=0D + host_busy =3D IoRead8 (IoBase + SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY;=0D + } while (--Loops && host_busy);=0D +=0D + if (Loops =3D=3D 0) {=0D + return EFI_TIMEOUT;=0D + }=0D +=0D + /* Clear any lingering errors, so the transaction will run. */=0D + IoWrite8 (IoBase + SMBHSTSTAT, IoRead8 (IoBase + SMBHSTSTAT));=0D +=0D + /* Set up transaction */=0D + /* Disable interrupts */=0D + IoWrite8 (IoBase + SMBHSTCTL, Ctrl);=0D +=0D + /* Set the device I'm talking to. */=0D + IoWrite8 (IoBase + SMBXMITADD, Xmitadd);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +SmbusExecuteCommand (=0D + IN UINT16 IoBase=0D + )=0D +{=0D + UINTN Loops =3D 10000;=0D + UINT8 Status;=0D +=0D + /* Start the command. */=0D + IoWrite8 (IoBase + SMBHSTCTL, IoRead8 (IoBase + SMBHSTCTL) | SMBHSTCNT_S= TART);=0D + Status =3D IoRead8 (IoBase + SMBHSTSTAT);=0D +=0D + /* Poll for it to start. */=0D + do {=0D + MicroSecondDelay (100);=0D +=0D + /* If we poll too slow, we could miss HOST_BUSY flag=0D + * set and detect INTR or x_ERR flags instead here.=0D + */=0D + Status =3D IoRead8 (IoBase + SMBHSTSTAT);=0D +=0D + Status &=3D ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS);=0D + } while (--Loops && Status =3D=3D 0);=0D +=0D + if (Loops =3D=3D 0) {=0D + return EFI_TIMEOUT;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC=0D +BOOLEAN=0D +SmbusHostCompleted (=0D + IN UINT8 Status=0D + )=0D +{=0D + if (Status & SMBHSTSTS_HOST_BUSY) {=0D + return FALSE;=0D + }=0D +=0D + /* These status bits do not imply completion of transaction. */=0D + Status &=3D ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBA= LERT_STS);=0D + return Status !=3D 0;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +SmbusCompleteCommand (=0D + IN UINT16 IoBase=0D + )=0D +{=0D + UINTN Loops =3D 10000;=0D + UINT8 Status;=0D +=0D + do {=0D + MicroSecondDelay (100);=0D + Status =3D IoRead8 (IoBase + SMBHSTSTAT);=0D + } while (--Loops && !SmbusHostCompleted (Status));=0D +=0D + if (Loops =3D=3D 0) {=0D + return EFI_TIMEOUT;=0D + }=0D +=0D + /* These status bits do not imply errors. */=0D + Status &=3D ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | SMBHSTSTS_SMBA= LERT_STS);=0D +=0D + if (Status =3D=3D SMBHSTSTS_INTR) {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + return EFI_NO_RESPONSE;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusProcessCallOperation (=0D + IN CONST UINT16 IoBase,=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,=0D + IN EFI_SMBUS_DEVICE_COMMAND Command,=0D + IN BOOLEAN PecCheck,=0D + IN OUT UINTN *Length,=0D + IN OUT VOID *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 ResultBuffer;=0D + UINT16 AddrBuffer;=0D +=0D + if (!Buffer || !Length) {=0D + return RETURN_INVALID_PARAMETER;=0D + }=0D +=0D + if (*Length !=3D 2) {=0D + return RETURN_INVALID_PARAMETER;=0D + }=0D +=0D + CopyMem (&AddrBuffer, Buffer, sizeof (AddrBuffer));=0D +=0D + /* Set up for process call */=0D + Status =3D SmbusSetupCommand (IoBase, I801_PROCESS_CALL, XMIT_WRITE (Sla= veAddress.SmbusDeviceAddress));=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* cmd will only be send if I2C_EN is zero */=0D + IoWrite8 (IoBase + SMBHSTCMD, Command);=0D +=0D + IoWrite8 (IoBase + SMBHSTDAT0, AddrBuffer & 0x00ff);=0D + IoWrite8 (IoBase + SMBHSTDAT1, (AddrBuffer & 0xff00) >> 8);=0D +=0D + /* Start the command */=0D + Status =3D SmbusExecuteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* Poll for transaction completion */=0D + Status =3D SmbusCompleteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* Read results of transaction */=0D + ResultBuffer =3D IoRead8 (IoBase + SMBHSTDAT0);=0D + ResultBuffer |=3D (IoRead8 (IoBase + SMBHSTDAT1) << 8);=0D +=0D + CopyMem (Buffer, &ResultBuffer, sizeof (ResultBuffer));=0D + *Length =3D sizeof (ResultBuffer);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusReadOperation (=0D + IN CONST UINT16 IoBase,=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,=0D + IN EFI_SMBUS_DEVICE_COMMAND Command,=0D + IN BOOLEAN PecCheck,=0D + IN OUT UINTN *Length,=0D + IN OUT VOID *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT8 ResultBuffer;=0D +=0D + if (!Buffer || !Length) {=0D + return RETURN_INVALID_PARAMETER;=0D + }=0D +=0D + /* Set up for a byte data read. */=0D + Status =3D SmbusSetupCommand (IoBase, I801_BYTE_DATA, XMIT_READ (SlaveAd= dress.SmbusDeviceAddress));=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + IoWrite8 (IoBase + SMBHSTCMD, Command);=0D +=0D + IoWrite8 (IoBase + SMBHSTDAT0, 0);=0D + IoWrite8 (IoBase + SMBHSTDAT1, 0);=0D +=0D + /* Start the command */=0D + Status =3D SmbusExecuteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* Poll for transaction completion */=0D + Status =3D SmbusCompleteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* Read results of transaction */=0D + ResultBuffer =3D IoRead8 (IoBase + SMBHSTDAT0);=0D +=0D + CopyMem (Buffer, &ResultBuffer, sizeof (ResultBuffer));=0D + *Length =3D sizeof (ResultBuffer);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusWriteOperation (=0D + IN CONST UINT16 IoBase,=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,=0D + IN EFI_SMBUS_DEVICE_COMMAND Command,=0D + IN BOOLEAN PecCheck,=0D + IN OUT UINTN *Length,=0D + IN OUT VOID *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT8 InputBuffer;=0D +=0D + if (!Buffer || !Length) {=0D + return RETURN_INVALID_PARAMETER;=0D + }=0D +=0D + if (*Length !=3D 1) {=0D + return RETURN_INVALID_PARAMETER;=0D + }=0D +=0D + CopyMem (&InputBuffer, Buffer, sizeof (InputBuffer));=0D +=0D + /* Set up for a byte data read. */=0D + Status =3D SmbusSetupCommand (IoBase, I801_BYTE_DATA, XMIT_WRITE (SlaveA= ddress.SmbusDeviceAddress));=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + IoWrite8 (IoBase + SMBHSTCMD, Command);=0D +=0D + IoWrite8 (IoBase + SMBHSTDAT0, InputBuffer);=0D +=0D + /* Start the command */=0D + Status =3D SmbusExecuteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + /* Poll for transaction completion */=0D + Status =3D SmbusCompleteCommand (IoBase);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusExecuteOperation (=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,=0D + IN EFI_SMBUS_DEVICE_COMMAND Command,=0D + IN EFI_SMBUS_OPERATION Operation,=0D + IN BOOLEAN PecCheck,=0D + IN OUT UINTN *Length,=0D + IN OUT VOID *Buffer=0D + )=0D +{=0D + UINT16 IoBase;=0D +=0D + IoBase =3D SmbusGetSMBaseAddress ();=0D + if (!IoBase) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + if (Operation =3D=3D EfiSmbusProcessCall) {=0D + return SmbusProcessCallOperation (=0D + IoBase,=0D + This,=0D + SlaveAddress,=0D + Command,=0D + PecCheck,=0D + Length,=0D + Buffer=0D + );=0D + } else if (Operation =3D=3D EfiSmbusReadByte) {=0D + return SmbusReadOperation (=0D + IoBase,=0D + This,=0D + SlaveAddress,=0D + Command,=0D + PecCheck,=0D + Length,=0D + Buffer=0D + );=0D + } else if (Operation =3D=3D EfiSmbusWriteByte) {=0D + return SmbusWriteOperation (=0D + IoBase,=0D + This,=0D + SlaveAddress,=0D + Command,=0D + PecCheck,=0D + Length,=0D + Buffer=0D + );=0D + }=0D +=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusHcProtocolArpDevice (=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN BOOLEAN ArpAll,=0D + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL=0D + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusHcProtocolGetArpMap (=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN OUT UINTN *Length,=0D + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +STATIC=0D +EFI_STATUS=0D +EFIAPI=0D +SmbusHcProtocolNotify (=0D + IN CONST EFI_SMBUS_HC_PROTOCOL *This,=0D + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,=0D + IN UINTN Data,=0D + IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +EFI_SMBUS_HC_PROTOCOL mSmbusProtocol =3D {=0D + SmbusExecuteOperation,=0D + SmbusHcProtocolArpDevice,=0D + SmbusHcProtocolGetArpMap,=0D + SmbusHcProtocolNotify=0D +};=0D +=0D +/**=0D + The Entry Point for SMBUS driver.=0D +=0D + It installs DriverBinding.=0D +=0D + @retval EFI_SUCCESS The entry point is executed successfully.=0D + @retval other Some error occurs when executing this entry po= int.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InstallSmbusProtocol (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 IoBase;=0D + UINT8 Device;=0D + UINT8 Function;=0D + BOOLEAN BreakLoop;=0D + UINT8 BaseClass;=0D + UINT8 SubClass;=0D +=0D + BreakLoop =3D FALSE;=0D + Status =3D EFI_SUCCESS;=0D +=0D + //=0D + // Search for SMBus Controller within PCI Devices on root bus=0D + //=0D + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) {=0D + for (Function =3D 0; Function <=3D PCI_MAX_FUNC; Function++) {=0D + if (PciRead16 (PCI_LIB_ADDRESS (0, Device, Function, 0x00)) !=3D 0x8= 086) {=0D + continue;=0D + }=0D +=0D + BaseClass =3D PciRead8 (PCI_LIB_ADDRESS (0, Device, Function, 0x0B))= ;=0D +=0D + if (BaseClass =3D=3D PCI_CLASS_SERIAL) {=0D + SubClass =3D PciRead8 (PCI_LIB_ADDRESS (0, Device, Function, 0xA))= ;=0D +=0D + if (SubClass =3D=3D PCI_CLASS_SERIAL_SMB) {=0D + BreakLoop =3D TRUE;=0D + PciDevice =3D PCI_LIB_ADDRESS (0, Device, Function, 0x00);=0D + break;=0D + }=0D + }=0D + }=0D +=0D + if (BreakLoop) {=0D + break;=0D + }=0D + }=0D +=0D + if (!BreakLoop) {=0D + DEBUG ((EFI_D_INFO, "No PCI SMBUS controller found.\n"));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + DEBUG ((EFI_D_INFO, "PCI Device found on 0-%x-%x\n", Device, Function));= =0D +=0D + IoBase =3D SmbusGetSMBaseAddress ();=0D + if (!IoBase) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + DEBUG ((=0D + EFI_D_INFO,=0D + "%a: Detected i801 SMBus controller with SMBASE 0x%x\n",=0D + __FUNCTION__,=0D + IoBase=0D + ));=0D +=0D + Status =3D gBS->InstallProtocolInterface (=0D + &mDriverHandle,=0D + &gEfiSmbusHcProtocolGuid,=0D + EFI_NATIVE_INTERFACE,=0D + &mSmbusProtocol=0D + );=0D +=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.h b/UefiPayloadPkg/SmbusD= xe/SMBusi801Dxe.h new file mode 100644 index 0000000000..e88823da31 --- /dev/null +++ b/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.h @@ -0,0 +1,17 @@ +/** @file=0D + Header file for a generic i801 SMBUS driver.=0D +=0D +Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +=0D +**/=0D +#ifndef _PCI_PLATFORM_DXE_H_=0D +#define _PCI_PLATFORM_DXE_H_=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#endif=0D diff --git a/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf b/UefiPayloadPkg/Smbu= sDxe/SMBusi801Dxe.inf new file mode 100644 index 0000000000..7d13c446ef --- /dev/null +++ b/UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf @@ -0,0 +1,45 @@ +## @file=0D +# This driver produces gEfiSmbusHcProtocolGuid protocol to load access SMB= US devices=0D +#=0D +# Copyright (c) 2020, 9elements Agency GmbH=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SMBusi801Dxe=0D + FILE_GUID =3D 390208DA-8E6F-4957-90D6-421737FEA9BF= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InstallSmbusProtocol=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources.common]=0D + SMBusi801Dxe.h=0D + SMBusi801Dxe.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D +=0D +[LibraryClasses]=0D + UefiDriverEntryPoint=0D + DebugLib=0D + IoLib=0D + UefiLib=0D + TimerLib=0D + PciLib=0D +=0D +[Protocols]=0D + gEfiSmbusHcProtocolGuid ## PRODUCES=0D +=0D +[Depex]=0D + TRUE=0D diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayload= Pkg.dsc index 1ce96a51c1..54543b7623 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -290,6 +290,7 @@ !if $(PERFORMANCE_MEASUREMENT_ENABLE)=0D PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerform= anceLib.inf=0D !endif=0D + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf=0D =0D [LibraryClasses.common.DXE_DRIVER]=0D PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D @@ -304,6 +305,7 @@ !if $(PERFORMANCE_MEASUREMENT_ENABLE)=0D PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf=0D !endif=0D + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf=0D =0D [LibraryClasses.common.DXE_RUNTIME_DRIVER]=0D PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D @@ -657,6 +659,11 @@ !endif=0D MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D =0D + #=0D + # SMBUS Support=0D + #=0D + UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf=0D +=0D #=0D # Console Support=0D #=0D diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayload= Pkg.fdf index c7b04978ad..8861d29162 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.fdf +++ b/UefiPayloadPkg/UefiPayloadPkg.fdf @@ -178,6 +178,11 @@ INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe= .inf !endif=0D INF MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf=0D =0D +#=0D +# SMBUS Support=0D +#=0D +INF UefiPayloadPkg/SmbusDxe/SMBusi801Dxe.inf=0D +=0D #=0D # Console Support=0D #=0D --=20 2.32.0