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From: "Isaac Oram" <isaac.w.oram@intel.com>
To: devel@edk2.groups.io
Cc: Isaac Oram <isaac.w.oram@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>,
	Chasel Chiu <chasel.chiu@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg: Update to Whitley FSP 4.2.0.2A
Date: Thu, 12 Jan 2023 15:56:34 -0800	[thread overview]
Message-ID: <c93b90be86517db82a133d4ed160eef116be2e59.1673561471.git.isaac.w.oram@intel.com> (raw)
In-Reply-To: <cover.1673561471.git.isaac.w.oram@intel.com>

This contains binary interface changes and requires FSP 4.2.0.2A or later

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
 Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec   | 23 +++++++++-------
 .../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec  |  4 ++-
 .../Cpu/Include/CpuPolicyPeiDxeCommon.h       |  2 +-
 .../WhitleySiliconPkg/Include/BdatSchema.h    | 16 +++++++-----
 .../Include/Guid/MemoryMapData.h              |  4 ++-
 .../Include/Guid/SocketIioVariable.h          | 13 +++++++---
 .../Include/Guid/SocketMemoryVariable.h       |  3 +++
 .../Include/Guid/SocketPciResourceData.h      |  4 ++-
 .../Guid/SocketPowermanagementVariable.h      |  2 ++
 .../Guid/SocketProcessorCoreVariable.h        |  2 +-
 .../WhitleySiliconPkg/Include/IioConfig.h     | 11 +++-----
 .../Intel/WhitleySiliconPkg/Include/IioRegs.h |  1 -
 .../Include/Library/EnhancedWarningLogLib.h   |  2 --
 .../Include/PlatformInfoTypes.h               | 16 +++++++-----
 .../Include/Ppi/MemoryPolicyPpi.h             | 10 +++++++
 .../Include/Ppi/RasImcS3Data.h                |  6 -----
 .../WhitleySiliconPkg/Include/Upi/KtiHost.h   |  2 --
 .../Core/Include/DataTypes.h                  | 10 ++++++-
 .../BaseMemoryCoreLib/Core/Include/MemHost.h  |  6 +----
 .../BaseMemoryCoreLib/Platform/PlatformHost.h |  5 ----
 .../Include/Private/Library/PchSpiCommonLib.h |  1 -
 .../Product/Whitley/SiliconPkg10nmPcds.dsc    |  5 ++++
 .../SecurityIp/SecurityIpSgxTem1v0_Inputs.h   |  2 +-
 .../SecurityIp/SecurityIpSgxTem1v0_Outputs.h  |  2 +-
 .../Intel/WhitleySiliconPkg/SiliconPkg.dec    | 26 ++++++++++++-------
 25 files changed, 106 insertions(+), 72 deletions(-)

diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
index 2ccdbffa35..db61caf399 100644
--- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
@@ -252,9 +252,9 @@
       WhitleySiliconPkg/CpRcPkg.dec
   }
   gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0
-  gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2
+  gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4
   gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2
-  gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a
+  gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A
 
   #
   # MRC DEFAULT SETTINGS
@@ -273,7 +273,7 @@
   #
   gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault             |                     0|  UINT8|0x00000040
 
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved8           |                 FALSE|BOOLEAN|0x0000003A
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved8                     |                 FALSE|BOOLEAN|0x0000003A
 
 
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault       |                 FALSE|BOOLEAN|0x00000060
@@ -285,7 +285,7 @@
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault        |                   0x2|  UINT8|0x00000066
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault         |                 FALSE|BOOLEAN|0x00000067
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault         |                   0x6|  UINT8|0x00000068
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved9       |                  TRUE|BOOLEAN|0x00000069
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved9                     |                  TRUE|BOOLEAN|0x00000069
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault            |                  TRUE|  UINT8|0x0000006A
 
 
@@ -293,10 +293,10 @@
   gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString     |L"MemBootHealthConfig"|  VOID*|0x00000070
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault            |                 FALSE|BOOLEAN|0x00000071
   gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault     |                 FALSE|BOOLEAN|0x00000072
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved10           |                     1|  UINT8|0x00000073
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved11               |                     1|  UINT8|0x00000074
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved12          |                     2|  UINT8|0x0000011F
-  gEfiCpRcPkgTokenSpaceGuid.PcdReserved13          |                  TRUE|BOOLEAN|0x00000120
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved10                    |                     1|  UINT8|0x00000073
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved11                    |                     1|  UINT8|0x00000074
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved12                    |                     2|  UINT8|0x0000011F
+  gEfiCpRcPkgTokenSpaceGuid.PcdReserved13                    |                  TRUE|BOOLEAN|0x00000120
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault     |                 FALSE|BOOLEAN|0x00000075
   #option to choose Mem Boot Health configuration type. 00=>Auto (Use defaults), 01=>Manual (Override defaults with setup option), 02=>Disable (Disable feature)
   gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck            |                    00|  UINT8|0x00000076
@@ -360,6 +360,11 @@
   # Ctl timing: CtlAll
   gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin     |                     5|  UINT8|0x00000131
 
+  #MC VC0 Deadlock Breaker
+  gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings            |                  TRUE|  BOOLEAN|0x00000132
+  gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer                   |                    18|    UINT8|0x00000133
+  gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold               |                     4|    UINT8|0x00000134
+
   #Reset on Critical Margin failure to perform Memory Training from scratch
   gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError          |                     1|  UINT8|0x00000087
 
@@ -526,7 +531,7 @@
   gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000036
   gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x00000118
 ## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor
-  gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C
+  gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C
   gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D
 
 [PcdsDynamicEx]
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
index 7b027b58c6..763b9d31e4 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
@@ -91,7 +91,9 @@
   # @Prompt CPU Config Register Table Entry Maximum Count.
   gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x60000022
 
-[PcdsDynamic, PcdsDynamicEx]
+  gCpuPkgTokenSpaceGuid.PcdCpuLowestApicIdAsBsp|TRUE|BOOLEAN|0x60000023
+
+[PcdsDynamicEx]
   gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001
 
   gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
index 6e84e0f7a6..dc5e09ea19 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
@@ -52,7 +52,7 @@ typedef struct {
   UINT8     CpuMtoIWa;
   BOOLEAN   RunCpuPpmInPei;
   BOOLEAN   AcExceptionOnSplitLockEnable;
-  BOOLEAN   CpuCrashLogGprs;
+  BOOLEAN   CpuCrashDataGprs;
 } CPU_POLICY_COMMON;
 
 #endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
index 0b80015c65..010e8183af 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
@@ -131,12 +131,16 @@ typedef struct {
 // List of all entry types supported by this revision of memory training data structure
 //
 typedef enum {
-  MemTrainingDataCapability  = 0,
-  MemTrainingDataIoGroup     = 1,
-  MemTrainingDataDram        = 2,
-  MemTrainingDataRcd         = 3,
-  MemTrainingDataIoSignal    = 4,
-  MemTrainingDataIoLatency   = 5,
+  MemTrainingDataCapability       = 0,
+  MemTrainingDataIoGroup          = 1,
+  MemTrainingDataDram             = 2,
+  MemTrainingDataRcd              = 3,
+  MemTrainingDataIoSignal         = 4,
+  MemTrainingDataIoLatency        = 5,
+  MemTrainingDataPpin             = 6,
+  MemTrainingDataBoardUuid        = 7,
+  MemTrainingDataTurnaround       = 8,
+  MemTrainingDataDcPmmTurnaround  = 9,
 
   MemTrainingDataTypeMax,
   MemTrainingDataTypeDelim = MAX_INT32
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
index 73f303594a..f7a14ff5f4 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
@@ -85,7 +85,9 @@ struct ChannelDevice {
   UINT8                               SpareLogicalRank[MAX_SPARE_RANK];   // Logical rank, selected as Spare
   UINT8                               SparePhysicalRank[MAX_SPARE_RANK];  // Physical rank, selected as spare
   UINT16                              SpareRankSize[MAX_SPARE_RANK];      // spare rank size
-  UINT8                               EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+  UINT8                               EnabledLogicalRanks;                // Bitmap of Logical ranks that are enabled
+  UINT8                               DdrPopulationMap;                   // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+  UINT8                               PmemPopulationMap;                  // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
   MEMMAP_DIMM_DEVICE_INFO_STRUCT      DimmInfo[MAX_DIMM];
 };
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
index a820cc6c25..0fafd00c98 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
@@ -133,8 +133,8 @@ typedef struct {
     UINT8   PcieSubSystemMode[TOTAL_IOU_VAR];
     UINT8   CompletionTimeoutGlobal;
     UINT8   CompletionTimeoutGlobalValue;
-    UINT8   CompletionTimeout[MAX_SOCKET];  // On Setup
-    UINT8   CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+    UINT8   ReservedCto[MAX_SOCKET];           // On Setup
+    UINT8   ReservedCtov[MAX_SOCKET];          // On Setup
     UINT8   CoherentReadPart;
     UINT8   CoherentReadFull;
     UINT8   PcieGlobalAspm;
@@ -372,7 +372,7 @@ typedef struct {
   UINT8  ReservedS19;       // On Setup
   UINT8  ReservedS20;          // On Setup
   UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup
-  UINT8  ReservedS22[TOTAL_PORTS_VAR];                   // On Setup
+  UINT8  CompletionTimeoutValue[TOTAL_PORTS_VAR];                   // On Setup
 
   UINT8  ReservedS23[TOTAL_PORTS_VAR];          //On Setup
   UINT8  ReservedS24[TOTAL_PORTS_VAR];              //On Setup
@@ -437,7 +437,12 @@ typedef struct {
   UINT8    VtdPciAcsCtlBit2;
   UINT8    VtdPciAcsCtlBit3;
   UINT8    VtdPciAcsCtlBit4;
-  UINT8    AltAttenTable[TOTAL_PORTS_VAR];    //On Setup
+  UINT8    AltAttenTable[TOTAL_PORTS_VAR];
+  UINT8    PciePort10bitTag[TOTAL_PORTS_VAR]; // Controls port support for 10-bit Tag
+
+  UINT8    MaskPcieRpWarmResetMcaWa;                 //on Setup
+  UINT8    PostedInterruptThrottle;
+
 } SOCKET_IIO_CONFIGURATION;
 #pragma pack()
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
index 533489fafc..f8710ee7bb 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
@@ -469,6 +469,9 @@ typedef struct {
   UINT8                   RmtMinimumMarginCheck;
 
   UINT8                   ReservedS149;
+  UINT8                   pTRR;
+  UINT8                   AdrPatrolScrubDisable;
+
 } SOCKET_MEMORY_CONFIGURATION;
 
 #pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
index 567a44e73f..439f61c88d 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
@@ -41,11 +41,13 @@ typedef struct {
   // If anything changed reset the system PCI resource configuration.
   //
   UINT64                 MmioHBase;
-  UINT64                 MmioHLimit;
+  UINT64                 MmioHGranularity;
   UINT32                 MmioLBase;
   UINT32                 MmioLLimit;
+  UINT32                 MmioLGranularity;
   UINT16                 IoBase;
   UINT16                 IoLimit;
+  UINT16                 IoGranularity;
   UINT16                 StackPresentBitmap[MAX_SOCKET];
   //
   // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
index 460e6e300b..c29bf51cb6 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
@@ -290,6 +290,8 @@ typedef struct {
   UINT8   RunCpuPpmInPei;
 
   UINT8   UncoreFreqRaplLimit;
+
+  UINT8   PrgTjOffsetEn;
 } SOCKET_POWERMANAGEMENT_CONFIGURATION;
 #pragma pack()
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
index 52ab370ce7..ca4ebd4d4a 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
@@ -136,7 +136,7 @@ typedef struct {
   UINT8  CFRS3mManualCommit;
   UINT8  CFRPucodeEnable;
   UINT8  CFRPucodeManualCommit;
-  UINT8  CpuCrashLogGprs;
+  UINT8  CpuCrashDataGprs;
 } SOCKET_PROCESSORCORE_CONFIGURATION;
 #pragma pack()
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
index a8e3e69255..385db192d2 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
@@ -45,6 +45,7 @@ typedef struct {
   UINT8   PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];   // On Setup
   UINT8   PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
   UINT8   PciePortLinkSpeed[MAX_TOTAL_PORTS];
+  UINT8   PciePort10bitTag[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
   UINT8   PciePtm;
   UINT8   PcieHotPlugEnable;
   UINT8   PCIe_LTR;
@@ -104,8 +105,7 @@ typedef struct {
 
     UINT8   CompletionTimeoutGlobal;
     UINT8   CompletionTimeoutGlobalValue;
-    UINT8   CompletionTimeout[MAX_SOCKET];  // On Setup
-    UINT8   CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+    UINT8   CompletionTimeoutValue[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup
     UINT8   CoherentReadPart;
     UINT8   CoherentReadFull;
     UINT8   PcieGlobalAspm;
@@ -124,7 +124,6 @@ typedef struct {
     UINT8    PcieLinkDis[MAX_TOTAL_PORTS];          // On Setup
     UINT8    PcieCommonClock[MAX_TOTAL_PORTS];  // On Setup
     UINT8    PcieDState[MAX_TOTAL_PORTS];           // On Setup
-    UINT8    PcieL0sLatency[MAX_TOTAL_PORTS];       //On Setup
     UINT8    PcieL1Latency[MAX_TOTAL_PORTS];        //On Setup
     UINT8    MsiEn[MAX_TOTAL_PORTS];                // On Setup
     UINT8    IODC[MAX_TOTAL_PORTS];                 // On Setup
@@ -273,6 +272,7 @@ typedef struct {
   UINT8   ProblematicPort;                          //on Setup
   UINT8   DmiAllocatingFlow;                        //on Setup
   UINT8   PcieAllocatingFlow;                       //on Setup
+  UINT8   MaskPcieRpWarmResetMcaWa;                 //on Setup
   UINT8   PcieAcpiHotPlugEnable;                    //on Setup
   BOOLEAN PcieLowLatencyRetimersEnabled;
   UINT8   HaltOnDmiDegraded;                        //on Setup
@@ -335,13 +335,10 @@ typedef struct {
   UINT32  ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
   UINT32  ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
 
-  UINT8   ReservedAE[MAX_TOTAL_PORTS];  // On Setup
-
   UINT8   ReservedAF[MAX_TOTAL_PORTS];
   UINT8   ReservedAG[MAX_TOTAL_PORTS];  // On Setup
   BOOLEAN ReservedAH;                // On Setup
 
-
 /**
 ==================================================================================================
 ======================    IIO Global Performance Tuner Related Setup Options =====================
@@ -374,7 +371,6 @@ typedef struct {
   UINT8   MSINFATEN[MAX_TOTAL_PORTS];
   UINT8   MSICOREN[MAX_TOTAL_PORTS];
   UINT8   ACPIPMEn[MAX_TOTAL_PORTS];
-  UINT8   DISL0STx[MAX_TOTAL_PORTS];
   UINT8   P2PRdDis[MAX_TOTAL_PORTS];
   UINT8   DisPMETOAck[MAX_TOTAL_PORTS];
   UINT8   ACPIHP[MAX_TOTAL_PORTS];
@@ -393,6 +389,7 @@ typedef struct {
   IIO_PCIE_CONFIG_DATA  IioPcieConfig;
 
   UINT32  VtdDisabledBitmask[MAX_SOCKET];
+  UINT8   PostedInterruptThrottle;
 } IIO_CONFIG;
 #pragma pack()
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
index 37a1e627da..66cb1e3dfc 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
@@ -128,7 +128,6 @@
 #define PCIE_PORT_0_FUNC_0    0x00
 
 #define PCIE_PORT_1A_DEV_1    0x02
-#define PCIE_PORT_1A_FUNC_1   0x00
 #define PCIE_PORT_1B_DEV_1    0x03
 #define PCIE_PORT_1C_DEV_1    0x04
 #define PCIE_PORT_1D_DEV_1    0x05
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
index 211dc48c86..745a52dafe 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
@@ -191,9 +191,7 @@ typedef struct {
   UINT32 EccS;
   UINT32 Chunk;
   UINT32 Column;
-  UINT32 ColumnExt;
   UINT32 Row;
-  UINT32 RowExt;
   UINT32 Bank;
   UINT32 Rank;
   UINT32 Subrank;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
index 8fc0efec24..0c14a2409f 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -41,10 +41,10 @@ typedef enum {
   TypeWilsonCityModular,
   TypeCoyotePass,
   TypeIdaville,
-  TypeMoroCityRP,
-  TypeBrightonCityRp,
+  TypeMoroCityRP = 0x0E,  //maps to PcdDefaultBoardId
+  TypeBrightonCityRp = 0x0F,  //maps to PcdDefaultBoardId value
   TypeJacobsville,
-  TypeSnrSvp,
+  TypeSnrSvp = 0x11,  //maps to PcdDefaultBoardId
   TypeSnrSvpSodimm,
   TypeJacobsvilleMDV,
   TypeFrostCreekRP,
@@ -64,13 +64,15 @@ typedef enum {
   TypeArcherCityXPV,
   TypeBigPineKey,
   TypeExperWorkStationRP,
-  TypeJunctionCity,
-  TypeAowanda,
+  TypeAmericanPass,
   EndOfEfiPlatformTypeEnum,
   //
   // Vendor board range currently starts at 0x80
   //
-  TypeBoardPortTemplate               // 0x80
+  TypeBoardPortTemplate,               // 0x80
+  TypeJunctionCity,
+  TypeAowanda,
+  EndOfVendorPlatformTypeEnum
 } EFI_PLATFORM_TYPE;
 
 #define TypePlatformUnknown       0xFF
@@ -78,7 +80,7 @@ typedef enum {
 #define TypePlatformMax           EndOfEfiPlatformTypeEnum - 1
 #define TypePlatformDefault       TypeWilsonPointRP
 #define TypePlatformVendorMin     0x80
-#define TypePlatformVendorMax     TypeBoardPortTemplate - 1
+#define TypePlatformVendorMax     EndOfVendorPlatformTypeEnum - 1
 
 //
 // CPU type: Standard (no MCP), -F, etc
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
index 38b90713f7..7a86804d9b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
@@ -1905,6 +1905,7 @@ struct memSetup {
   /// 1 = High<BR>
   /// 2 = Low<BR>
   UINT8   PanicWm;
+  UINT8   pTRR;
 
   /// @brief
   /// Enable/Disable LRDIMM DB DFE.<BR>
@@ -1923,6 +1924,15 @@ struct memSetup {
   //
   UINT8                 VirtualNumaEnable;
 
+  ///
+  /// @brief
+  /// Enable/Disable patrol scrub when entering the ADR.<BR>
+  /// @details
+  /// 0 - disable.<BR>
+  /// 1 - enable.<BR>
+  //
+  UINT8                 AdrPatrolScrubDisable;
+
   ///
   /// @brief
   /// Smart Test Key pattern.<BR>
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
index 2198f8516a..82725bc84e 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
@@ -44,13 +44,7 @@ EFI_STATUS
   OUT       VOID                            *Data
   );
 
-/**
- RAS IMC S3 Data PPI
-**/
 struct _RAS_IMC_S3_DATA_PPI {
-  /**
-    Retrieves data for S3 saved memory RAS features from non-volatile storage.
-  **/
   RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA  GetImcS3RasData;
 };
 
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
index 09a3f37edf..5cadda4907 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
@@ -300,12 +300,10 @@ typedef struct {
 
     Contains a pointer to a 24 byte fixed length array.
     The array contains the 3 instances of the following c-struct
-    ~~~
     typedef struct {
       UINT32  CfrImagePtr;
       UINT32  CfrImageSize;
     }
-    ~~~
     This allows a maximum of 3 CFR/SINIT binaries to be provided by platform code.
   **/
   UINT32              CFRImagePtr;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
index eb4bd92a1d..ef1775e1ed 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
@@ -12,11 +12,17 @@
 
 #include <Base.h>
 
+///
+/// 8-byte DWORD addressable unsigned value.
+///
 typedef struct u64_struct {
   UINT32  lo;
   UINT32  hi;
 } UINT64_STRUCT, *PUINT64_STRUCT;
 
+///
+/// 8-byte DWORD addressable unsigned value.
+///
 typedef union {
   struct {
     UINT32  Low;
@@ -25,7 +31,9 @@ typedef union {
   UINT64 Data;
 } UINT64_DATA;
 
-
+///
+/// 16-byte DWORD addressable unsigned value.
+///
 typedef struct u128_struct {
   UINT32  one;
   UINT32  two;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
index 8eaea40f72..3ae5bcb612 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
@@ -641,11 +641,9 @@ struct rankDevice {
 ///
 typedef struct dimmDevice {
   INT32               minTCK;     ///< minimum tCK for this DIMM (SPD_MIN_TCK)
-#ifdef DEBUG_CODE_BLOCK
   UINT32              tCL;
   UINT16              tRCD;
   UINT16              tRP;
-#endif  // DEBUG_CODE_BLOCK
   UINT16              NVmemSize;
   UINT16              memSize;    ///< Memory size for this DIMM (64MB granularity)
   UINT16              UnmappedMemSize;
@@ -653,6 +651,7 @@ typedef struct dimmDevice {
   struct FmcCacheSt   FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status
   UINT8               SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DIMM partitionRatios
   UINT8               CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MAX_STROBE/2];  // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB
+  BOOLEAN             TrainingModeEnabled; //Training Mode for BPS
   BOOLEAN             FmcWdbFlushFailed; /// < 0 = WDB flush failed on previous boot, 1 = WDB flush completed w/o errors on previous boot
   BOOLEAN             EadrFlushFailed;   /// < 0 = Extended ADR flush failed on previous boot, 1 = Extended ADR flush completed w/o errors on previous boot
 } DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice
@@ -919,9 +918,7 @@ typedef struct memVar {
   UINT8                   callingTrngOffstCfgOnce; ///<to prevent looping inside RMT
   UINT8                   earlyCmdClkExecuted;
   UINT8                   checkMappedOutRanks;
-#ifdef DEBUG_CODE_BLOCK
   UINT8                   earlyCtlClkSerialDebugFlag;
-#endif // DEBUG_CODE_BLOCK
   UINT32                  memSize;          ///< Total physical memory size
   UINT32                  NVmemSize;          ///< Total physical memory size
   UINT32                  TotalInterleavedMemSize;      ///< DDR4 memory size for this socket (64MB granularity)
@@ -1048,4 +1045,3 @@ typedef struct memVar {
 #pragma pack(pop)
 
 #endif // _memhost_h
-
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
index aa9b570f63..2fa735b65b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
@@ -24,12 +24,7 @@
 #define MAX_PPR_ADDR_ENTRIES           20
 #define MAX_PPR_ADDR_ENTRIES_SPPR      40
 
-#if !defined(SILENT_MODE)
-#define DEBUG_CODE_BLOCK  1
-#endif
-
 #define UBIOS_GENERATION_EN               BIT22     // flag to enable DfxUbiosGeneration from Simics
 #define HYBRID_SYSTEM_LEVEL_EMULATION_EN  BIT23     // flag to enable DfxHybridSystemLevelEmulation from Simics
 
 #endif   // _platformhost_h
-
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
index f93740f4f0..a1fd5ae0f5 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
@@ -53,7 +53,6 @@ typedef struct {
   EFI_HANDLE            Handle;
   PCH_SPI_PROTOCOL      SpiProtocol;
   UINT16                PchAcpiBase;
-  UINTN                 PchSpiBase;
   UINT16                ReadPermission;
   UINT16                WritePermission;
   UINT32                SfdpVscc0Value;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
index f9c588b61c..1988965205 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
+++ b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
@@ -26,6 +26,11 @@
   gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE
 
   # Default SMBUS speed for Whitley is 700Khz - see SMB_CLOCK_FREQUENCY definition
+  # 0 - SMB_CLK_100K - 100 Khz
+  # 1 - SMB_CLK_400K - 400 Khz
+  # 2 - SMB_CLK_700K - 700 Khz
+  # 3 - SMB_CLK_1M   - 1   Mhz
+  #
   gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault|0x2
 
 !if (($(CPUTARGET) == "ICX"))
diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
index c464343929..4b1de79adf 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
@@ -13,7 +13,7 @@
 UINT8  EnableSgx;                               ///< Enable SGX
 UINT8  SgxFactoryReset;                         ///< Delete all registration data, if SGX enabled force IPE/FirstBinding flow
 UINT64 PrmrrSize;                               ///< SGX PRMRR size
-UINT64 ReservedS239;
+UINT64 SprspOrLaterPrmSize;                     ///< SGX PRM size (SPR+ only)
 UINT8  SgxQoS;                                  ///< SGX Quality of Service
 UINT8  SgxAutoRegistrationAgent;                ///< SGX Auto Registration Agent
 UINT8  SgxPackageInfoInBandAccess;              ///< SGX Expose Package Info to OS
diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
index 45b63b21c5..1df00251d7 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
@@ -15,8 +15,8 @@ UINT64 ValidPrmrrBitMap;
 UINT64 SprspOrLaterPrmSizeBitmap;               // ## PRODUCED by SgxPreMemInit
 UINT8  ShowEpoch;
 UINT8  SkipSignalPpmDone;                       // ## PRODUCED by SgxEarlyInit
+UINT8  IsSmxCapable;                            // ## PRODUCED by SgxPreMemInit
 
-UINT8  SprspOrLaterIsPrmSizeInvalidated;        // ## PRODUCED by SgxPreMemInit
 UINT8  SprspOrLaterAreHardwarePreconditionsMet; // ## PRODUCED by SgxPreMemInit
 UINT8  SprspOrLaterAreMemoryPreconditionsMet;   // ## PRODUCED by SgxPreMeminit
 UINT8  SprspOrLaterAreSetupPreconditionsMet;    // ## PRODUCED by SgxPreMemInit
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index e03ee6d5d8..e010d65854 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -698,13 +698,6 @@ gPeiSmmControlPpiGuid  =  {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
 #
 # VTD PCDs Begin
 #
-  ## The mask is used to control VTd behavior.<BR><BR>
-  #  BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.)
-  #  BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)
-  #  BIT2: Force no IOMMU access attribute request recording before DMAR table is installed.
-  #  BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Protection
-  # @Prompt The policy for VTd driver behavior.
-  gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002
 
   ## Declares VTd PEI DMA buffer size.<BR><BR>
   #  When this PCD value is referred by platform to calculate the required
@@ -840,7 +833,7 @@ gPeiSmmControlPpiGuid  =  {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
   gSiPkgTokenSpaceGuid.PcdTempRefreshOption             |0|UINT8|0x7000000A
 
   # Temperature refresh value default, Values are in Celcius
-  gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue             |0x19|UINT8|0x70000001
+  gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue             |0x00|UINT8|0x70000001
   gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue              |0x53|UINT8|0x70000002
   gSiPkgTokenSpaceGuid.PcdFourxRefreshValue             |0x5F|UINT8|0x70000003
 
@@ -933,6 +926,8 @@ gPeiSmmControlPpiGuid  =  {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
 # VTD PCDs End
 #
 
+  gSiPkgTokenSpaceGuid.PcdPcieMultiVcEnable|FALSE|BOOLEAN|0xF0000038
+
 [PcdsDynamicEx]
   gReferenceCodePolicyTokenSpaceGuid.PcdEvMode         |0x00|UINT8|0x00010001
   # ReservedC: The Mailbox Command which it gona to assert.
@@ -958,12 +953,26 @@ gPeiSmmControlPpiGuid  =  {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
   #
   gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E
 
+  #
+  # RAS: PcdRasIerrPresent - TRUE: IERR has occured need reset; FALSE: No IERR
+  #
+  gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002
+
 [PcdsDynamicEx]
   gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007
   gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A
   gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D
   gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B
 
+##  Will be set if platform is WS else remains FALSE for Server platform.
+  gPlatformTokenSpaceGuid.PcdIsCPUWsType|FALSE|BOOLEAN|0x6000001A
+
+##  C2F
+##  Will be set if platform is resuming from a global reset after ADR trigger.
+  # C2F driver will read the PCD and determine whether to perform C2f Entry.
+  # @Prompt Provide status if Adr resume or not
+
+  gPlatformTokenSpaceGuid.PcdAdrResumeStatus|0|UINT8|0x0000104A
 ##
 ## ME
 ##
@@ -979,7 +988,6 @@ gPeiSmmControlPpiGuid  =  {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
 ## RAS
 ##
   gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001
-  gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002
 
 [PcdsFeatureFlag]
   ## This PCD used by FPGA drivers to decide to install FPGA features.
-- 
2.39.0.windows.1


  reply	other threads:[~2023-01-12 23:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-12 23:56 [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Isaac Oram
2023-01-12 23:56 ` Isaac Oram [this message]
2023-01-12 23:56 ` [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg: Update to Whitley FSP 4.2.0.2A Isaac Oram
2023-01-18  1:27 ` [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Nate DeSimone
2023-01-18 23:45   ` Isaac Oram

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