* FW: Question regarding CMOS regions. [not found] ` <cb259067389a48d88bac493203f1c71d@BLRX13MDC420.AMER.DELL.COM> @ 2018-08-14 3:47 ` MohammadYounasKhan.P 2018-08-16 4:44 ` MohammadYounasKhan.P 0 siblings, 1 reply; 5+ messages in thread From: MohammadYounasKhan.P @ 2018-08-14 3:47 UTC (permalink / raw) To: edk2-devel Hi All, As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored using IO ports 0x72-0x73. 1. How to know that the system has 128bytes of CMOS or 256 bytes of CMOS region? 2. Is there any CMOS location which represents CMOS upper region is exists or valid or any other mechanism for it? 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS location 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? Thank you, Younas. ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Question regarding CMOS regions. 2018-08-14 3:47 ` FW: Question regarding CMOS regions MohammadYounasKhan.P @ 2018-08-16 4:44 ` MohammadYounasKhan.P 2018-08-16 6:08 ` Ni, Ruiyu 0 siblings, 1 reply; 5+ messages in thread From: MohammadYounasKhan.P @ 2018-08-16 4:44 UTC (permalink / raw) To: edk2-devel Hi Guys, Please help to reply to my below queries. Thank you, Younas. -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Pathan, MohammadYounasKhan Sent: Tuesday, August 14, 2018 9:17 AM To: edk2-devel@lists.01.org Subject: [edk2] FW: Question regarding CMOS regions. Hi All, As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored using IO ports 0x72-0x73. 1. How to know that the system has 128bytes of CMOS or 256 bytes of CMOS region? 2. Is there any CMOS location which represents CMOS upper region is exists or valid or any other mechanism for it? 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS location 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? Thank you, Younas. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Question regarding CMOS regions. 2018-08-16 4:44 ` MohammadYounasKhan.P @ 2018-08-16 6:08 ` Ni, Ruiyu 2018-08-16 6:28 ` MohammadYounasKhan.P 0 siblings, 1 reply; 5+ messages in thread From: Ni, Ruiyu @ 2018-08-16 6:08 UTC (permalink / raw) To: MohammadYounasKhan.P@Dell.com, edk2-devel@lists.01.org Younas, Why are you still working on CMOS in now UEFI world? Detailed answer is in below. Thanks/Ray > -----Original Message----- > From: edk2-devel <edk2-devel-bounces@lists.01.org> On Behalf Of > MohammadYounasKhan.P@Dell.com > Sent: Thursday, August 16, 2018 12:44 PM > To: edk2-devel@lists.01.org > Subject: Re: [edk2] Question regarding CMOS regions. > > Hi Guys, > > Please help to reply to my below queries. > > Thank you, > Younas. > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Pathan, MohammadYounasKhan > Sent: Tuesday, August 14, 2018 9:17 AM > To: edk2-devel@lists.01.org > Subject: [edk2] FW: Question regarding CMOS regions. > > Hi All, > > As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are > stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored using IO > ports 0x72-0x73. > > 1. How to know that the system has 128bytes of CMOS or 256 bytes of CMOS > region? You could read the data to know whether high 128 bytes are valid or not. > 2. Is there any CMOS location which represents CMOS upper region is exists or > valid or any other mechanism for it? Refer to #1. > 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS location > 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? It depends on BIOS implementation. I don't see any bios is duplicating the contents. > > Thank you, > Younas. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Question regarding CMOS regions. 2018-08-16 6:08 ` Ni, Ruiyu @ 2018-08-16 6:28 ` MohammadYounasKhan.P 2018-08-16 6:59 ` Ramesh R. 0 siblings, 1 reply; 5+ messages in thread From: MohammadYounasKhan.P @ 2018-08-16 6:28 UTC (permalink / raw) To: ruiyu.ni, edk2-devel Thanks Ruiyu. I have some inconsistencies with CMOS regions. Even EDKII uses some CMOS regions. I have attached the CMOS dump took using RW tool below: Type:ISA Port 0070,0071 Width:01 00=56 01=17 02=45 03=17 04=11 05=15 06=04 07=16 08=08 09=18 0A=26 0B=02 0C=50 0D=80 0E=00 0F=00 10=00 11=00 12=00 13=00 14=00 15=7B 16=02 17=FF 18=FF 19=00 1A=00 1B=00 1C=00 1D=00 1E=00 1F=00 20=00 21=00 22=00 23=00 24=00 25=00 26=00 27=00 28=00 29=00 2A=00 2B=00 2C=00 2D=00 2E=02 2F=7B 30=FF 31=FF 32=20 33=00 34=00 35=9D 36=0B 37=00 38=00 39=00 3A=00 3B=00 3C=00 3D=00 3E=00 3F=00 40=00 41=00 42=CA 43=B8 44=6C 45=58 46=00 47=00 48=00 49=00 4A=00 4B=00 4C=00 4D=00 4E=00 4F=00 50=00 51=00 52=00 53=00 54=03 55=00 56=00 57=00 58=00 59=00 5A=00 5B=00 5C=00 5D=00 5E=00 5F=00 60=00 61=00 62=00 63=00 64=00 65=00 66=00 67=00 68=00 69=00 6A=00 6B=00 6C=01 6D=00 6E=00 6F=A5 70=00 71=00 72=00 73=00 74=00 75=00 76=00 77=00 78=00 79=5F 7A=00 7B=00 7C=00 7D=00 7E=00 7F=00 80=56 81=17 82=45 83=17 84=11 85=15 86=04 87=16 88=08 89=18 8A=26 8B=02 8C=40 8D=80 8E=00 8F=00 90=00 91=00 92=00 93=00 94=00 95=7B 96=02 97=FF 98=FF 99=00 9A=00 9B=00 9C=00 9D=00 9E=00 9F=00 A0=00 A1=00 A2=00 A3=00 A4=00 A5=00 A6=00 A7=00 A8=00 A9=00 AA=00 AB=00 AC=00 AD=00 AE=02 AF=7B B0=FF B1=FF B2=20 B3=00 B4=00 B5=9D B6=0B B7=00 B8=00 B9=00 BA=00 BB=00 BC=00 BD=00 BE=00 BF=00 C0=00 C1=00 C2=CA C3=B8 C4=6C C5=58 C6=00 C7=00 C8=00 C9=00 CA=00 CB=00 CC=00 CD=00 CE=00 CF=00 D0=00 D1=00 D2=00 D3=00 D4=03 D5=00 D6=00 D7=00 D8=00 D9=00 DA=00 DB=00 DC=00 DD=00 DE=00 DF=00 E0=00 E1=00 E2=00 E3=00 E4=00 E5=00 E6=00 E7=00 E8=00 E9=00 EA=00 EB=00 EC=01 ED=00 EE=00 EF=A5 F0=00 F1=00 F2=00 F3=00 F4=00 F5=00 F6=00 F7=00 F8=00 F9=5F FA=00 FB=00 FC=00 FD=00 FE=00 FF=00 I have update my queries below. Thank you, Younas. -----Original Message----- From: Ni, Ruiyu [mailto:ruiyu.ni@intel.com] Sent: Thursday, August 16, 2018 11:38 AM To: Pathan, MohammadYounasKhan; edk2-devel@lists.01.org Subject: RE: Question regarding CMOS regions. Younas, Why are you still working on CMOS in now UEFI world? Detailed answer is in below. Thanks/Ray > -----Original Message----- > From: edk2-devel <edk2-devel-bounces@lists.01.org> On Behalf Of > MohammadYounasKhan.P@Dell.com > Sent: Thursday, August 16, 2018 12:44 PM > To: edk2-devel@lists.01.org > Subject: Re: [edk2] Question regarding CMOS regions. > > Hi Guys, > > Please help to reply to my below queries. > > Thank you, > Younas. > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Pathan, MohammadYounasKhan > Sent: Tuesday, August 14, 2018 9:17 AM > To: edk2-devel@lists.01.org > Subject: [edk2] FW: Question regarding CMOS regions. > > Hi All, > > As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are > stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored > using IO ports 0x72-0x73. > > 1. How to know that the system has 128bytes of CMOS or 256 bytes of > CMOS region? You could read the data to know whether high 128 bytes are valid or not. [Younas]: How to check the validity of data? > 2. Is there any CMOS location which represents CMOS upper region is > exists or valid or any other mechanism for it? Refer to #1. [Younas]: CMOS upper region means port 0x72-0x73. Each IO port can store 256 bytes of data (0x00-0xFF). Default lower CMOS region has date and time and is valid always. But for upper CMOS region, I am not sure how to check whether it is valid or not? > 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS > location > 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? It depends on BIOS implementation. I don't see any bios is duplicating the contents. [Younas]: You can refer to my CMOS dump copied above which shows upper 128bytes have same information as lower 128bytes (of port 0x70-0x71). I would like to know why we are doing this? > > Thank you, > Younas. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Question regarding CMOS regions. 2018-08-16 6:28 ` MohammadYounasKhan.P @ 2018-08-16 6:59 ` Ramesh R. 0 siblings, 0 replies; 5+ messages in thread From: Ramesh R. @ 2018-08-16 6:59 UTC (permalink / raw) To: MohammadYounasKhan.P@Dell.com, ruiyu.ni@intel.com, edk2-devel@lists.01.org 1) To check the Extended RAM validity. * Read the Offset 0 from Extended RTC Ram. * If no 0 value, extended RTC Ram is present. * If it's 0xFF, write some value to Offset 0 * Read it back. If you get the value that you wrote, extended RTC RAM is present and preserve the old value again. * If you still get 0xFF, Extended RTC RAM is not present. 2) Extended RTC RAM is NOT duplicate of standard RTC RAM. It's up to BIOS vendor how they use it. May be BIOS uses the extended RTC RAM as duplicate copy of the standard RTC RAM. Check the "Real Time Clock Registers" Section in the SB Spec. Thanks, Ramesh -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of MohammadYounasKhan.P@Dell.com Sent: 16 August 2018 11:59 To: ruiyu.ni@intel.com; edk2-devel@lists.01.org Subject: Re: [edk2] Question regarding CMOS regions. Thanks Ruiyu. I have some inconsistencies with CMOS regions. Even EDKII uses some CMOS regions. I have attached the CMOS dump took using RW tool below: Type:ISA Port 0070,0071 Width:01 00=56 01=17 02=45 03=17 04=11 05=15 06=04 07=16 08=08 09=18 0A=26 0B=02 0C=50 0D=80 0E=00 0F=00 10=00 11=00 12=00 13=00 14=00 15=7B 16=02 17=FF 18=FF 19=00 1A=00 1B=00 1C=00 1D=00 1E=00 1F=00 20=00 21=00 22=00 23=00 24=00 25=00 26=00 27=00 28=00 29=00 2A=00 2B=00 2C=00 2D=00 2E=02 2F=7B 30=FF 31=FF 32=20 33=00 34=00 35=9D 36=0B 37=00 38=00 39=00 3A=00 3B=00 3C=00 3D=00 3E=00 3F=00 40=00 41=00 42=CA 43=B8 44=6C 45=58 46=00 47=00 48=00 49=00 4A=00 4B=00 4C=00 4D=00 4E=00 4F=00 50=00 51=00 52=00 53=00 54=03 55=00 56=00 57=00 58=00 59=00 5A=00 5B=00 5C=00 5D=00 5E=00 5F=00 60=00 61=00 62=00 63=00 64=00 65=00 66=00 67=00 68=00 69=00 6A=00 6B=00 6C=01 6D=00 6E=00 6F=A5 70=00 71=00 72=00 73=00 74=00 75=00 76=00 77=00 78=00 79=5F 7A=00 7B=00 7C=00 7D=00 7E=00 7F=00 80=56 81=17 82=45 83=17 84=11 85=15 86=04 87=16 88=08 89=18 8A=26 8B=02 8C=40 8D=80 8E=00 8F=00 90=00 91=00 92=00 93=00 94=00 95=7B 96=02 97=FF 98=FF 99=00 9A=00 9B=00 9C=00 9D=00 9E=00 9F=00 A0=00 A1=00 A2=00 A3=00 A4=00 A5=00 A6=00 A7=00 A8=00 A9=00 AA=00 AB=00 AC=00 AD=00 AE=02 AF=7B B0=FF B1=FF B2=20 B3=00 B4=00 B5=9D B6=0B B7=00 B8=00 B9=00 BA=00 BB=00 BC=00 BD=00 BE=00 BF=00 C0=00 C1=00 C2=CA C3=B8 C4=6C C5=58 C6=00 C7=00 C8=00 C9=00 CA=00 CB=00 CC=00 CD=00 CE=00 CF=00 D0=00 D1=00 D2=00 D3=00 D4=03 D5=00 D6=00 D7=00 D8=00 D9=00 DA=00 DB=00 DC=00 DD=00 DE=00 DF=00 E0=00 E1=00 E2=00 E3=00 E4=00 E5=00 E6=00 E7=00 E8=00 E9=00 EA=00 EB=00 EC=01 ED=00 EE=00 EF=A5 F0=00 F1=00 F2=00 F3=00 F4=00 F5=00 F6=00 F7=00 F8=00 F9=5F FA=00 FB=00 FC=00 FD=00 FE=00 FF=00 I have update my queries below. Thank you, Younas. -----Original Message----- From: Ni, Ruiyu [mailto:ruiyu.ni@intel.com] Sent: Thursday, August 16, 2018 11:38 AM To: Pathan, MohammadYounasKhan; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> Subject: RE: Question regarding CMOS regions. Younas, Why are you still working on CMOS in now UEFI world? Detailed answer is in below. Thanks/Ray > -----Original Message----- > From: edk2-devel <edk2-devel-bounces@lists.01.org<mailto:edk2-devel-bounces@lists.01.org>> On Behalf Of > MohammadYounasKhan.P@Dell.com<mailto:MohammadYounasKhan.P@Dell.com> > Sent: Thursday, August 16, 2018 12:44 PM > To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> > Subject: Re: [edk2] Question regarding CMOS regions. > > Hi Guys, > > Please help to reply to my below queries. > > Thank you, > Younas. > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Pathan, MohammadYounasKhan > Sent: Tuesday, August 14, 2018 9:17 AM > To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> > Subject: [edk2] FW: Question regarding CMOS regions. > > Hi All, > > As we know CMOS data can be 128 or 256 bytes. CMOS lower 128 bytes are > stored in IO ports 0x70-0x71 whereas CMOS upper 128 bytes are stored > using IO ports 0x72-0x73. > > 1. How to know that the system has 128bytes of CMOS or 256 bytes of > CMOS region? You could read the data to know whether high 128 bytes are valid or not. [Younas]: How to check the validity of data? > 2. Is there any CMOS location which represents CMOS upper region is > exists or valid or any other mechanism for it? Refer to #1. [Younas]: CMOS upper region means port 0x72-0x73. Each IO port can store 256 bytes of data (0x00-0xFF). Default lower CMOS region has date and time and is valid always. But for upper CMOS region, I am not sure how to check whether it is valid or not? > 3. Are we replicating lower 128 bytes to upper 128 bytes in CMOS > location > 0x70-0x71 (or 0x72-0x73)? If yes, Why are we doing that? It depends on BIOS implementation. I don't see any bios is duplicating the contents. [Younas]: You can refer to my CMOS dump copied above which shows upper 128bytes have same information as lower 128bytes (of port 0x70-0x71). I would like to know why we are doing this? > > Thank you, > Younas. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org> https://lists.01.org/mailman/listinfo/edk2-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
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2018-08-14 3:47 ` FW: Question regarding CMOS regions MohammadYounasKhan.P
2018-08-16 4:44 ` MohammadYounasKhan.P
2018-08-16 6:08 ` Ni, Ruiyu
2018-08-16 6:28 ` MohammadYounasKhan.P
2018-08-16 6:59 ` Ramesh R.
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