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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=amd.com; Received: from DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) by DM5PR12MB1193.namprd12.prod.outlook.com (2603:10b6:3:70::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.22; Fri, 5 Jun 2020 17:58:59 +0000 Received: from DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::4ce1:9947:9681:c8b1]) by DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::4ce1:9947:9681:c8b1%10]) with mapi id 15.20.3066.019; Fri, 5 Jun 2020 17:58:59 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Subject: [PATCH v9 40/46] UefiCpuPkg: Add a 16-bit protected mode code segment descriptor Date: Fri, 5 Jun 2020 12:58:41 -0500 Message-Id: X-Mailer: git-send-email 2.27.0 In-Reply-To: References: X-ClientProxiedBy: DM5PR20CA0008.namprd20.prod.outlook.com (2603:10b6:3:93::18) To DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR20CA0008.namprd20.prod.outlook.com (2603:10b6:3:93::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.18 via Frontend Transport; Fri, 5 Jun 2020 17:58:58 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 902c1035-fcc0-4a5a-1c01-08d8097a1f0e X-MS-TrafficTypeDiagnostic: DM5PR12MB1193: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 0425A67DEF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wLUmGf0yXreVCraOuC7d3sp00afjth540gkpNUkCF+5bU+gOJSPeLUX1lDQ6Fk/1IxQJhyIUbgp26WdILx8hAm4bKCUK8zG1EVT1r3QXAeMqjAetROe6aXAX23ACWgdNK2VeT3f8UfEA7y6Wl++yQQo0NOvCjTFtjcnewRD2aMN4BrKRyZlxUZMTlAiI26CnEeCOkLikO/IvZFM/AQof267bc574t4V0LpUYMHivpOIahN5lBaOU1+iFWqtkMd4YrzfxCmrVzbq0sHqOLg/oHMNXMwcd0Fpo5gYDVnsMv8TUzmHEGKtoSs0LloOimcACrBEcGmMgVb5rVt+vY3A3lMy14RByYPvG5WNh/LcIcL2FxMAyVwjzz3AacpL/vvaTmfaxwA9gXqgUpAEls8R85H3djPsnYQMv16Cx9OILnQ0PliDTukzPYjVJiTwhzVXmszydMcdN53TZ/AnkW/6Jnw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM5PR12MB1355.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(4636009)(136003)(396003)(376002)(346002)(366004)(39860400002)(2906002)(36756003)(52116002)(7696005)(83380400001)(16526019)(5660300002)(26005)(6916009)(186003)(966005)(478600001)(6666004)(66476007)(66556008)(6486002)(8936002)(66946007)(8676002)(956004)(86362001)(316002)(2616005)(136400200001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 4iAZ5mlhNiWcwSxwmj4GijnNJ/KI4dvF4jVyVJAkIZr4VOHGLhevMLOxTZD0BWL9kZq+/9wCE33ydtZbGt3WZdL5/MzjyA0OzgKjBzJETUoLpsxRZfHQYMBmmGF2NKDmVfQwpn4c3YK0YfBBZ5FlZtWDEOObeGGy0IrnV0zRpMIFceG0uWRd2l3AIIspxvmOPKRnwiv3bYlCaJSChb//Y0M+hjIB6NsS+PHn9ezje1xraSNRMDfPD1xhpYIcKd1CQ4hYdApna1AEP4XoUZo0JJ/DHy4ByAYpz++wCjghfhUbVYrR5R9KpzDAC/IEfuqpYx5D55IfmNStbSvu+AQYJ+c6KJXk3+bc5nnOJO7Gz8ZkWwoyIcGpQ2Y198hIh515yd+USHXpAQVuH6vCgIElRzbwkLX3rKUwXDUmdX8ip268XJOiBN2qdc9lJ+wgMCLCEpLPkWzkmLC3Dji8Ciy0gPiL6XCH66pvgzJ3pOgeydA= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 902c1035-fcc0-4a5a-1c01-08d8097a1f0e X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2020 17:58:59.1000 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: REoofZrWhJrA7EJIWV3/nhqr89IeSu75kG+WAR19weNW4Un5grb7XkU/+qODdHHfVYOfFKTrSEW7lpw80ohZcw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1193 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 3a0210b2f172..1c94487cbee8 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode;=0D GDT_ENTRY SysData;=0D GDT_ENTRY SysCode;=0D - GDT_ENTRY Spare4;=0D + GDT_ENTRY SysCode16;=0D GDT_ENTRY LinearData64;=0D GDT_ENTRY LinearCode64;=0D GDT_ENTRY Spare5;=0D @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)=0D #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)=0D #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)=0D -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4)=0D +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16)=0D #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64)=0D #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)=0D #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)=0D diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 64efadeba601..a1ab543f2da5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate =3D { 0x0,=0D },=0D //=0D - // SPARE4_SEL=0D + // SYS_CODE16_SEL=0D //=0D {=0D - 0x0, // limit 15:0=0D + 0x0FFFF, // limit 15:0=0D 0x0, // base 15:0=0D 0x0, // base 23:16=0D - 0x0, // type=0D - 0x0, // limit 19:16, flags=0D + 0x09A, // present, ring 0, code, execute/read=0D + 0x08F, // page-granular, 16-bit=0D 0x0, // base 31:24=0D },=0D //=0D diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuP= kg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24=0D %endif=0D =0D +; linear code segment descriptor=0D +LINEAR_CODE16_SEL equ $-GDT_BASE=0D + DW 0xffff ; limit 15:0=0D + DW 0 ; base 15:0=0D + DB 0 ; base 23:16=0D + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)=0D + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIM= IT(0xf)=0D + DB 0 ; base 31:24=0D +=0D GDT_END:=0D =0D --=20 2.27.0