From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A15582034714E for ; Thu, 19 Oct 2017 01:04:27 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7AA0DB167; Thu, 19 Oct 2017 08:08:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7AA0DB167 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-85.rdu2.redhat.com [10.10.120.85]) by smtp.corp.redhat.com (Postfix) with ESMTP id 25E901915F; Thu, 19 Oct 2017 08:08:02 +0000 (UTC) To: Eric Dong , edk2-devel@lists.01.org Cc: Ruiyu Ni , Crystal Lee References: <1508380936-8608-1-git-send-email-eric.dong@intel.com> From: Laszlo Ersek Message-ID: Date: Thu, 19 Oct 2017 10:08:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <1508380936-8608-1-git-send-email-eric.dong@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Thu, 19 Oct 2017 08:08:04 +0000 (UTC) Subject: Re: [Patch] UefiCpuPkg/MpInitLib: Avoid call PcdGe* in Ap & Bsp. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Oct 2017 08:04:27 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 10/19/17 04:42, Eric Dong wrote: > MicrocodeDetect function will run by every threads, and it will > use PcdGet to get PcdCpuMicrocodePatchAddress and > PcdCpuMicrocodePatchRegionSize, if change both PCD default to dynamic, > system will in non-deterministic behavior. > > By design, UEFI/PI services are single threaded and not re-entrant > so Multi processor code should not use UEFI/PI services. Here, Pcd > protocol/PPI is used to access dynamic PCDs so it would result in > non-deterministic behavior. > > This code get PCD value in BSP and save them in CPU_MP_DATA for Ap. > > https://bugzilla.tianocore.org/show_bug.cgi?id=726 > > Cc: Crystal Lee > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > --- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 10 +++------- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 ++ > UefiCpuPkg/Library/MpInitLib/MpLib.h | 2 ++ > 3 files changed, 7 insertions(+), 7 deletions(-) Eric, can you please fix up the subject line after you get an R-b and are about to push the patch? -UefiCpuPkg/MpInitLib: Avoid call PcdGe* in Ap & Bsp. +UefiCpuPkg/MpInitLib: Avoid call PcdGet* in Ap & Bsp. Thanks! Laszlo > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c > index 982995b..35f66f7 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -42,8 +42,6 @@ MicrocodeDetect ( > IN CPU_MP_DATA *CpuMpData > ) > { > - UINT64 MicrocodePatchAddress; > - UINT64 MicrocodePatchRegionSize; > UINT32 ExtendedTableLength; > UINT32 ExtendedTableCount; > CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; > @@ -61,9 +59,7 @@ MicrocodeDetect ( > VOID *MicrocodeData; > MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; > > - MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress); > - MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize); > - if (MicrocodePatchRegionSize == 0) { > + if (CpuMpData->MicrocodePatchRegionSize == 0) { > // > // There is no microcode patches > // > @@ -93,8 +89,8 @@ MicrocodeDetect ( > > LatestRevision = 0; > MicrocodeData = NULL; > - MicrocodeEnd = (UINTN) (MicrocodePatchAddress + MicrocodePatchRegionSize); > - MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchAddress; > + MicrocodeEnd = (UINTN) (CpuMpData->MicrocodePatchAddress + CpuMpData->MicrocodePatchRegionSize); > + MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; > do { > // > // Check if the microcode is for the Cpu and the version is newer > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index 924b909..f3ee6d4 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -1458,6 +1458,8 @@ MpInitLibInitialize ( > CpuMpData->SwitchBspFlag = FALSE; > CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1); > CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber); > + CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress); > + CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize); > InitializeSpinLock(&CpuMpData->MpLock); > // > // Save BSP's Control registers to APs > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 19defda..84ae24f 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -233,6 +233,8 @@ struct _CPU_MP_DATA { > UINT8 Vector; > BOOLEAN PeriodicMode; > BOOLEAN TimerInterruptState; > + UINT64 MicrocodePatchAddress; > + UINT64 MicrocodePatchRegionSize; > }; > > extern EFI_GUID mCpuInitMpLibHobGuid; >