[edk2-devel] question about PCI bridge's bus range window configure's save and restore

["Tiger Liu(BJ-RD)" <tigerliu@zhaoxin.com>]

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Hi, Experts:
I have a question about PCI Bridge’s config space’s save and restore.

Pci bus driver configured PCI Bridges’ secondary bus number register and subordinate bus number register.

So, if system resumes from S3(Suspend to ram) state, who is responsible for restoring PCI Bridges’ secondary bus number / subordinate bus number registers’ content?

Will the OS be responsible for it?

Thanks



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