From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 57A477803CC for ; Sat, 16 Sep 2023 16:00:35 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=qB/7W6B7OvZ48NFGV8w5TP38fLnaEGC25xIttCDdlXE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1694880034; v=1; b=PdAGR8+rbhARSqdf3BDg/13tLJGxX6juTscgGBlpwifkmsh2xOzIJmzB6VkGrhrZRxpuuBhw zvDz3xflUu+FOFVwU/3xvyt1lTO6p7OTtK/2qm2kyNYrA5jybBJEfu7purlNCAoJxILnBfZb52b XqdXrjZ00w8gdeFF20sk1k/A= X-Received: by 127.0.0.2 with SMTP id klcFYY7687511xlnfi8zhywa; Sat, 16 Sep 2023 09:00:34 -0700 X-Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.220]) by mx.groups.io with SMTP id smtpd.web11.14364.1694880032863427967 for ; Sat, 16 Sep 2023 09:00:33 -0700 X-Received: from rv-uefi.. (unknown [211.87.236.31]) by zwqz-smtp-mta-g1-4 (Coremail) with SMTP id _____wCnYzsW0QVlszHTCA--.455S2; Sun, 17 Sep 2023 00:00:23 +0800 (CST) From: caiyuqing_hz@163.com To: devel@edk2.groups.io Cc: Sunil V L , Leif Lindholm , Michael D Kinney , USER0FISH , Inochi Amaoto Subject: [edk2-devel] [PATCH edk2-platforms v4 2/8] Sophgo/SG2042Pkg: Add PlatformUpdateMmuDxe module. Date: Sun, 17 Sep 2023 00:00:22 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 X-CM-TRANSID: _____wCnYzsW0QVlszHTCA--.455S2 X-Coremail-Antispam: 1Uf129KBjvAXoW3tFW3WFWDuF4kKr1rKFy8Zrb_yoW8WFy5Go ZrtF4rKws5WwsxurWxGrs7G3yIgFyvgw4rX3Z0qFyjg3Z5Cw4ruw10ka13Gw1Svw17AFZ8 GryxXa4xAFWfur95n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxUcD73DUUUU X-Originating-IP: [211.87.236.31] X-CM-SenderInfo: 5fdl535tlqwslk26il2tof0z/1tbiWB7sxWNftoy2WQAAsG Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,caiyuqing_hz@163.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: shne6tMnquWa8DI5yvOJNLQTx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=PdAGR8+r; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=163.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: caiyuqing379 SG2042 (Xuantie C920) MMU can be enabled in SV39 mode. C920 has five customizable page properties that control whether the page is Strong order(SO), Cacheable(C), Bufferable(B), Shareable(SH), Trustable(Sec). This driver modifies the page table attributes to avoid exceptions based on the memory attributes of the C920. Introduces a PCD variable PcdForceNoMMU to disable MMU configuration. Currently, enabling MMU results in a timeout for reading data blocks from the SD card. Signed-off-by: caiyuqing379 Co-authored-by: USER0FISH Cc: dahogn Cc: meng-cz Cc: yli147 Cc: ChaiEvan Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney --- .../PlatformUpdateMmuDxe.inf | 34 + .../PlatformUpdateMmuDxe.c | 593 ++++++++++++++++++ 2 files changed, 627 insertions(+) create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c diff --git a/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf b/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf new file mode 100644 index 000000000000..42000b0e267a --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf @@ -0,0 +1,34 @@ +## @file +# This driver modifies the page table attribute based on the memory attribute of the C920. +# +# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PlatformUpdateMmuDxe + FILE_GUID = 9d1dd27f-6d7f-427b-aec4-b62f6279c2f1 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformUpdateMmu + +[Sources] + PlatformUpdateMmuDxe.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec + +[LibraryClasses] + BaseLib + UefiLib + UefiDriverEntryPoint + RiscVMmuLib + DxeServicesTableLib + +[FixedPcd] + gSophgoSG2042PlatformPkgTokenSpaceGuid.PcdForceNoMMU ## CONSUMES diff --git a/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c b/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c new file mode 100644 index 000000000000..55be8f9e12ad --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c @@ -0,0 +1,593 @@ +/** @file + This driver modifies the page table attribute based on the memory attribute of the C920. + C920 has five customizable page properties that control whether the page is Strong order, + Cacheable, Bufferable, Shareable,Trustable. + + Copyright (c) 2011-2020, ARM Limited. All rights reserved. + Copyright (c) 2016, Linaro Limited. All rights reserved. + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universiy, China.P.R. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RISCV_PG_V BIT0 +#define RISCV_PG_R BIT1 +#define RISCV_PG_W BIT2 +#define RISCV_PG_X BIT3 +#define RISCV_PG_G BIT5 +#define RISCV_PG_A BIT6 +#define RISCV_PG_D BIT7 +#define RISCV_PG_SH BIT60 +#define RISCV_PG_B BIT61 +#define RISCV_PG_C BIT62 +#define RISCV_PG_SO BIT63 +#define PTE_ATTRIBUTES_MASK 0xE + +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL +#define PTE_PPN_SHIFT 10 +#define RISCV_MMU_PAGE_SHIFT 12 + +STATIC UINTN mMaxRootTableLevel; +STATIC UINTN mBitPerLevel; +STATIC UINTN mTableEntryCount; + +/** + Determine if the MMU enabled or not. + + @retval TRUE The MMU already enabled. + @retval FALSE The MMU not enabled. + +**/ +STATIC +VOID +RiscVMmuDisabled ( + VOID + ) +{ + RiscVSetSupervisorAddressTranslationRegister (SATP_MODE_OFF << SATP64_MODE_SHIFT); +} + +/** + Determine if the MMU enabled or not. + + @retval TRUE The MMU already enabled. + @retval FALSE The MMU not enabled. + +**/ +STATIC +BOOLEAN +RiscVMmuEnabled ( + VOID + ) +{ + return ((RiscVGetSupervisorAddressTranslationRegister () & + SATP64_MODE) != (SATP_MODE_OFF << SATP64_MODE_SHIFT)); +} + +/** + Retrieve the root translate table. + + @return The root translate table. + +**/ +STATIC +UINTN +RiscVGetRootTranslateTable ( + VOID + ) +{ + return (RiscVGetSupervisorAddressTranslationRegister () & SATP64_PPN) << + RISCV_MMU_PAGE_SHIFT; +} + +/** + Determine if an entry is valid pte. + + @param Entry The entry value. + + @retval TRUE The entry is a valid pte. + @retval FALSE The entry is not a valid pte. + +**/ +STATIC +BOOLEAN +IsValidPte ( + IN UINTN Entry + ) +{ + if (((Entry & RISCV_PG_V) == 0) || + (((Entry & (RISCV_PG_R | RISCV_PG_W)) == RISCV_PG_W))) + { + return FALSE; + } + + return TRUE; +} + +/** + Set an entry to be a valid pte. + + @param Entry The entry value. + + @return The entry value. + +**/ +STATIC +UINTN +SetValidPte ( + IN UINTN Entry + ) +{ + /* Set Valid and Global mapping bits */ + return Entry | RISCV_PG_G | RISCV_PG_V; +} + +/** + Determine if an entry is a block pte. + + @param Entry The entry value. + + @retval TRUE The entry is a block pte. + @retval FALSE The entry is not a block pte. + +**/ +STATIC +BOOLEAN +IsBlockEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + (Entry & (RISCV_PG_X | RISCV_PG_R)); +} + +/** + Determine if an entry is a table pte. + + @param Entry The entry value. + + @retval TRUE The entry is a table pte. + @retval FALSE The entry is not a table pte. + +**/ +STATIC +BOOLEAN +IsTableEntry ( + IN UINTN Entry + ) +{ + return IsValidPte (Entry) && + !IsBlockEntry (Entry); +} + +/** + Set an entry to be a table pte. + + @param Entry The entry value. + + @return The entry value. + +**/ +STATIC +UINTN +SetTableEntry ( + IN UINTN Entry + ) +{ + Entry = SetValidPte (Entry); + Entry &= ~(RISCV_PG_X | RISCV_PG_W | RISCV_PG_R); + + return Entry; +} + +/** + Replace an existing entry with new value. + + @param Entry The entry pointer. + @param Value The new entry value. + @param RegionStart The start of region that new value affects. + @param IsLiveBlockMapping TRUE if this is live update, FALSE otherwise. + +**/ +STATIC +VOID +ReplaceTableEntry ( + IN UINTN *Entry, + IN UINTN Value, + IN UINTN RegionStart, + IN BOOLEAN IsLiveBlockMapping + ) +{ + *Entry = Value; + + if (IsLiveBlockMapping && RiscVMmuEnabled ()) { + RiscVLocalTlbFlush (RegionStart); + } +} + +/** + Get an ppn value from an entry. + + @param Entry The entry value. + + @return The ppn value. + +**/ +STATIC +UINTN +GetPpnfromPte ( + IN UINTN Entry + ) +{ + return ((Entry & PTE_PPN_MASK) >> PTE_PPN_SHIFT); +} + +/** + Set an ppn value to a entry. + + @param Entry The entry value. + @param Address The address. + + @return The new entry value. + +**/ +STATIC +UINTN +SetPpnToPte ( + UINTN Entry, + UINTN Address + ) +{ + UINTN Ppn; + + Ppn = ((Address >> RISCV_MMU_PAGE_SHIFT) << PTE_PPN_SHIFT); + ASSERT (~(Ppn & ~PTE_PPN_MASK)); + Entry &= ~PTE_PPN_MASK; + return Entry | Ppn; +} + +/** + Free resources of translation table recursively. + + @param TranslationTable The pointer of table. + @param Level The current level. + +**/ +STATIC +VOID +FreePageTablesRecursive ( + IN UINTN *TranslationTable, + IN UINTN Level + ) +{ + UINTN Index; + + if (Level < mMaxRootTableLevel - 1) { + for (Index = 0; Index < mTableEntryCount; Index++) { + if (IsTableEntry (TranslationTable[Index])) { + FreePageTablesRecursive ( + (UINTN *)(GetPpnfromPte ((TranslationTable[Index])) << + RISCV_MMU_PAGE_SHIFT), + Level + 1 + ); + } + } + } + + FreePages (TranslationTable, 1); +} + +/** + Update region mapping recursively. + + @param RegionStart The start address of the region. + @param RegionEnd The end address of the region. + @param AttributeSetMask The attribute mask to be set. + @param AttributeClearMask The attribute mask to be clear. + @param PageTable The pointer of current page table. + @param Level The current level. + @param TableIsLive TRUE if this is live update, FALSE otherwise. + + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +STATIC +EFI_STATUS +UpdateRegionMappingRecursive ( + IN UINTN RegionStart, + IN UINTN RegionEnd, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *PageTable, + IN UINTN Level, + IN BOOLEAN TableIsLive + ) +{ + EFI_STATUS Status; + UINTN BlockShift; + UINTN BlockMask; + UINTN BlockEnd; + UINTN *Entry; + UINTN EntryValue; + UINTN *TranslationTable; + BOOLEAN NextTableIsLive; + + ASSERT (Level < mMaxRootTableLevel); + ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0); + + BlockShift = (mMaxRootTableLevel - Level - 1) * mBitPerLevel + RISCV_MMU_PAGE_SHIFT; + BlockMask = MAX_ADDRESS >> (64 - BlockShift); + + DEBUG ( + ( + DEBUG_VERBOSE, + "%a(%d): %llx - %llx set %lx clr %lx\n", + __func__, + Level, + RegionStart, + RegionEnd, + AttributeSetMask, + AttributeClearMask + ) + ); + + for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) { + BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1); + Entry = &PageTable[(RegionStart >> BlockShift) & (mTableEntryCount - 1)]; + + // + // If RegionStart or BlockEnd is not aligned to the block size at this + // level, we will have to create a table mapping in order to map less + // than a block, and recurse to create the block or page entries at + // the next level. No block mappings are allowed at all at level 0, + // so in that case, we have to recurse unconditionally. + // + if ((Level == 0) || + (((RegionStart | BlockEnd) & BlockMask) != 0) || IsTableEntry (*Entry)) + { + ASSERT (Level < mMaxRootTableLevel - 1); + if (!IsTableEntry (*Entry)) { + // + // No table entry exists yet, so we need to allocate a page table + // for the next level. + // + TranslationTable = AllocatePages (1); + if (TranslationTable == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (TranslationTable, EFI_PAGE_SIZE); + + if (IsBlockEntry (*Entry)) { + // + // We are splitting an existing block entry, so we have to populate + // the new table with the attributes of the block entry it replaces. + // + Status = UpdateRegionMappingRecursive ( + RegionStart & ~BlockMask, + (RegionStart | BlockMask) + 1, + *Entry & PTE_ATTRIBUTES_MASK, + PTE_ATTRIBUTES_MASK, + TranslationTable, + Level + 1, + FALSE + ); + if (EFI_ERROR (Status)) { + // + // The range we passed to UpdateRegionMappingRecursive () is block + // aligned, so it is guaranteed that no further pages were allocated + // by it, and so we only have to free the page we allocated here. + // + FreePages (TranslationTable, 1); + return Status; + } + } + + NextTableIsLive = FALSE; + } else { + TranslationTable = (UINTN *)(GetPpnfromPte (*Entry) << RISCV_MMU_PAGE_SHIFT); + NextTableIsLive = TableIsLive; + } + + // + // Recurse to the next level + // + Status = UpdateRegionMappingRecursive ( + RegionStart, + BlockEnd, + AttributeSetMask, + AttributeClearMask, + TranslationTable, + Level + 1, + NextTableIsLive + ); + if (EFI_ERROR (Status)) { + if (!IsTableEntry (*Entry)) { + // + // We are creating a new table entry, so on failure, we can free all + // allocations we made recursively, given that the whole subhierarchy + // has not been wired into the live page tables yet. (This is not + // possible for existing table entries, since we cannot revert the + // modifications we made to the subhierarchy it represents.) + // + FreePageTablesRecursive (TranslationTable, Level + 1); + } + + return Status; + } + + if (!IsTableEntry (*Entry)) { + EntryValue = SetPpnToPte (0, (UINTN)TranslationTable); + EntryValue = SetTableEntry (EntryValue); + ReplaceTableEntry ( + Entry, + EntryValue, + RegionStart, + TableIsLive + ); + } + } else { + EntryValue = (*Entry & ~AttributeClearMask) | AttributeSetMask; + // + // We don't have page fault exception handler when a virtual page is accessed and + // the A bit is clear, or is written and the D bit is clear. + // So just set A for read and D for write permission. + // + if ((AttributeSetMask & RISCV_PG_R) != 0) { + EntryValue |= RISCV_PG_A; + } + + if ((AttributeSetMask & RISCV_PG_W) != 0) { + EntryValue |= RISCV_PG_D; + } + + EntryValue = SetPpnToPte (EntryValue, RegionStart); + EntryValue = SetValidPte (EntryValue); + ReplaceTableEntry (Entry, EntryValue, RegionStart, TableIsLive); + } + } + + return EFI_SUCCESS; +} + +/** + Update region mapping at root table. + + @param RegionStart The start address of the region. + @param RegionLength The length of the region. + @param AttributeSetMask The attribute mask to be set. + @param AttributeClearMask The attribute mask to be clear. + @param RootTable The pointer of root table. + @param TableIsLive TRUE if this is live update, FALSE otherwise. + + @retval EFI_INVALID_PARAMETER The RegionStart or RegionLength was not valid. + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +STATIC +EFI_STATUS +UpdateRegionMapping ( + IN UINTN RegionStart, + IN UINTN RegionLength, + IN UINTN AttributeSetMask, + IN UINTN AttributeClearMask, + IN UINTN *RootTable, + IN BOOLEAN TableIsLive + ) +{ + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) { + return EFI_INVALID_PARAMETER; + } + + return UpdateRegionMappingRecursive ( + RegionStart, + RegionStart + RegionLength, + AttributeSetMask, + AttributeClearMask, + RootTable, + 0, + TableIsLive + ); +} + +/** + The API to configure and enable RISC-V MMU with the highest mode supported. + + @retval EFI_OUT_OF_RESOURCES Not enough resource. + @retval EFI_SUCCESS The operation succesfully. + +**/ +EFI_STATUS +EFIAPI +PlatformUpdateMmu ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemoryMap; + UINTN NumberOfDescriptors; + UINTN Index; + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + if(RiscVMmuEnabled () && PcdGetBool (PcdForceNoMMU)){ + + FreePageTablesRecursive ((UINTN *)RiscVGetRootTranslateTable (), 0); + + RiscVMmuDisabled (); + DEBUG (( + DEBUG_INFO, + "%a: SG2042 MMU disabled\n", + __func__ + )); + + return Status; + } + + if (RiscVMmuEnabled ()) { + mMaxRootTableLevel = 3; + mBitPerLevel = 9; + mTableEntryCount = 512; + + NumberOfDescriptors = 0; + MemoryMap = NULL; + Status = gDS->GetMemorySpaceMap ( + &NumberOfDescriptors, + &MemoryMap + ); + ASSERT_EFI_ERROR (Status); + + for (Index = 0; Index < NumberOfDescriptors; Index++) { + if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) { + // Update Read/Write/Strong Order attribute for memory mapped IO + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W | RISCV_PG_SH | RISCV_PG_SO, + PTE_ATTRIBUTES_MASK, + (UINTN *)RiscVGetRootTranslateTable (), + TRUE + ); + } else if (MemoryMap[Index].GcdMemoryType == EfiGcdMemoryTypeSystemMemory) { + // Update Read/Write/Execute/Sharable/Cacheable attribute for system memory + UpdateRegionMapping ( + MemoryMap[Index].BaseAddress, + MemoryMap[Index].Length, + RISCV_PG_R | RISCV_PG_W | RISCV_PG_X | RISCV_PG_B | RISCV_PG_C | RISCV_PG_SH, + PTE_ATTRIBUTES_MASK, + (UINTN *)RiscVGetRootTranslateTable (), + TRUE + ); + } + } + + DEBUG (( + DEBUG_INFO, + "%a: SG2042 Update memory attribute\n", + __func__ + )); + + FreePool ((VOID *)MemoryMap); + } + + return Status; +} -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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