From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.43555.1685337895637278330 for ; Sun, 28 May 2023 22:24:55 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=h7IP3nOx; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: yong.li@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685337895; x=1716873895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Iv7C0eixphQTDNTdp1BvhlB6f8iaF1KmdxBrESYIHuU=; b=h7IP3nOx2zfBz0dACAW/Z375ZRAwXZnArnZqG/ln+XGrXhixvGwnMcGR oWY8YPjtH8acrI+iiw5sTMMBjp3O8r0rFfPeVRfSe44sr2I3vzoJXheoh het81mCXKvM7L3pZuunTtw5gvYiF04k/mU9DkPV/weoAMKunWSM7pQe+x g4uFZ5/jdNGyFUeldzFEPGxW5TQB9h35xcP6Lzg7M03Ol7IwtrsixsQ5D 9HYSFpvGxTWjlSSeqNUSjyojFJWCKwk5p33H2mc+RbMuNI0vyooOIrXZr DgJv2GzbdAj3Q06F/eixjHRWfX28SOXvt1B2kD+s8IEVB7jQgzhk8bgm+ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="344120938" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="344120938" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 May 2023 22:24:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10724"; a="771002581" X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="771002581" Received: from intel-optiplex-7090.sh.intel.com ([10.239.159.128]) by fmsmga008.fm.intel.com with ESMTP; 28 May 2023 22:24:52 -0700 From: "Li, Yong" To: devel@edk2.groups.io Cc: Yong Li , Andrei Warkentin , Evan Chai , Sunil V L , Tuan Phan Subject: [PATCH 1/1] MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64 Date: Mon, 29 May 2023 13:24:42 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Impelement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrier in RiscV: fence.i; fence r,r More detail is in Chapter 17, RVWMO Memory Consistency Model https://github.com/riscv/riscv-isa-manual This API is first introduced in the below commits for IA32 and x64 https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3 https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4 and below the commit for ARM and AArch64 implementation https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534 This commit is to add the RiscV64 implementation which will be used by variable service under Variable/RuntimeDxe Cc: Andrei Warkentin Cc: Evan Chai Cc: Sunil V L Cc: Tuan Phan Signed-off-by: Yong Li --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + .../BaseLib/RiscV64/SpeculationBarrier.S | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3a48492b1a01..03c7b02e828b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -404,6 +404,7 @@ [Sources.RISCV64] RiscV64/CpuScratch.S | GCC RiscV64/ReadTimer.S | GCC RiscV64/RiscVMmu.S | GCC + RiscV64/SpeculationBarrier.S | GCC [Sources.LOONGARCH64] Math64.c diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S new file mode 100644 index 000000000000..581a7653996f --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S @@ -0,0 +1,34 @@ +##------------------------------------------------------------------------------ +# +# SpeculationBarrier() for RISCV64 +# +# Copyright (c) 2023, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +##------------------------------------------------------------------------------ + +.text +.p2align 2 + +ASM_GLOBAL ASM_PFX(SpeculationBarrier) + + +#/** +# Uses as a barrier to stop speculative execution. +# +# Ensures that no later instruction will execute speculatively, until all prior +# instructions have completed. +# +#**/ +#VOID +#EFIAPI +#SpeculationBarrier ( +# VOID +# ); +# +ASM_PFX(SpeculationBarrier): + fence rw,rw + fence.i + fence r,r + ret -- 2.25.1