[edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[Nate DeSimone]

This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT
to 1 and 3 respectively. This will enable OS power management to set the CPU
clock speed in the P_CNT register on these platforms.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Heng Luo <heng.luo@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

Nate DeSimone (4):
  KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

 .../CometlakeURvp/OpenBoardPkgPcd.dsc         |  9 +++-
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc     |  9 +++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc            | 52 +++++++++++++++++--
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc          | 11 +++-
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc         | 10 +++-
 .../UpXtreme/OpenBoardPkgPcd.dsc              |  9 +++-
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc       |  9 +++-
 7 files changed, 98 insertions(+), 11 deletions(-)

-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Merged missing PCD settings into GalagoPro3

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Benjamin Doron <benjamin.doron00@gmail.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc     |  9 +++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc            | 52 +++++++++++++++++--
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc          | 11 +++-
 3 files changed, 65 insertions(+), 7 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the Aspire VN7-572G board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -346,6 +346,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..26e2c16aae 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the GalagoPro3 board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -40,6 +40,26 @@
   #
   gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
 
+  #
+  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+  #        (both inside FSP and outside FSP).
+  #        Pros:
+  #          * PEI Main is re-built from source and is always the latest version
+  #          * Platform code can link any desired LibraryClass to PEI Main
+  #            (Ex: Custom DebugLib instance, SerialPortLib, etc.)
+  #        Cons:
+  #          * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+  #            that the FSP PEIMs were tested with, adding risk of breakage.
+  #          * Two copies of PEI Main will exist in the final binary,
+  #            #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+  #            executed, wasting space.
+  #
+  # <b>TRUE</b>:  The PEI Main included in FSP is used to dispatch all PEIMs
+  #        (both inside FSP and outside FSP). PEI Main will not be included in
+  #        FvPreMemory. This is the default and is the recommended choice.
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
+
   #
   # FSP Base address PCD will be updated in FDF basing on flash map.
   #
@@ -52,6 +72,7 @@
   gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
   gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
 
+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
   #
   # FSP API mode does not share stack with the boot loader,
   # so FSP needs more temporary memory for FSP heap + stack size.
@@ -63,6 +84,24 @@
   # since the stacks are separate.
   #
   gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+!else
+  #
+  # In FSP Dispatch mode boot loader stack size must be large
+  # enough for executing both boot loader and FSP.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
+!endif
+
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+!else
+  #
+  # FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same
+  # platform memory.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
+!endif
 
 [PcdsFeatureFlag.common]
   ######################################
@@ -222,7 +261,7 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
-
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
   #
   # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
   # (They will be DynamicEx in FSP Dispatch mode)
@@ -242,6 +281,7 @@
   #  3: Place AP in the Run-Loop state.
   # @Prompt The AP wait loop state.
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+!endif
 
   ######################################
   # Silicon Configuration
@@ -251,8 +291,12 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
-  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
 
   ######################################
   # Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 725596cbf7..ccf757e202 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the KabylakeRvp3 board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -78,6 +78,7 @@
   # so FSP needs more temporary memory for FSP heap + stack size.
   #
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
+
   #
   # FSP API mode does not need to enlarge the boot loader stack size
   # since the stacks are separate.
@@ -290,6 +291,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
@@ -346,7 +354,6 @@
   gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 !endif
 
-
   ######################################
   # Board Configuration
   ######################################
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++-
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index 84d4ec1331..8f3cc6ba28 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the UpXtreme board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -259,6 +259,13 @@
   gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
   gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 4a7ba4d5f0..4a5d5ef03b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the WhiskeylakeURvp board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -242,6 +242,13 @@
   ######################################
   gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ######################################
   # Platform Configuration
   ######################################
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
   #
-- 
2.27.0.windows.1

[edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the TigerlakeURvp board.
 #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -118,6 +118,14 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
 #!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
 [PcdsFeatureFlag.common]
   ######################################
   # Edk2 Configuration
-- 
2.27.0.windows.1

Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

It seems the FSP changes should at least be in a separate commit even if 
a part of this overall series.

Regards,
Michael

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Merged missing PCD settings into GalagoPro3
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Benjamin Doron <benjamin.doron00@gmail.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc     |  9 +++-
>   .../GalagoPro3/OpenBoardPkgPcd.dsc            | 52 +++++++++++++++++--
>   .../KabylakeRvp3/OpenBoardPkgPcd.dsc          | 11 +++-
>   3 files changed, 65 insertions(+), 7 deletions(-)
> 
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> index 21ee86403d..02080aa864 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the Aspire VN7-572G board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -346,6 +346,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..26e2c16aae 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the GalagoPro3 board.
>   #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -40,6 +40,26 @@
>     #
>     gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
>   
> +  #
> +  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
> +  #        (both inside FSP and outside FSP).
> +  #        Pros:
> +  #          * PEI Main is re-built from source and is always the latest version
> +  #          * Platform code can link any desired LibraryClass to PEI Main
> +  #            (Ex: Custom DebugLib instance, SerialPortLib, etc.)
> +  #        Cons:
> +  #          * The PEI Main being used to execute FSP PEIMs is not the PEI Main
> +  #            that the FSP PEIMs were tested with, adding risk of breakage.
> +  #          * Two copies of PEI Main will exist in the final binary,
> +  #            #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> +  #            executed, wasting space.
> +  #
> +  # <b>TRUE</b>:  The PEI Main included in FSP is used to dispatch all PEIMs
> +  #        (both inside FSP and outside FSP). PEI Main will not be included in
> +  #        FvPreMemory. This is the default and is the recommended choice.
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> +
>     #
>     # FSP Base address PCD will be updated in FDF basing on flash map.
>     #
> @@ -52,6 +72,7 @@
>     gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
>     gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
>   
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
>     #
>     # FSP API mode does not share stack with the boot loader,
>     # so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
>     # since the stacks are separate.
>     #
>     gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> +!else
> +  #
> +  # In FSP Dispatch mode boot loader stack size must be large
> +  # enough for executing both boot loader and FSP.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
> +!endif
> +
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> +  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
> +!else
> +  #
> +  # FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same
> +  # platform memory.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
> +!endif
>   
>   [PcdsFeatureFlag.common]
>     ######################################
> @@ -222,7 +261,7 @@
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> -
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
>     #
>     # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
>     # (They will be DynamicEx in FSP Dispatch mode)
> @@ -242,6 +281,7 @@
>     #  3: Place AP in the Run-Loop state.
>     # @Prompt The AP wait loop state.
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +!endif
>   
>     ######################################
>     # Silicon Configuration
> @@ -251,8 +291,12 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> -  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> -  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
>   
>     ######################################
>     # Platform Configuration
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> index 725596cbf7..ccf757e202 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the KabylakeRvp3 board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -78,6 +78,7 @@
>     # so FSP needs more temporary memory for FSP heap + stack size.
>     #
>     gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> +
>     #
>     # FSP API mode does not need to enlarge the boot loader stack size
>     # since the stacks are separate.
> @@ -290,6 +291,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> @@ -346,7 +354,6 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>   !endif
>   
> -
>     ######################################
>     # Board Configuration
>     ######################################

Re: [edk2-devel] [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 ++++++++-
>   .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
>   2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> index 84d4ec1331..8f3cc6ba28 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the UpXtreme board.
>   #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -259,6 +259,13 @@
>     gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
>     gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
> index 4a7ba4d5f0..4a5d5ef03b 100644
> --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the WhiskeylakeURvp board.
>   #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -242,6 +242,13 @@
>     ######################################
>     gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################

Re: [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> index 589b002d06..68dd08423b 100644
> --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the CometlakeURvp board.
>   #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -253,6 +253,13 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>     gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     #
>     # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
>     #

Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> index ebbbc7b9f9..aba3c8d6d0 100644
> --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the TigerlakeURvp board.
>   #
> -#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
>   #  SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
>   ##
> @@ -118,6 +118,14 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
>   #!endif
>     gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
> +
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>   [PcdsFeatureFlag.common]
>     ######################################
>     # Edk2 Configuration

Re: [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>

> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Monday, June 6, 2022 3:50 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>
> Subject: [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg:
> Indicate width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9
> ++++++++-
>  .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc                  | 9 ++++++++-
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> index 84d4ec1331..8f3cc6ba28 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> ds
> +++ c
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the UpXtreme board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -259,6 +259,13 @@
>    gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgToken
> SpaceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> index 4a7ba4d5f0..4a5d5ef03b 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pk
> +++ gPcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the WhiskeylakeURvp board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -242,6 +242,13 @@
>    ######################################
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgToken
> SpaceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    ######################################
>    # Platform Configuration
>    ######################################
> --
> 2.27.0.windows.1

Re: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>

> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Monday, June 6, 2022 3:50 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Esakkithevar, Kathappan
> <kathappan.esakkithevar@intel.com>
> Subject: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> index 589b002d06..68dd08423b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the CometlakeURvp board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -253,6 +253,13 @@
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    #
>    # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>    #
> --
> 2.27.0.windows.1

Re: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>

> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Monday, June 6, 2022 3:51 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>; Luo, Heng <heng.luo@intel.com>
> Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> index ebbbc7b9f9..aba3c8d6d0 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the TigerlakeURvp board.
>  #
> -#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14
> @@
>    gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
>  #!endif
>    gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
> +
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>  [PcdsFeatureFlag.common]
>    ######################################
>    # Edk2 Configuration
> --
> 2.27.0.windows.1

Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Thanks for the feedback Michael. This has been addressed in the new V2 series.

-----Original Message-----
From: Michael Kubacki <mikuback@linux.microsoft.com> 
Sent: Monday, June 6, 2022 3:56 PM
To: devel@edk2.groups.io; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Kubacki, Michael <michael.kubacki@microsoft.com>; Benjamin Doron <benjamin.doron00@gmail.com>; Soller, Jeremy <jeremy@system76.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

It seems the FSP changes should at least be in a separate commit even if a part of this overall series.

Regards,
Michael

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register and 
> indicate the width of the clock duty cycle to OS power management
> 
> Merged missing PCD settings into GalagoPro3
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Benjamin Doron <benjamin.doron00@gmail.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc     |  9 +++-
>   .../GalagoPro3/OpenBoardPkgPcd.dsc            | 52 +++++++++++++++++--
>   .../KabylakeRvp3/OpenBoardPkgPcd.dsc          | 11 +++-
>   3 files changed, 65 insertions(+), 7 deletions(-)
> 
> diff --git 
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc 
> b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> index 21ee86403d..02080aa864 100644
> --- 
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP
> +++ kgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the Aspire VN7-572G board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights 
> reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights 
> +reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -346,6 +346,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  # 
> + and indicate the width of the clock duty cycle to OS power 
> + management  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> diff --git 
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..26e2c16aae 100644
> --- 
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.d
> +++ sc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the GalagoPro3 board.
>   #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights 
> reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights 
> +reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -40,6 +40,26 @@
>     #
>     gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
>   
> +  #
> +  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
> +  #        (both inside FSP and outside FSP).
> +  #        Pros:
> +  #          * PEI Main is re-built from source and is always the latest version
> +  #          * Platform code can link any desired LibraryClass to PEI Main
> +  #            (Ex: Custom DebugLib instance, SerialPortLib, etc.)
> +  #        Cons:
> +  #          * The PEI Main being used to execute FSP PEIMs is not the PEI Main
> +  #            that the FSP PEIMs were tested with, adding risk of breakage.
> +  #          * Two copies of PEI Main will exist in the final binary,
> +  #            #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> +  #            executed, wasting space.
> +  #
> +  # <b>TRUE</b>:  The PEI Main included in FSP is used to dispatch all PEIMs
> +  #        (both inside FSP and outside FSP). PEI Main will not be included in
> +  #        FvPreMemory. This is the default and is the recommended choice.
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> +
>     #
>     # FSP Base address PCD will be updated in FDF basing on flash map.
>     #
> @@ -52,6 +72,7 @@
>     gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
>     gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
>   
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
>     #
>     # FSP API mode does not share stack with the boot loader,
>     # so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
>     # since the stacks are separate.
>     #
>     gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> +!else
> +  #
> +  # In FSP Dispatch mode boot loader stack size must be large
> +  # enough for executing both boot loader and FSP.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
> +!endif
> +
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> +  
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceG
> +uid.PcdPciExpressBaseAddress
> +  
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgToken
> +SpaceGuid.PcdPciExpressRegionLength
> +!else
> +  #
> +  # FSP Dispatch mode requires more platform memory as boot loader 
> +and FSP sharing the same
> +  # platform memory.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
> +!endif
>   
>   [PcdsFeatureFlag.common]
>     ######################################
> @@ -222,7 +261,7 @@
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> -
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
>     #
>     # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
>     # (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7 
> @@
>     #  3: Place AP in the Run-Loop state.
>     # @Prompt The AP wait loop state.
>     gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +!endif
>   
>     ######################################
>     # Silicon Configuration
> @@ -251,8 +291,12 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> -  
> gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGu
> id.PcdPciExpressBaseAddress
> -  
> gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenS
> paceGuid.PcdPciExpressRegionLength
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  # 
> + and indicate the width of the clock duty cycle to OS power 
> + management  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
>   
>     ######################################
>     # Platform Configuration
> diff --git 
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc 
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> index 725596cbf7..ccf757e202 100644
> --- 
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the KabylakeRvp3 board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights 
> reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights 
> +reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -78,6 +78,7 @@
>     # so FSP needs more temporary memory for FSP heap + stack size.
>     #
>     gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> +
>     #
>     # FSP API mode does not need to enlarge the boot loader stack size
>     # since the stacks are separate.
> @@ -290,6 +291,13 @@
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>     gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  # 
> + and indicate the width of the clock duty cycle to OS power 
> + management  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     ######################################
>     # Platform Configuration
>     ######################################
> @@ -346,7 +354,6 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>   !endif
>   
> -
>     ######################################
>     # Board Configuration
>     ######################################

Re: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Heng Luo]

Reviewed-by: Heng Luo <heng.luo@intel.com>

> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Tuesday, June 7, 2022 6:51 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Kubacki, Michael <michael.kubacki@microsoft.com>;
> Luo, Heng <heng.luo@intel.com>
> Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> width of the clock duty cycle to OS power management
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Heng Luo <heng.luo@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> index ebbbc7b9f9..aba3c8d6d0 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the TigerlakeURvp board.
>  #
> -#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14 @@
>    gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
>  #!endif
>    gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
> +
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>  [PcdsFeatureFlag.common]
>    ######################################
>    # Edk2 Configuration
> --
> 2.27.0.windows.1

Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael D Kinney]

Acked-by: Michael D Kinney <michael.d.kinney@intel.com>


> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Heng Luo
> Sent: Monday, June 6, 2022 6:07 PM
> To: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>
> Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
> 
> Reviewed-by: Heng Luo <heng.luo@intel.com>
> 
> > -----Original Message-----
> > From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> > Sent: Tuesday, June 7, 2022 6:51 AM
> > To: devel@edk2.groups.io
> > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit
> > <ankit.sinha@intel.com>; Kubacki, Michael <michael.kubacki@microsoft.com>;
> > Luo, Heng <heng.luo@intel.com>
> > Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> > width of CLK duty cycle in FADT
> >
> > Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> > width of the clock duty cycle to OS power management
> >
> > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> > Cc: Ankit Sinha <ankit.sinha@intel.com>
> > Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> > Cc: Heng Luo <heng.luo@intel.com>
> > Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> > ---
> >  .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
> >  1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > index ebbbc7b9f9..aba3c8d6d0 100644
> > ---
> > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > +++
> > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> > +++ .dsc
> > @@ -1,7 +1,7 @@
> >  ## @file
> >  #  PCD configuration build description file for the TigerlakeURvp board.
> >  #
> > -#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> > +reserved.<BR>
> >  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14 @@
> >    gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
> >  #!endif
> >    gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
> > +
> > +  #
> > +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> > + and indicate the width of the clock duty cycle to OS power management
> > + #
> > +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> > +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> > +
> >  [PcdsFeatureFlag.common]
> >    ######################################
> >    # Edk2 Configuration
> > --
> > 2.27.0.windows.1
> 
> 
> 
> 
>