From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web08.5264.1654556162997232686 for ; Mon, 06 Jun 2022 15:56:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=CF+Doxu5; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from [192.168.4.22] (unknown [47.195.228.134]) by linux.microsoft.com (Postfix) with ESMTPSA id 5892C20BE623; Mon, 6 Jun 2022 15:56:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5892C20BE623 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1654556162; bh=y5V84xdLdIImu3FSrX2TTjeCsJ9wD5AFVczwILZEgfY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=CF+Doxu5cdLFH/wWDlEC8vyW47joSteVoDyIRplO4fTTy9aKRHBU0Onqxs5Zt1HoH icvSeacFPlnvnen6lYZ95FZlWKVz1Vl5+gejH1K11/dLjFvbmrp5/pZaN6Wj36/NQu BMUGYuxsiS16rs70M/nHsBezyt1HvuUiyzL4K8PM= Message-ID: Date: Mon, 6 Jun 2022 18:56:00 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT To: devel@edk2.groups.io, nathaniel.l.desimone@intel.com Cc: Chasel Chiu , Ankit Sinha , Michael Kubacki , Benjamin Doron , Jeremy Soller References: <20220606225030.3403-1-nathaniel.l.desimone@intel.com> <20220606225030.3403-2-nathaniel.l.desimone@intel.com> From: "Michael Kubacki" In-Reply-To: <20220606225030.3403-2-nathaniel.l.desimone@intel.com> Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit It seems the FSP changes should at least be in a separate commit even if a part of this overall series. Regards, Michael On 6/6/2022 6:50 PM, Nate DeSimone wrote: > Set the location of the DUTY_CYCLE field in the P_CNT register > and indicate the width of the clock duty cycle to OS power management > > Merged missing PCD settings into GalagoPro3 > > Cc: Chasel Chiu > Cc: Ankit Sinha > Cc: Michael Kubacki > Cc: Benjamin Doron > Cc: Jeremy Soller > Signed-off-by: Nate DeSimone > --- > .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 +++- > .../GalagoPro3/OpenBoardPkgPcd.dsc | 52 +++++++++++++++++-- > .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++- > 3 files changed, 65 insertions(+), 7 deletions(-) > > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc > index 21ee86403d..02080aa864 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc > +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the Aspire VN7-572G board. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -346,6 +346,13 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and BIOS Guard not present, measured boot enforcement checking code not present > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register > + # and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > index 44dacdf082..26e2c16aae 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the GalagoPro3 board. > # > -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -40,6 +40,26 @@ > # > gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE > > + # > + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs > + # (both inside FSP and outside FSP). > + # Pros: > + # * PEI Main is re-built from source and is always the latest version > + # * Platform code can link any desired LibraryClass to PEI Main > + # (Ex: Custom DebugLib instance, SerialPortLib, etc.) > + # Cons: > + # * The PEI Main being used to execute FSP PEIMs is not the PEI Main > + # that the FSP PEIMs were tested with, adding risk of breakage. > + # * Two copies of PEI Main will exist in the final binary, > + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never > + # executed, wasting space. > + # > + # TRUE: The PEI Main included in FSP is used to dispatch all PEIMs > + # (both inside FSP and outside FSP). PEI Main will not be included in > + # FvPreMemory. This is the default and is the recommended choice. > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE > + > # > # FSP Base address PCD will be updated in FDF basing on flash map. > # > @@ -52,6 +72,7 @@ > gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 > gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 > > +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 > # > # FSP API mode does not share stack with the boot loader, > # so FSP needs more temporary memory for FSP heap + stack size. > @@ -63,6 +84,24 @@ > # since the stacks are separate. > # > gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 > +!else > + # > + # In FSP Dispatch mode boot loader stack size must be large > + # enough for executing both boot loader and FSP. > + # > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 > +!endif > + > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) > + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength > +!else > + # > + # FSP Dispatch mode requires more platform memory as boot loader and FSP sharing the same > + # platform memory. > + # > + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 > +!endif > > [PcdsFeatureFlag.common] > ###################################### > @@ -222,7 +261,7 @@ > gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 > - > +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) > # > # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild > # (They will be DynamicEx in FSP Dispatch mode) > @@ -242,6 +281,7 @@ > # 3: Place AP in the Run-Loop state. > # @Prompt The AP wait loop state. > gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 > +!endif > > ###################################### > # Silicon Configuration > @@ -251,8 +291,12 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register > + # and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > > ###################################### > # Platform Configuration > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > index 725596cbf7..ccf757e202 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc > @@ -1,7 +1,7 @@ > ## @file > # PCD configuration build description file for the KabylakeRvp3 board. > # > -# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -78,6 +78,7 @@ > # so FSP needs more temporary memory for FSP heap + stack size. > # > gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 > + > # > # FSP API mode does not need to enlarge the boot loader stack size > # since the stacks are separate. > @@ -290,6 +291,13 @@ > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 > gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > > + # > + # Set the location of the DUTY_CYCLE field in the P_CNT register > + # and indicate the width of the clock duty cycle to OS power management > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3 > + > ###################################### > # Platform Configuration > ###################################### > @@ -346,7 +354,6 @@ > gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} > !endif > > - > ###################################### > # Board Configuration > ######################################