From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web10.26188.1629129219962881896 for ; Mon, 16 Aug 2021 08:53:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=AQfFfPK9; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from [10.0.0.120] (c-73-27-179-174.hsd1.fl.comcast.net [73.27.179.174]) by linux.microsoft.com (Postfix) with ESMTPSA id DB7BA20C29E6; Mon, 16 Aug 2021 08:53:38 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com DB7BA20C29E6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1629129219; bh=keG8ubD7jDhIGb5M9G4Xik3jqD3PCaIYjoHi6AZDNco=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=AQfFfPK98/sWj6xOrGOfXQzJ9xwZSceYq2wcKFjlZme+8iDVmVmj18bVG6TugTr2u buAyaK20umJAn+GuXlxrMA/dgtmamJpO6FLfqEyuFsxIHYSBURaWuRCMJsS2YzJSX2 1Zv4wvgvLyFYrs46BUTgKpEtSHa6kDfL/+d8vBLo= Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeSiliconPkg: Default for PeciC10Reset should be 1 To: devel@edk2.groups.io, nathaniel.l.desimone@intel.com Cc: Chasel Chiu , Sai Chaganty , Benjamin Doron , Michael Kubacki References: <20210816040238.29564-1-nathaniel.l.desimone@intel.com> From: "Michael Kubacki" Message-ID: Date: Mon, 16 Aug 2021 11:53:37 -0400 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: <20210816040238.29564-1-nathaniel.l.desimone@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Reviewed-by: Michael Kubacki On 8/16/2021 12:02 AM, Nate DeSimone wrote: > The default value for CpuConfigLibPreMemConfig->PeciC10Reset > should be 1 so that Peci Reset on C10 exit is disabled. > > Other bug fixes in > KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c > > 1. PCI configuration space can only be read 32-bits at a time. > Converted MmioRead64 to MmioRead32. > 2. Added a RShiftU64() call to prevent compiler instrinsics from > being inserted. Since this is a 64-bit integer shift done in > IA-32 mode it is possible for intrinsic calls to be added. > > Cc: Chasel Chiu > Cc: Sai Chaganty > Cc: Benjamin Doron > Cc: Michael Kubacki > Signed-off-by: Nate DeSimone > --- > .../Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c > index 35041322a7..85baa46208 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c > @@ -1,7 +1,7 @@ > /** @file > This file is PeiCpuPolicy library. > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -45,13 +45,14 @@ LoadCpuConfigLibPreMemConfigDefault ( > CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance > CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active > CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE; > - CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); > + CpuConfigLibPreMemConfig->CpuRatio = RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK; > + > /// > /// FCLK Frequency > /// > CpuFamily = GetCpuFamily(); > CpuSku = GetCpuSku(); > - MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0; > + MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0; > if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) { > PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3; > } else { > @@ -67,6 +68,8 @@ LoadCpuConfigLibPreMemConfigDefault ( > } else { > CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz > } > + > + CpuConfigLibPreMemConfig->PeciC10Reset = 1; // Disables Peci Reset on C10 exit > } > > /**