From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 26 Apr 2019 13:27:48 -0700 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 723BECCB7F; Fri, 26 Apr 2019 20:27:48 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-104.rdu2.redhat.com [10.10.121.104]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2E0001001DDB; Fri, 26 Apr 2019 20:27:46 +0000 (UTC) Subject: Re: [edk2-devel] [Patch 1/4] MdePkg/BaseLib: Verify SSE2 support in IA32 AsmLfence() To: devel@edk2.groups.io, michael.d.kinney@intel.com Cc: Liming Gao References: <20190425175334.5944-1-michael.d.kinney@intel.com> <20190425175334.5944-2-michael.d.kinney@intel.com> From: "Laszlo Ersek" Message-ID: Date: Fri, 26 Apr 2019 22:27:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20190425175334.5944-2-michael.d.kinney@intel.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Fri, 26 Apr 2019 20:27:48 +0000 (UTC) Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 04/25/19 19:53, Michael D Kinney wrote: > Use CPUID in IA32 implementation of AsmLfence() to verify > that SSE2 is supported before using the LFENCE instruction. > > Cc: Liming Gao > Signed-off-by: Michael D Kinney > --- > MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm > index 44478be35f..0a60ae1d57 100644 > --- a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm > +++ b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm > @@ -1,5 +1,5 @@ > ;------------------------------------------------------------------------------ ; > -; Copyright (c) 2018, Intel Corporation. All rights reserved.
> +; Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent > ; > ; Module Name: > @@ -26,5 +26,17 @@ > ;------------------------------------------------------------------------------ > global ASM_PFX(AsmLfence) > ASM_PFX(AsmLfence): > + ; > + ; Use CPUID instruction (CPUID.01H:EDX.SSE2[bit 26] = 1) to test whether the > + ; processor supports SSE2 instruction. Save/restore non-volatile register > + ; EBX that is modified by CPUID > + ; > + push ebx > + mov eax, 1 > + cpuid > + bt edx, 26 > + jnc Done > lfence > +Done: > + pop ebx > ret > The SDM seems to confirm that lfence depends on SSE2. However, that raises another question: AsmLfence() is used for implementing SpeculationBarrier() on IA32/X64. And so I wonder: the plaforms where lfence is unavailable, do they *not* need a speculation barrier at all, or do they need a *different* implementation? Thanks, Laszlo