From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1264321B02822 for ; Wed, 7 Nov 2018 05:41:41 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 999F14E4C6; Wed, 7 Nov 2018 13:41:40 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-90.rdu2.redhat.com [10.10.120.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id BA45E60462; Wed, 7 Nov 2018 13:41:39 +0000 (UTC) To: Eric Dong , edk2-devel@lists.01.org Cc: Ruiyu Ni References: <20181107082607.6608-1-eric.dong@intel.com> From: Laszlo Ersek Message-ID: Date: Wed, 7 Nov 2018 14:41:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181107082607.6608-1-eric.dong@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 07 Nov 2018 13:41:40 +0000 (UTC) Subject: Re: [Patch] UefiCpuPkg/RegisterCpuFeaturesLib: Adjust Order. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 13:41:41 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/07/18 09:26, Eric Dong wrote: > In current code logic, only adjust feature position if current CPU > feature position not follow the request order. Just like Feature A > need to be executed before feature B, but current feature A registers > after feature B. So code will adjust the position for feature A, move > it to just before feature B. If the position already met the > requirement, code will not adjust the position. > > This logic has issue when met all below cases: > 1. feature A has core or package level dependence with feature B. > 2. feature A is register before feature B. > 3. Also exist other features exist between feature A and B. > > Root cause is driver ignores the dependence for this case, so threads > may execute not follow the dependence order. > > Fix this issue by change code logic to adjust feature position for > CPU features which has dependence relationship. > > Change-Id: I86171cb1dbf44a2f6fd8d5d2209cafee9451b866 > Cc: Laszlo Ersek > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > --- > .../RegisterCpuFeaturesLib.c | 62 ++++++++++++++++++++-- > 1 file changed, 58 insertions(+), 4 deletions(-) (1) please drop the "Change-Id" line from the commit message. (2) Other than that, I defer to Ray. Thanks Laszlo