From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web11.341.1571160052087569537 for ; Tue, 15 Oct 2019 10:20:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=kCg+nA92; spf=pass (domain: nvidia.com, ip: 216.228.121.64, mailfrom: ashishsingha@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 15 Oct 2019 10:21:02 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 15 Oct 2019 10:20:51 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 15 Oct 2019 10:20:51 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 15 Oct 2019 17:20:50 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 15 Oct 2019 17:20:50 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 15 Oct 2019 17:20:50 +0000 Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 15 Oct 2019 10:20:50 -0700 From: "Ashish Singhal" To: , , , CC: Ashish Singhal Subject: [PATCH v4 0/2] Fix Aligned Page Allocation For XHCI Date: Tue, 15 Oct 2019 11:20:45 -0600 Message-ID: X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1571160062; bh=wQFQrwp/g5iow59yUpnutr6vu8qVQsB/mm3YaAlyBp4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=kCg+nA925bk7WjzWWZkyeuv57Bd8rZ1nMM4BGjvmw6N6tPkCSt9qFuIqH6EbP+xg7 dnPlOB5x6/ZMfE0845ssv/QL7h9kNXjP4u5ri5BaijwX8gvn5wdTBgZ4OaqO8rlxiP tRLMyd0ZZsW3VX+g11Dcf3vL3BZdGggJGOqL8oAhgcKMt7VPaaCv8y10N9BB3LfoSQ tEPv/DOAXvIVIuJn9wHj687oRRnJbk+F2nhZO1942G/PDHOdNSswrOt9xVNXAhGGhL NoQIr8GgfY3MNMEk3Pm5v2aofx0VVqh4Hwfy56b5Y39ext0nZiCnsvjrBd7jRwNioa ttS/Tvx2l7EDg== Content-Type: text/plain This patch set is an attempt to fix the error where we allocate incorrectly aligned memory for XHCI PEI and DXE. The change for DXE phase has been verified already but change for PEI needs to be verified by Hao as I do not have a setup to be able to verify that. The change in DXE just updates a parameter passed in to allocate aligned memory. The change in PEI adds a new function to allocate aligned memory. There was no need to add separate function to free aligned pages as unaligned pages have been already freed during allocation function and the aligned one can be freed using the existing function. Ashish Singhal (2): MdeModulePkg/XhciDxe: Fix Aligned Page Allocation MdeModulePkg/XhciPei: Fix Aligned Page Allocation MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 2 +- MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c | 128 ++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 25 +------ MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h | 28 +++++++ 4 files changed, 161 insertions(+), 22 deletions(-) -- 2.7.4