* [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables
@ 2022-02-07 19:02 Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3 Oram, Isaac W
` (7 more replies)
0 siblings, 8 replies; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Nate DeSimone, Liming Gao, Eric Dong
This patch series adds ACPI tables and the associated UBA driver required to patch the tables during boot.
The common AmlGenOffset python script needed to be updated for Python 3.
The server ACPI tables are large, so the 02 through 05 are just separating into multiple commits for review.
Building ACPI tables requires a pre-build step that generates AML offsets by building the ACPI tables with
the appropriate flags, then stripping out offsets that do not need to be patched during boot.
Then the stripped down AML offsets are available for the main build as a C source data structure.
In the main build, StaticSkuDataDxe incorporates the AML offset data and publishes them if it is the
correct motherboard.
The AcpiTables10nm data file and the StaticSkuDataDxe driver were previously provided in binary form in
FvLateOpenBoard. The AcpiPlatform driver that consumes the AML offset data and patches tables with boottime
data is still a binary.
The tables are provided as a part of WhitleyOpenBoardPkg because they can support multiple boards.
It is expected that most boards will make copies in their board directories and customize from there.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
Isaac Oram (8):
MinPlatformPkg/AmlGenOffset: Update for python 3
WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions
WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables
WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table
WhitleyOpenBoardPkg/Build: Enable includable build options
WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table
WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver
Platform/Intel/.gitignore | 2 +
Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py | 13 +-
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc | 54 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc | 81 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl | 20 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi | 346 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi | 205 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi | 730 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl | 61 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl | 19 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi | 137 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi | 183 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl | 1322 +++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi | 328 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi | 270 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi | 164 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi | 25 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi | 66 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi | 427 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi | 18 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi | 669 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl | 91 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi | 191 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi | 5388 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi | 219 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi | 163 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc | 72 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc | 171 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc | 972 ++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc | 61 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc | 68 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc | 137 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc | 44 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc | 136 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc | 89 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h | 91 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h | 30 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h | 37 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h | 206 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h | 88 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h | 43 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h | 58 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h | 57 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h | 56 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h | 84 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h | 58 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h | 50 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h | 120 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h | 87 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h | 59 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h | 82 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h | 67 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc | 151 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h | 41 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h | 42 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 7 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 148 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 1 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 5 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c | 54 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c | 100 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c | 110 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md | 19 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c | 60 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h | 41 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf | 59 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 5 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc | 41 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf | 26 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py | 63 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg | 15 +
Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h | 8 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl | 833 +++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl | 307 ++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl | 271 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl | 203 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl | 50 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl | 558 ++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl | 150 +
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 1 +
123 files changed, 19064 insertions(+), 157 deletions(-)
create mode 100644 Platform/Intel/.gitignore
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl
--
2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions Oram, Isaac W
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Nate DeSimone, Liming Gao, Eric Dong
Update for library changes.
Remove version.
Changed to not open files as bytes.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py b/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
index e13ca06471..4799eee1a9 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
@@ -32,16 +32,16 @@ if __name__ == '__main__':
#
# Create command line argument parser object
#
- parser = argparse.ArgumentParser(prog=__prog__, version=__version__, usage=__usage__, description=__copyright__, conflict_handler='resolve')
+ parser = argparse.ArgumentParser(prog=__prog__, usage=__usage__, description=__copyright__, conflict_handler='resolve')
group = parser.add_mutually_exclusive_group(required=True)
group.add_argument("-e", action="store_true", dest='Encode', help='encode file')
group.add_argument("-d", action="store_true", dest='Decode', help='decode file')
- parser.add_argument("-o", "--output", dest='OutputFile', type=str, metavar='filename', help="specify the output filename", required=True)
+ parser.add_argument("-o", "--output", dest='OutputFileName', type=str, metavar='filename', help="specify the output filename", required=True)
parser.add_argument("-v", "--verbose", dest='Verbose', action="store_true", help="increase output messages")
parser.add_argument("-q", "--quiet", dest='Quiet', action="store_true", help="reduce output messages")
parser.add_argument("--debug", dest='Debug', type=int, metavar='[0-9]', choices=range(0,10), default=0, help="set debug level")
parser.add_argument("--aml_filter", dest='AmlFilterStr', type=str, help="specify the AML filter.")
- parser.add_argument(metavar="input_file", dest='InputFile', type=argparse.FileType('rb'), help="specify the input filename")
+ parser.add_argument(metavar="input_file", dest='InputFile', type=argparse.FileType('r'), help="specify the input filename")
#
# Parse command line arguments
@@ -49,11 +49,11 @@ if __name__ == '__main__':
args = parser.parse_args()
if args.Encode:
- print 'Unsupported'
+ print('Unsupported')
if args.Decode:
- args.OutputFileName = args.OutputFile
- args.OutputFile = open(args.OutputFileName, 'wb')
+ args.OutputFileName = os.path.normpath(args.OutputFileName)
+ args.OutputFile = open(args.OutputFileName, 'w')
AmlFilter = args.AmlFilterStr
filter_pattern = '|'.join(AmlFilter.split(' '))
@@ -69,4 +69,3 @@ if __name__ == '__main__':
if match_obj is not None:
args.OutputFile.write(line)
args.OutputFile.close()
-
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3 Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL Oram, Isaac W
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
Header files for C structures used to build ACPI tables
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h | 91 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h | 30 +++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h | 37 ++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h | 206 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h | 88 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h | 43 ++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h | 58 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h | 57 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h | 56 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h | 84 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h | 58 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h | 50 +++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h | 45 +++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h | 120 ++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h | 87 +++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h | 48 +++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h | 59 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h | 82 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h | 53 +++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h | 67 +++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 7 +-
Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h | 8 +
22 files changed, 1430 insertions(+), 4 deletions(-)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
new file mode 100644
index 0000000000..0fb913a6a8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
@@ -0,0 +1,91 @@
+/** @file
+ This file describes the contents of the BDAT ACPI.
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BDAT_H_
+#define _BDAT_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+#define EFI_BDAT_TABLE_SIGNATURE SIGNATURE_32('B','D','A','T')
+
+#define BDAT_PRIMARY_VER 0x0004
+#define BDAT_SECONDARY_VER 0x0000
+
+typedef struct {
+ UINT8 BiosDataSignature[8]; // "BDATHEAD"
+ UINT32 BiosDataStructSize; // sizeof BDAT_STRUCTURE + sizeof BDAT_MEMORY_DATA_STRUCTURE + sizeof BDAT_RMT_STRUCTURE
+ UINT16 Crc16; // 16-bit CRC of BDAT_STRUCTURE (calculated with 0 in this field)
+ UINT16 Reserved;
+ UINT16 PrimaryVersion; // Primary version
+ UINT16 SecondaryVersion; // Secondary version
+ UINT32 OemOffset; // Optional offset to OEM-defined structure
+ UINT32 Reserved1;
+ UINT32 Reserved2;
+} BDAT_HEADER_STRUCTURE;
+
+typedef struct bdatSchemaList {
+ UINT16 SchemaListLength; //Number of Schemas present
+ UINT16 Reserved;
+ UINT16 Year;
+ UINT8 Month;
+ UINT8 Day;
+ UINT8 Hour;
+ UINT8 Minute;
+ UINT8 Second;
+ UINT8 Reserved1;
+ //
+ // This is a dynamic region, where Schema list address is filled out.
+ // Each schema location is 32 bits long and complies with BDAT 4.0 version.
+ //
+} BDAT_SCHEMA_LIST_STRUCTURE;
+
+//BDAT Header Struct which contains information all exisitng BDAT Schemas
+typedef struct bdatStruct {
+ BDAT_HEADER_STRUCTURE BdatHeader;
+ BDAT_SCHEMA_LIST_STRUCTURE BdatSchemas;
+} BDAT_STRUCTURE;
+
+//
+// BIOS Data ACPI structure
+//
+typedef struct {
+
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BdatGas;
+
+} EFI_BDAT_ACPI_DESCRIPTION_TABLE;
+
+//
+// BIOS Data Parameter Region Generic Address
+// Information
+//
+#define EFI_BDAT_ACPI_POINTER 0x0
+
+#define ___INTERNAL_CONVERT_TO_STRING___(a) #a
+#define CONVERT_TO_STRING(a) ___INTERNAL_CONVERT_TO_STRING___(a)
+
+//
+// This is copied from Include\Acpi.h
+//
+#define CREATOR_ID_INTEL 0x4C544E49 //"LTNI""INTL"(Intel)
+#define CREATOR_REV_INTEL 0x20090903
+
+#define EFI_ACPI_TABLE_VERSION_ALL (EFI_ACPI_TABLE_VERSION_1_0B|EFI_ACPI_TABLE_VERSION_2_0|EFI_ACPI_TABLE_VERSION_3_0)
+
+#pragma pack()
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
new file mode 100644
index 0000000000..cfaa9247d8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
@@ -0,0 +1,30 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DBG2_H_
+#define _DBG2_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/DebugPort2Table.h>
+
+#pragma pack(1)
+typedef
+struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Table;
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Entry;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAdressRegister;
+ UINT32 AddressSize;
+ CHAR8 NamespaceString[2];
+
+} DBG2_DEBUG_TABLE;
+#pragma pack()
+
+
+#endif //_DBG2_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
new file mode 100644
index 0000000000..56e32c41f5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
@@ -0,0 +1,37 @@
+/** @file
+ This file describes the contents of the ACPI Firmware ACPI Control
+ Structure (FACS). Some additional ACPI values are defined in Acpi1_0.h and
+ Acpi2_0.h
+ All changes to the FACS contents should be done in this file.
+
+ @copyright
+ Copyright 1996 - 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FACS_H
+#define _FACS_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// FACS Definitions
+//
+#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
+#define EFI_ACPI_GLOBAL_LOCK 0x00000000
+
+//
+// Firmware Control Structure Feature Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
+
+#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
+
+#define EFI_ACPI_OSPM_FLAGS 0x00000000
+
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
new file mode 100644
index 0000000000..004aac350d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
@@ -0,0 +1,206 @@
+/** @file
+ This file describes the contents of the ACPI Fixed ACPI Description Table
+ FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
+ All changes to the FADT contents should be done in this file.
+
+ @copyright
+ Copyright 1996 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FADT_H_
+#define _FADT_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+#include "Platform.h"
+#include <Library/PcdLib.h>
+
+//
+// FADT Definitions
+//
+#define EFI_ACPI_OEM_FADT_REVISION 0x00000000
+//
+// For ACPI 1.0 supprt
+// Harwich sets this to #define EFI_ACPI_INT_MODEL 0x01
+//
+
+/*
+INT_MODEL Field
+The FADT defines the fixed ACPI information that is needed by the operating system as
+defined in section 5.2.5 of the ACPI 1.0 specification. Currently, this table provides a field
+for INT_MODEL, which was intended to be used to report the interrupt mode of the machine.
+This field is ignored by the Microsoft?Windows?2000 and later operating system because the
+Microsoft Windows 98 operating system only supports programmable interrupt controller (PIC) mode.
+This forces system manufacturers (OEMs) who want to support Windows 98 to enter a "0" in the INT_MODEL field.
+This would then preclude using multiple processors on Windows 2000 and later versions.
+Because the INT_MODEL field in the FADT cannot be dynamically updated while the machine is running,
+it cannot be used to report the interrupt mode, and therefore it is ignored by Windows 98,
+and Windows 2000 and later versions.
+http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx
+For Watson Creek we set this to 0 and then dynamically update this to 1 in the DSDT tables _PIC method and GPIC field.
+*/
+#define EFI_ACPI_INT_MODEL 0x0
+
+#define EFI_ACPI_PREFERRED_PM_PROFILE 0x04
+
+#define EFI_ACPI_SCI_INT 0x0009
+#define EFI_ACPI_SMI_CMD 0x0
+
+#define EFI_ACPI_ACPI_ENABLE 0x00
+#define EFI_ACPI_ACPI_DISABLE 0x00
+#define EFI_ACPI_S4_BIOS_REQ 0x00
+#define EFI_ACPI_CST_CNT 0x00
+
+#define EFI_ACPI_PSTATE_CNT 0x00
+#define EFI_ACPI_GPE1_BASE (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 2)
+#define EFI_ACPI_P_LVL2_LAT 0x0065
+#define EFI_ACPI_P_LVL3_LAT 0x03E9
+//
+// #define EFI_ACPI_FLUSH_SIZE 0x0400
+//
+#define EFI_ACPI_FLUSH_SIZE 0x0000
+//
+// #define EFI_ACPI_FLUSH_STRIDE 0x0010
+//
+#define EFI_ACPI_FLUSH_STRIDE 0x0000
+#define EFI_ACPI_DUTY_OFFSET 0x01
+//
+// #define EFI_ACPI_DUTY_OFFSET 0x00
+//
+#define EFI_ACPI_DUTY_WIDTH 0x00
+
+#define EFI_ACPI_DAY_ALRM 0x0D
+#define EFI_ACPI_MON_ALRM 0x00
+#define EFI_ACPI_CENTURY 0x32
+
+//
+// IA-PC Boot Architecture Flags, see ACPI 2.0 table specification and Acpi6_2.h
+// No legacy KBC and legcay devices other reported in ASL code
+//
+// #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_2_LEGACY_DEVICES | EFI_ACPI_6_2_8042)
+//
+//#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042
+#define EFI_ACPI_OS_ASPM_DISABLE (1 << 4)
+
+#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042 | EFI_ACPI_OS_ASPM_DISABLE
+
+//
+// Fixed Feature Flags, see ACPI 6.2 table specification and Acpi6_2.h
+//
+#define EFI_ACPI_FIXED_FEATURE_FLAGS (EFI_ACPI_6_2_RESET_REG_SUP | \
+ EFI_ACPI_6_2_RTC_S4 | \
+ EFI_ACPI_6_2_SLP_BUTTON | \
+ EFI_ACPI_6_2_WBINVD | \
+ EFI_ACPI_6_2_PROC_C1 \
+ )
+
+//
+// PM1A Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS (FixedPcdGet32 (PcdEfiAcpiPm1aEvtBlkAddress))
+
+//
+// PM1B Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x00000000
+
+//
+// PM1A Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
+
+//
+// PM1B Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x00
+
+//
+// PM2 Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
+#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
+
+//
+// Power Management Timer Control Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
+
+//
+// General Purpose Event 0 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100 // size of R_PCH_ACPI_GPE0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96 (2*0x80 = 0x100)
+#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_GPE0_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x80)
+
+//
+// General Purpose Event 1 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0
+#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0
+#define EFI_ACPI_GPE1_BLK_ADDRESS 0x0
+//
+// Reset Register Generic Address Information
+//
+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
+#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
+#define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9
+#define EFI_ACPI_RESET_VALUE 0x06
+
+//
+// Number of bytes decoded by PM1 event blocks (a and b)
+//
+#define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM1 control blocks (a and b)
+//
+#define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM2 control block
+//
+#define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by PM timer block
+//
+#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE0 block
+//
+#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE1 block
+//
+#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
new file mode 100644
index 0000000000..ad6684acce
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
@@ -0,0 +1,88 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _HMAT_HMAT_H_
+#define _HMAT_HMAT_H_
+
+#include <IndustryStandard/Acpi.h>
+#include <UncoreCommonIncludes.h>
+#include "Platform.h"
+#include "Msars.h"
+#include "Sllbis.h"
+#include "Mscis.h"
+
+#define EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+#define EFI_ACPI_OEM_HMAT_REVISION 0x00000001
+
+#define EFI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T')
+#define MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE 0
+#define SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TYPE 1
+#define MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE 2
+
+#define EFI_ACPI_HMAT_MSARS_COUNT (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE)
+#define EFI_ACPI_HMAT_LBIS_COUNT (EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES * MAX_HMAT_MEMORY_HIERACHY_LEVELS)
+#define EFI_ACPI_HMAT_MSCIS_COUNT (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE)
+
+
+#define HMAT_BW_BASE_UNIT 1024 // 1024 MB/S
+#define HMAT_LATENCY_BASE_UNIT 1 // 1ns
+
+#define HBM_4_NODES_CASE 4
+#define HBM_2_NODES_CASE 2
+#define HBM_1_NODE_CASE 1
+
+//
+// In HBM as Cache mode, Cache Flags are only for Last Level of Cache (Flags = 1), and 1st Level of Cache (Flags = 2).
+// So Flag = 0 should be skipped.
+//
+#define HMAT_HBM_CACHE_FLAG_OFFSET 1
+
+#pragma pack(1)
+typedef enum {
+ TypeFlatMemoryMode = 1,
+ TypeCacheMemoryMode = 2,
+ TypeHybridMemoryMode = 3,
+} LBIS_MEMORY_FLAGS_TYPE;
+
+typedef struct {
+ UINT8 Valid;
+ UINT32 ElementId;
+ UINT64 MemMapIndexMap;
+ UINT8 Cacheable;
+ UINT64 MemorySideCacheSize;
+ UINT16 NumSmbiosHandles;
+ UINT16 SmbiosHandles[MAX_TYPE17_CACHE_DEVICES];
+ UINT8 PhysicalSocketId;
+} MEMORY_DOMAIN_LIST_INFO;
+
+typedef struct {
+ UINT32 ProcessorDomainNumber;
+ UINT32 MemoryDomainNumber;
+ UINT16 ProcessorDomainList [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS];
+ MEMORY_DOMAIN_LIST_INFO MemoryDomainList [EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS];
+ UINT8 SncEnabled;
+ UINT8 SncNumOfCluster;
+ UINT8 VirtualNumaEnabled;
+ UINT8 VirtualNumOfCluster;
+ UINT8 ProcessorDomainSocketIdList [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS];
+} HMAT_PROXIMITY_DOMAIN_DATA_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 Reserved; // To make the structures 8 byte aligned
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+typedef struct {
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER HmatHeader;
+ MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE Msars[EFI_ACPI_HMAT_MSARS_COUNT];
+ LATENCY_BANDWIDTH_INFO_STRUCTURE Lbis[EFI_ACPI_HMAT_LBIS_COUNT];
+ MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT];
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+#pragma pack()
+
+#endif /* _HMAT_H_ */
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
new file mode 100644
index 0000000000..a3b9ef256a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
@@ -0,0 +1,43 @@
+/** @file
+ This file describes the contents of the ACPI High Precision Event Timer Description Table
+ HPET). Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h, and Acpi3_0.h
+ All changes to the HPET contents should be done in this file.
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _HPET_H_
+#define _HPET_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+
+//
+// HPET Definitions
+//
+#define EFI_ACPI_OEM_HPET_REVISION 0x00000001
+
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A701
+
+//
+// Event Timer Block Base Address Information
+//
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_MEMORY
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
+#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000
+
+#define EFI_ACPI_HPET_NUMBER 0x00
+
+#define EFI_ACPI_MIN_CLOCK_TICK 0x0080
+
+#define EFI_ACPI_HPET_ATTRIBUTES 0x00
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
new file mode 100644
index 0000000000..7277961baa
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
@@ -0,0 +1,58 @@
+/** @file
+ ACPI Memory mapped configuration space base address Description Table
+ implementation, based on PCI Firmware Specification Revision 3.0 final draft,
+ downloadable at http://www.pcisig.com/home
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MCFG_H_
+#define _MCFG_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include "Platform.h"
+//
+// "MCFG" Static Resource Affinity Table
+//
+#define EFI_ACPI_6_2_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D
+
+//
+// MCFG Definitions, see specification for details.
+//
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT MAX_SOCKET
+
+//
+// MCFG Table definition. The table must be defined in a platform
+// specific manner.
+//
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+
+#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Segment[
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT];
+#endif
+
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE;
+
+#pragma pack()
+
+#endif // _MCFG_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
new file mode 100644
index 0000000000..058ae67717
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
@@ -0,0 +1,57 @@
+/** @file
+ This file describes the contents of the MIGT ACPI table.
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MIGT_H_
+#define _MIGT_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// MIGT ACPI structure
+//
+typedef struct {
+
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ // MIGT Specific Entries
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ControlRegister;
+ UINT32 ControlRegisterValue;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ActionRegion;
+
+} EFI_MIGT_ACPI_DESCRIPTION_TABLE;
+
+
+//
+// MIGT ACPI Definitions
+//
+#define MIGT_SMI_SERVICE_ID 0xFD // Door Bell
+
+#define EFI_MIGT_ACPI_TABLE_SIGNATURE SIGNATURE_32('M','I','G','T')
+#define EFI_MIGT_ACPI_DESCRIPTION_TABLE_REVISION 0x01
+#define EFI_MIGT_ACPI_OEM_REVISION 0x00000000
+
+//
+// MIGT Control Register Generic Address Information
+//
+#define EFI_MIGT_CR_ACPI_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_MIGT_CR_ACPI_REGISTER_BIT_WIDTH 0x8
+#define EFI_MIGT_CR_ACPI_REGISTER_BIT_OFFSET 0x0
+#define EFI_MIGT_CR_ACPI_SMI_ADDRESS 0xB2
+
+//
+// MIGT Action Region Generic Address Information
+//
+#define EFI_MIGT_AR_ACPI_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_MEMORY
+#define EFI_MIGT_AR_ACPI_REGISTER_BIT_WIDTH 64
+#define EFI_MIGT_AR_ACPI_REGISTER_BIT_OFFSET 0x0
+#define EFI_MIGT_AR_ACPI_MEMORY_ADDRESS 0x0
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
new file mode 100644
index 0000000000..a088d66ea5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
@@ -0,0 +1,56 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MSARS_H_
+#define _MSARS_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#pragma pack(1)
+typedef struct {
+ UINT16 ProcessorDomainValid:1;
+ UINT16 MemoryDomainValid:1;
+ UINT16 ReservationHint:1;
+ UINT16 Reserved_15_3:13;
+} MSARS_FLAGS_BITS;
+
+typedef union {
+ UINT16 Value;
+ MSARS_FLAGS_BITS Bits;
+} MSARS_FLAGS;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Reserved_2_4;
+ UINT32 Length;
+ MSARS_FLAGS Flags;
+ UINT16 Reserved_10_12;
+ UINT32 ProcessorProximityDomain;
+ UINT32 MemoryProximityDomain;
+ UINT32 Reserved_20_24;
+ UINT64 AddrBase; //System Physical Address Range Base
+ UINT64 AddrLength; //System Physical Address Range Length
+} MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE;
+#pragma pack()
+
+// MSARS_INIT Macro
+// Used to initialize MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE
+#define MSARS_INIT() { \
+ (UINT16) MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE, \
+ (UINT16) 0, \
+ (UINT32) sizeof(MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE), \
+ {(UINT16) 0}, \
+ (UINT16) 0, \
+ (UINT32) 0, \
+ (UINT32) 0, \
+ (UINT32) 0, \
+ (UINT64) 0, \
+ (UINT64) 0, \
+ },
+
+#endif /* _MSARS_H_ */
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
new file mode 100644
index 0000000000..44d80910e2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
@@ -0,0 +1,84 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MSCIS_H_
+#define _MSCIS_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define EFI_ACPI_HMAT_CACHE_LEVEL_NONE 0
+#define EFI_ACPI_HMAT_ONE_LEVEL_CACHE 1
+#define EFI_ACPI_HMAT_TWO_LEVEL_CACHE 2
+#define EFI_ACPI_HMAT_THREE_LEVEL_CACHE 3
+
+#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_NONE 0
+#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_DIRECT_MAPPED 1
+#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_COIMPLEX_CACHE_INDEXING 2
+
+#define EFI_ACPI_HMAT_WRITE_POLICY_NONE 0
+#define EFI_ACPI_HMAT_WRITE_POLICY_WB 1
+#define EFI_ACPI_HMAT_WRITE_POLICY_WT 2
+
+#define HBM_CACHE_LINE_SIZE 72
+#define DDR4_CACHE_LINE_SIZE 64
+
+//
+// MAX_CH = MAX_IMC * MAX_MC_CH
+// MAX_IMC = Maximum memory controllers per socket
+// MAX_MC_CH = Max number of channels per MC
+// For each channel, 1 DDR can act as 2LM cache. This is the maximum number of cache devices per memory domain
+//
+#define MAX_TYPE17_CACHE_DEVICES MAX_CH
+
+#pragma pack(1)
+typedef struct {
+ UINT32 TotalCacheLevels:4;
+ UINT32 CacheLevel:4;
+ UINT32 CacheAssociativity:4;
+ UINT32 WritePolicy:4;
+ UINT32 CacheLineSize:16;
+} CACHE_ATTRIBUTES_BITS;
+
+typedef union {
+ UINT32 Data;
+ CACHE_ATTRIBUTES_BITS Bits;
+} CACHE_ATTRIBUTES;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Reserved_2_4;
+ UINT32 Length;
+ UINT32 MemoryProximityDomain;
+ UINT32 Reserved_12_16;
+ UINT64 MemorySideCacheSize;
+ CACHE_ATTRIBUTES CacheAttributes;
+ UINT16 Reserved_28_30;
+ UINT16 NumSmbiosHandles;
+ UINT16 SmbiosHandles [MAX_TYPE17_CACHE_DEVICES];
+} MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE;
+#pragma pack()
+
+// MSCIS_INIT Macro
+// Used to initialize MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE
+#define MSCIS_INIT() { \
+ (UINT16) MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE, \
+ (UINT16) 0, \
+ (UINT32) sizeof(MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE), \
+ (UINT32) 0, \
+ (UINT32) 0, \
+ (UINT64) 0, \
+ {(UINT32) 0}, \
+ (UINT16) 0, \
+ (UINT16) 0, \
+ },
+/*
+ SMBIOS handles not used for 2LM. Will be added for HBM
+ {(UINT16) 0}, \
+ },
+*/
+#endif /* _MSCIS_H_ */
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
new file mode 100644
index 0000000000..31c6e0f580
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
@@ -0,0 +1,58 @@
+/** @file
+ This file describes the contents of the ACPI Maximum System Characteristics Table (MSCT).
+ Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h, and Acpi3_0.h.
+ All changes to the MSCT contents should be done in this file.
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _MSCT_H_
+#define _MSCT_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+#include <Platform.h>
+#include <UncoreCommonIncludes.h>
+
+//
+// MSCT Definitions, see specification for details.
+//
+#ifndef EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE 0x5443534D
+#endif
+#define EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+#define EFI_ACPI_OEM_MSCT_REVISION 0x00000001
+#define EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION 0x01
+
+
+//
+// MSCT Table definition
+//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Revision;
+ UINT8 Length;
+ UINT32 ProxDomRangeLow;
+ UINT32 ProxDomRangeHigh;
+ UINT32 MaxProcessorCapacity;
+ UINT64 MaxMemoryCapacity;
+} EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 OffsetProxDomInfo;
+ UINT32 MaxNumProxDom;
+ UINT32 MaxNumClockDom;
+ UINT64 MaxPhysicalAddress;
+ EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE ProxDomInfoStructure[MAX_SOCKET];
+} EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE;
+
+#pragma pack()
+
+#endif //_MSCT_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
new file mode 100644
index 0000000000..5ea51b6d59
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
@@ -0,0 +1,50 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// The version of NvDimm F/W Interface Table (Nfit) supported has been updated to ASWG-ECR-Draft4-RC6_93.doc
+// This file contains definitions for Acpi side for the Nfit creation and publication of Nfit tables.
+// A BIG NOTE: When ever the NVDIMM_FW_INTERFACE_TABLE defined either here or what is in Nfit.h of CrystalRidge Protocol driver
+// changes, the same changes need to relect in both the files.
+
+#ifndef _NFIT_DEFS_H_
+#define _NFIT_DEFS_H_
+
+#include <IndustryStandard/Acpi62.h>
+
+#define NVDIMM_FW_INTERFACE_TABLE_SIGNATURE EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE
+#define NVDIMM_FW_INTERFACE_TABLE_REVISION EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION
+
+#define MAX_NFIT_SIZE 0x18000
+
+
+//
+// NVDIMM Firmware Interface Table struct
+// IMPORTANT NOTE: Num of various sub-table fields of the Nfit has been eliminated in the latest Nfit Spec (0.8k)
+// And also since there is NO memory allocation scheme for Nfit (all globals), Adding a buffer NfitTables with the,
+// max nfit size currently set to 4k. Will need to watch if we will ever overrun this buffer. It is expected that
+// Nfit parser will need to parse the NfitTables field to understand the various other Nfit Tables in this buffer
+// based on the Type and Length field of these tables.
+//
+#pragma pack(1)
+typedef struct _NVDIMM_FW_INT_TBL {
+ UINT32 Signature; // 'NFIT' should be the signature for this table
+ UINT32 Length; // Length in bytes fir the entire table
+ UINT8 Revision; // Revision # of this table, initial is '1'
+ UINT8 Checksum; // Entire Table Checksum must sum to 0
+ UINT8 OemID[6]; // OemID
+ UINT8 OemTblID[8]; // Should be Manufacturer's Model #
+ UINT32 OemRevision; // Oem Revision of for Supplied OEM Table ID
+ UINT32 CreatorID; // Vendor ID of the utility that is creating this table
+ UINT32 CreatorRev; // Revision of utility that is creating this table
+ UINT32 Reserved;
+ UINT8 NfitTables[MAX_NFIT_SIZE]; // See Description above (IMPORTANT).
+} NVDIMM_FW_INTERFACE_TABLE;
+#pragma pack()
+
+#endif // _NFIT_DEFS_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
new file mode 100644
index 0000000000..ceb0684f17
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
@@ -0,0 +1,45 @@
+/** @file
+ Pcat.h
+
+ @copyright
+ Copyright 2014 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCAT_DEFS_H_
+#define _PCAT_DEFS_H_
+
+#include <Uefi/UefiBaseType.h>
+
+/// @brief PCAT Signature to put in table header
+#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'A', 'T')
+
+#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_REVISION 0x11
+
+#define MAX_PCAT_SIZE 0x200
+
+typedef struct {
+ UINT32 Signature; // 'PCAT' should be the signature for this table
+ UINT32 Length; // Length in bytes for the entire table
+ UINT8 Revision; // Revision # of this table, initial is '1'
+ UINT8 Checksum; // Entire Table Checksum must sum to 0
+ UINT8 OemID[6]; // OemID
+ UINT8 OemTblID[8]; // Should be Manufacturer's Model #
+ UINT32 OemRevision; // Oem Revision of for Supplied OEM Table ID
+ UINT32 CreatorID; // Vendor ID of the utility that is creating this table
+ UINT32 CreatorRev; // Revision of utility that is creating this table
+ UINT32 Reserved; // Alignement for size modulo 8 = 0
+ UINT8 PCATTables[MAX_PCAT_SIZE];
+} NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE, *PNVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE;
+
+/// @brief Layout of SSKU Attribute Extension Table header
+typedef struct {
+ UINT16 Type; // Type for Mgmt Info Struct, type should be 3
+ UINT16 Length; // Length in Bytes for Entire SSKU Attribute Extension Table size.
+ UINT16 Rsvd;
+ UINT16 VendorID; // Vendor ID
+ EFI_GUID Guid; // Intel defined SSKU Attribute Extension Table. guid: F93032E5-B045-40ef-91C8-F02B06AD948D
+} NVDIMM_SSKU_ATTR_EXT_TABLE, *PNVDIMM_SSKU_ATTR_EXT_TABLE;
+
+#endif //_PCAT_DEFS_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
new file mode 100644
index 0000000000..923483f2da
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
@@ -0,0 +1,120 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_PMTT_H_
+#define _ACPI_PMTT_H_
+
+//
+// Includes
+//
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SmBios.h>
+#include <Platform.h>
+#include <UncoreCommonIncludes.h>
+
+//
+// PMTT Definitions
+//
+#define ACPI_PMTT_TABLE_SIGNATURE 0x54544D50
+#define ACPI_PMTT_TABLE_REVISION 0x02
+#define ACPI_PMTT_OEM_REVISION 1
+
+#define PMTT_TOP_LEVEL_AGGREGATOR_DEVICE 0x0001
+#define PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY 0x0002
+#define PMTT_AEP_DIMM 0x0004
+
+#define ACPI_TOP_LEVEL_SOCKET 0x00
+#define ACPI_TOP_LEVEL_IMC 0x01
+#define PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM 0x02
+#define ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE 0xFF
+
+// PMTT GUID variables
+#define PMTT_TYPE_DIE_GUID { 0xA2555053, 0xCDE4, 0x40A5, {0x80, 0x76, 0x00, 0xE3, 0xAB, 0xA6, 0xCA, 0xA7} }
+#define PMTT_TYPE_CHANNEL_GUID { 0x23BF9281, 0xE69c, 0x471F, {0xB2, 0x99, 0xB0, 0x98, 0x2B, 0x2F, 0x55, 0xF9} }
+#define PMTT_TYPE_SLOT_GUID { 0xFDCB2a68, 0xC203, 0x4312, {0xB2, 0x91, 0xB8, 0xE8, 0x62, 0x86, 0xC2, 0xC1} }
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ UINT32 SmbiosHandle;
+} ACPI_PMTT_DIMM_DEVICE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ GUID TypeUuid;
+ UINT16 SlotId;
+ UINT16 Rsvd2;
+ ACPI_PMTT_DIMM_DEVICE Dimm;
+} ACPI_PMTT_SLOT_DEVICE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ GUID TypeUuid;
+ UINT16 ChannelId;
+ UINT16 Rsvd2;
+ ACPI_PMTT_SLOT_DEVICE Slot[MAX_DIMM];
+} ACPI_PMTT_CHANNEL_DEVICE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ UINT16 ImcId;
+ UINT16 Rsvd2;
+ ACPI_PMTT_CHANNEL_DEVICE Channel[MAX_MC_CH];
+} ACPI_PMTT_IMC_DEVICE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ GUID TypeUuid;
+ UINT16 DieId;
+ UINT16 Rsvd2;
+ ACPI_PMTT_IMC_DEVICE Imc[MAX_IMC];
+} ACPI_PMTT_DIE_DEVICE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Rsvd;
+ UINT16 Length;
+ UINT16 Flag;
+ UINT16 Rsvd1;
+ UINT32 NumOfMemoryDevices;
+ UINT16 SckIdent;
+ UINT16 Rsvd2;
+ ACPI_PMTT_DIE_DEVICE Die[MAX_DIE];
+} ACPI_PMTT_SOCKET_DEVICE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT32 NumOfMemoryDevices;
+ ACPI_PMTT_SOCKET_DEVICE Socket[MAX_SOCKET];
+} ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE;
+
+#endif // _ACPI_PMTT_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
new file mode 100644
index 0000000000..c119a0f712
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
@@ -0,0 +1,87 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2017 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLLBIS_H_
+#define _SLLBIS_H_
+
+#include <UncoreCommonIncludes.h>
+
+#define EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS MC_MAX_NODE
+#define EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE)
+
+#define EFI_ACPI_HMAT_MEMORY_HIERACHY_MEMORY 0
+#define EFI_ACPI_HMAT_MEMORY_HIERACHY_LAST_LEVEL_MEMORY 1
+#define EFI_ACPI_HMAT_MEMORY_HIERACHY_FIRST_LEVEL_MEMORY 2
+#define EFI_ACPI_HMAT_MEMORY_HIERACHY_SECOND_LEVEL_MEMORY 3
+#define EFI_ACPI_HMAT_MEMORY_HIERACHY_THIRD_LEVEL_MEMORY 4
+
+
+#define EFI_ACPI_HMAT_ACCESS_LATENCY 0
+#define EFI_ACPI_HMAT_READ_LATENCY 1
+#define EFI_ACPI_HMAT_WRITE_LATENCY 2
+#define EFI_ACPI_HMAT_ACCESS_BANDWIDTH 3
+#define EFI_ACPI_HMAT_READ_BANDWIDTH 4
+#define EFI_ACPI_HMAT_WRITE_BANDWIDTH 5
+
+#define EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES 4
+#define EFI_ACPI_HMAT_NUMBER_SLLBIS_DATA_TYPES 6
+
+#define EFI_ACPI_HMAT_ELEMENT_BASE_UNIT_VALUE 10
+
+#define MAX_HMAT_MEMORY_HIERACHY_LEVELS 3 // Flat, Cache, and Hybrid
+#define HMAT_PERFORMANCE_UNIFORM_ACCESS 1
+#define HMAT_PERFORMANCE_NONUNIFORM_ACCESS 0
+
+#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_LENGTH 4
+#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_START_BIT 4
+
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Reserved_2_4;
+ UINT32 Length;
+ UINT8 Flags;
+ UINT8 DataType;
+ UINT16 Reserved_10_12;
+ UINT32 InitiatorProximityDomainsNumber;
+ UINT32 TargetProximityDomainsNumber;
+ UINT32 Reserved_20_24;
+ UINT64 EntryBaseUnit;
+ UINT32 InitiatorProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS];
+ UINT32 TargetProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS];
+ UINT16 RelativeDistanceEntry[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS][EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS];
+} LATENCY_BANDWIDTH_INFO_STRUCTURE;
+#pragma pack()
+
+// LBIS Macros
+// Used to initialize LATENCY_BANDWIDTH_INFO_STRUCTURE
+#define LBIS_START() { \
+ (UINT16) SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TYPE, \
+ (UINT16) 0, \
+ (UINT32) sizeof(LATENCY_BANDWIDTH_INFO_STRUCTURE), \
+ (UINT8) 0, \
+ (UINT8) 0, \
+ (UINT16) 0, \
+ (UINT32) 0, \
+ (UINT32) 0, \
+ (UINT32) 0, \
+ (UINT64) 0, \
+ {(UINT32) 0}, \
+ {(UINT32) 0}, \
+ {
+
+#define RELATIVE_DISTANCE() \
+ {(UINT16) 0},
+
+#define LBIS_END() \
+ }, \
+},
+
+#endif /* _SLLBIS_H_ */
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
new file mode 100644
index 0000000000..90ea2c24cb
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
@@ -0,0 +1,48 @@
+/** @file
+ This file describes the contents of the ACPI Serial Port Console Redirection
+ Table (SPCR). Some additional ACPI 2.0 values are defined in Acpi2_0.h.
+ All changes to the Spcr contents should be done in this file.
+
+ @copyright
+ Copyright 1999 - 2002 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SPCR_H_
+#define _SPCR_H_
+
+//
+// SPCR Definitions, see TBD specification for details.
+//
+
+#define EFI_ACPI_OEM_SPCR_REVISION 0x00000000 // TBD
+
+#define EFI_ACPI_INTERFACE_TYPE 0x00 // full 16550 interface.
+
+//
+// Base Address
+//
+#define EFI_ACPI_BASE_ADDRESS_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO
+#define EFI_ACPI_BASE_ADDRESS_BIT_WIDTH 0x08
+#define EFI_ACPI_BASE_ADDRESS_BIT_OFFSET 0x00
+#define EFI_ACPI_BASE_ADDRESS_ADDRESS 0x0000000000000000 // Updated at run time
+
+#define EFI_ACPI_INTERRUPT_TYPE 0x03 // Dual-8259 and IOAPIC
+#define EFI_ACPI_IRQ 0x04 // Updated at run time
+#define EFI_ACPI_GLOBAL_SYSTEM_INTERRUPT 0x04 // Updated at run time
+#define EFI_ACPI_BAUD_RATE 0x07 // 115200
+#define EFI_ACPI_PARITY 0x00 // No parity
+#define EFI_ACPI_STOP_BITS 0x00 // 0 stop bit
+#define EFI_ACPI_FLOW_CONTROL 0x00 // No flow control
+#define EFI_ACPI_TERMINAL_TYPE 0x03 // ANSI
+#define EFI_ACPI_LANGUAGE 0x00 // Reserved
+#define EFI_ACPI_PCI_DEVICE_ID 0xFFFF
+#define EFI_ACPI_PCI_VENDOR_ID 0xFFFF
+#define EFI_ACPI_PCI_BUS_NUMBER 0x00
+#define EFI_ACPI_PCI_DEVICE_NUMBER 0x00
+#define EFI_ACPI_PCI_FUNCTION_NUMBER 0x00
+#define EFI_ACPI_PCI_FLAGS 0x00000000
+#define EFI_ACPI_PCI_SEGMENT 0x00
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
new file mode 100644
index 0000000000..576c390bd6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
@@ -0,0 +1,59 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SPMI_H_
+#define _SPMI_H_
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// Spmi Definitions, see specification for details.
+//
+#ifndef EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE
+#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053
+#endif
+
+#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION 0x05
+#define EFI_ACPI_OEM_SPMI_REVISION 0x00000001
+#define EFI_ACPI_SPMI_SPECIFICATION_REVISION 0x0200
+
+
+//
+// SPMI Table definition
+//
+#pragma pack(1)
+
+#define KEYBOARD_CONTROLLER_STYLE 0x01
+#define SYSTEM_IO 0x01
+#define IPMI_DEFAULT_IO_BASE 0xCA2
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 InterfaceType; // 36
+ UINT8 Reserved37; // 37
+ UINT16 SpecificationRevision; // 38 - 39
+ UINT8 InterruptType; // 40
+ UINT8 GPE; // 41
+ UINT8 Reserved42; // 42
+ UINT8 PciDeviceFlag; // 43
+ UINT32 GlobalSystemInterrupt; // 44 - 47
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; // 48 - 59
+ UINT8 UidByte1; // 60 LSB
+ UINT8 UidByte2; // 61
+ UINT8 UidByte3; // 62
+ UINT8 UidByte4; // 63 MSB
+ UINT8 Reserved64; // 64
+} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE;
+
+
+#pragma pack()
+
+#endif //_SPMI_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h
new file mode 100644
index 0000000000..fe25f5b4e3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h
@@ -0,0 +1,82 @@
+/** @file
+ ACPI Watchdog Description Table as defined in Intel
+ ICH Family Watchdog Timer (WDT) Application Note (AP-725)
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
+#define _WATCH_DOG_DESCRIPTION_TABLE_H_
+
+//
+// Include files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+//
+// WDDT structure ACPI 6.2 compliant
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT16 SpecVersion;
+ UINT16 TableVersion;
+ UINT16 Vid;
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ UINT16 TimerMaxCount;
+ UINT16 TimerMinCount;
+ UINT16 TimerCountPeriod;
+ UINT16 Status;
+ UINT16 Capability;
+} EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE;
+
+//
+// "WDDT" Watchdog Description Table signatures
+//
+#define EFI_ACPI_WDDT_SIGNATURE 0x54444457
+
+#pragma pack()
+
+//
+// WDDT Revision
+//
+#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01
+
+//
+// WDDT Spec Version
+//
+#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01
+
+//
+// WDDT Description Table Version
+//
+#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01
+
+//
+// WDT Status
+//
+#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
+#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
+#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
+#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
+#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
+#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
+
+//
+// WDT Capability
+//
+#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
+#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
+#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
+#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
+#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
new file mode 100644
index 0000000000..9ffe2c6e89
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
@@ -0,0 +1,53 @@
+/** @file
+ This file describes the contents of the ACPI Watchdog Description
+ Table (WDDT). Some additional ACPI values are defined in Acpi1_0.h and
+ Acpi2_0.h.
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _WDDT_H
+#define _WDDT_H
+
+//
+// Statements that include other files
+//
+#include <IndustryStandard/Acpi.h>
+
+//
+// WDDT Definitions, ACPI 6.2
+//
+#define EFI_ACPI_WDDT_DESCRIPTION_TABLE_REVISION 1
+#define EFI_ACPI_OEM_WDDT_REVISION 0x00000001
+#define EFI_ACPI_WDDT_SPEC_VERSION 0x0100
+#define EFI_ACPI_WDDT_TABLE_VERSION 0x0100
+#define EFI_ACPI_WDDT_TIMER_MAX_COUNT 0x003f
+#define EFI_ACPI_WDDT_TIMER_MIN_VALUE 0x0004
+#define EFI_ACPI_WDDT_TIMER_PERIOD_COUNT 600
+//
+// WDDT_STATUS bits
+//
+#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
+#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
+#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
+#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
+#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
+#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
+#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
+
+//
+// WDDT Capability bits
+//
+#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
+#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
+#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
+#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
+#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
+
+#pragma pack()
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
new file mode 100644
index 0000000000..112e162931
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
@@ -0,0 +1,67 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2020 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#ifndef _WSMT_H_
+#define _WSMT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// signature "WSMT"
+//
+
+#define ACPI_WSMT_SIGNATURE 0x544D5357
+#define ACPI_WSMT_LENGTH 40
+#define ACPI_OEM_WSMT_REVISION 0x00000000
+#define EFI_ACPI_WSMT_REVISION 0x00000001
+#define WSMT_PROTECTION_FLAG (BIT0 | BIT1 | BIT2 )
+
+
+#pragma pack(1)
+
+typedef union {
+ struct {
+ //
+ //BIT0:
+ //If set, expresses that for all synchronous SMM entries,
+ //SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
+ //
+ UINT32 FixedCommBuffers:1;
+ //
+ //BIT1: COMM_BUFFER_NESTED_PTR_PROTECTION
+ //If set, expresses that for all synchronous SMM entries, SMM will validate that input and
+ //output pointers embedded within the fixed communication buffer only refer to address ranges
+ //that lie entirely within the expected fixed memory regions.
+ //
+ UINT32 CommBufferNestedPointerProtection:1;
+ //
+ //BIT2: SYSTEM_RESOURCE_PROTECTION
+ //Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
+ //
+ UINT32 SystemResourceProtection:1;
+ UINT32 Reserved:29;
+ } Bits;
+ UINT32 Flags;
+} EFI_ACPI_WSMT_PROTECTION_FLAGS;
+
+//
+// WSMT ACPI table
+//
+typedef struct _ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_WSMT_PROTECTION_FLAGS ProtectionFlags;
+} ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE;
+
+#pragma pack()
+
+#endif //_WSMT_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
index 5e27d9beb4..4d416325ae 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -16,8 +16,8 @@
PACKAGE_VERSION = 0.91
[Includes]
- Include
- Include/Protocol
+ Include
+ Include/Protocol
#TODO: Move these generated temp files into include.
Uba/BoardInit/Dxe
@@ -159,8 +159,7 @@
[PcdsFixedAtBuild]
-#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used here to it, or move these values to the SocketPkg where the GUID is defined
-# Using a GUID defined in another .DEC file is a violation of the UEFI packaging standards.
+ gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress|0x00000500|UINT32|0x00000031
gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E
gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
index 0ea93e9a78..7af4eb72f6 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
@@ -80,6 +80,8 @@
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
#endif
+#define MAX_CRS_ENTRIES_PER_NODE 8 // Max number of ranges allowed on a memory node
+
#ifndef TOTAL_CB3_DEVICES
#define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKET. Note: this covers up to 8S.
#endif
@@ -108,4 +110,10 @@
#define MAX_B2P_MAILBOX_GROUPS 32
#endif // !MAX_B2P_MAILBOX_GROUPS
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL"
+#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009
+
#endif
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3 Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables Oram, Isaac W
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
LBG ACPI DSDT content
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl | 833 ++++++++++++++++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl | 307 ++++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl | 271 +++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl | 203 +++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl | 50 ++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl | 558 +++++++++++++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl | 150 ++++
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 1 +
28 files changed, 2673 insertions(+)
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl
new file mode 100644
index 0000000000..a8ea35534c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl
@@ -0,0 +1,833 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Register/PchRegsPcr.h>
+
+Name (PNVB, 0xFFFF0000) // PCH NVS Base address
+Name (PNVL, 0xAA55) // PCH NVS Length
+Include ("PchNvs.asl")
+
+//
+// Trace Hub debug library
+// Include it earlier so the debug function can be used as soon as possible
+//
+Include ("TraceHubDebug.asl")
+
+Name(SPTH,1)
+Name(SPTL,2)
+Method(PCHV) {
+ If(LEqual(PCHS, 1)) { Return (SPTH) } // series=H -> SPT-H
+ If(LEqual(PCHS, 2)) { Return (SPTL) } // series=LP -> SPT-LP
+ Return (0)
+}
+
+//
+// This PME event (PCH's GPE 6Dh) is received when any PCH internal device with
+// PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal.
+//
+Scope(\_GPE) {
+ Method(_L6D, 0, Serialized) {
+ \_SB.PC00.XHCI.GPEH()
+ \_SB.PC00.CAVS.GPEH()
+ \_SB.PC00.GBE1.GPEH()
+ }
+}
+
+Scope (\_SB.PC00) {
+
+ //
+ // PCH reserved resource
+ //
+ Device(PRRE) {
+ Name(_HID,EISAID("PNP0C02")) // motherboard resource
+ Name(_UID,"PCHRESV")
+ Name(_STA,0x3) // device present and decodes its resources, but not to be displayed in OSPM
+
+ Method(_CRS,0,Serialized)
+ {
+ Name(BUF0,ResourceTemplate(){
+ //
+ // PCH RESERVED MMIO RANGE
+ // 0xFD000000 to 0xFE7FFFFF
+ // to skip over address range that might be claimed by the GPIO, Intel Serial IO, Thermal, TraceHub and CIO2 devices
+ // need to split this into 5 ranges
+ // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC device.
+ //
+ Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 - 0xFDABFFFF
+ // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3
+ Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 - 0xFDADFFFF, only cover GPIO_COMM2 range
+ // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1
+ Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 - 0xFDFFFFFF
+ Memory32Fixed(ReadWrite,0xFE000000,0x00010000) // 0xFE000000 - 0xFE00FFFF
+ Memory32Fixed(ReadWrite,0xFE011000,0x0000f000) // 0xFE011000 - 0xFE01FFFF
+ // Skip 0xFE020000 - 0xFE035FFF for Serial IO
+ Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 - 0xFE03BFFF
+ // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode
+ Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 - 0xFE3FFFFF
+ // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode
+ Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 - 0xFE7FFFFF
+ })
+ Return(BUF0)
+ }
+ }
+ Device(IOTR) {
+ //
+ // This device claims IO range reserved for IO traps
+ // to prevent OS from reusing it for other purposes
+ //
+ Name(_HID,EISAID("PNP0C02"))
+ Name(_UID,"IoTraps")
+ Name(BUF0,ResourceTemplate(){
+ Io(Decode16,0x0,0x0,0x1,0xFF,TAG0)
+ Io(Decode16,0x0,0x0,0x1,0xFF,TAG1)
+ Io(Decode16,0x0,0x0,0x1,0xFF,TAG2)
+ Io(Decode16,0x0,0x0,0x1,0xFF,TAG3)
+ })
+ CreateWordField(BUF0,TAG0._MIN,AMI0)
+ CreateWordField(BUF0,TAG0._MAX,AMA0)
+ CreateWordField(BUF0,TAG1._MIN,AMI1)
+ CreateWordField(BUF0,TAG1._MAX,AMA1)
+ CreateWordField(BUF0,TAG2._MIN,AMI2)
+ CreateWordField(BUF0,TAG2._MAX,AMA2)
+ CreateWordField(BUF0,TAG3._MIN,AMI3)
+ CreateWordField(BUF0,TAG3._MAX,AMA3)
+ CreateByteField(BUF0,TAG0._LEN,LEN0)
+ CreateByteField(BUF0,TAG1._LEN,LEN1)
+ CreateByteField(BUF0,TAG2._LEN,LEN2)
+ CreateByteField(BUF0,TAG3._LEN,LEN3)
+ Method(_CRS) {
+ Store(ITA0,AMI0);Store(ITA0,AMA0)
+ Store(ITA1,AMI1);Store(ITA1,AMA1)
+ Store(ITA2,AMI2);Store(ITA2,AMA2)
+ Store(ITA3,AMI3);Store(ITA3,AMA3)
+ if(LNotEqual(ITS0,1)) { Store(0, LEN0) }
+ if(LNotEqual(ITS1,1)) { Store(0, LEN1) }
+ if(LNotEqual(ITS2,1)) { Store(0, LEN2) }
+ if(LNotEqual(ITS3,1)) { Store(0, LEN3) }
+ return (BUF0)
+ }
+ }
+
+
+ //
+ // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory Region declare,
+ // it's better to be declared as early as possible since it's widely used in whole ACPI name space.
+ // Please add any code which needs to reference any register of it after this
+ //
+ Scope (\_SB.PC00.LPC0) {
+ Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
+
+ OperationRegion(LPC, PCI_Config, 0x00, 0x100)
+ Field(LPC, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x02),
+ CDID, 16,
+ Offset(0x08),
+ CRID, 8,
+ Offset(0x80),
+ IOD0, 8,
+ IOD1, 8,
+ Offset(0xA0),
+ , 9,
+ PRBL, 1,
+ Offset(0xAC),
+ , 8,
+ , 8,
+ XUSB, 1,
+ Offset(0xB8),
+ , 22,
+ GR0B, 2,
+ , 8,
+ Offset(0xBC),
+ , 2,
+ GR19, 2,
+ , 28,
+ Offset(0xDC),
+ , 2,
+ ESPI, 1,
+ }
+ }
+
+ //
+ // PCH Power Management Controller
+ //
+ Scope(\_SB.PC00.PMC1) {
+ Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
+
+ OperationRegion(PMCB, PCI_Config, 0x00, 0x100)
+ Field(PMCB, AnyAcc, NoLock, Preserve) {
+ VDID, 32,
+ Offset(0x40),
+ , 8,
+ ACBA, 8,
+ Offset(0x48),
+ , 12,
+ PWBA, 20,
+ }
+ }
+
+ //
+ // SMBus Controller - Device 31, Function 4
+ //
+ Device(SBUS) {
+ Name(_ADR,0x001F0004)
+ Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
+ }
+}
+
+Scope(\)
+{
+ //
+ // PCR Register Access Methods
+ //
+ // PCR Dword Read
+ // arg0: PID
+ // arg1: Offset
+ //
+ Method (PCRR, 2, Serialized) {
+ Add (ShiftLeft (arg0, 16), arg1, Local0)
+ Add (SBRG, Local0, Local0)
+ OperationRegion (PCR0, SystemMemory, Local0, 0x4)
+ Field(PCR0,DWordAcc,Lock,Preserve) {
+ Offset(0x00),
+ DAT0, 32
+ } // End Field PCR0
+ Return (DAT0)
+ } // End Method PCRR
+
+ //
+ // PCR Dword Write
+ // arg0: PID
+ // arg1: Offset
+ // arg2: write data
+ //
+ Method (PCRW, 3, Serialized) {
+ Add (ShiftLeft (arg0, 16), arg1, Local0)
+ Add (SBRG, Local0, Local0)
+ OperationRegion (PCR0, SystemMemory, Local0, 0x4)
+ Field(PCR0,DWordAcc,Lock,Preserve) {
+ Offset(0x00),
+ DAT0, 32
+ } // End Field PCR0
+ Store (arg2, DAT0)
+
+ // read back for PCR back to back limitation
+ OperationRegion (PCR1, SystemMemory, ADD (SBRG, 0x00C73418), 0x4)
+ Field(PCR1,DWordAcc,Lock,Preserve) {
+ Offset(0x00),
+ DAT1, 32
+ } // End Field PCR1
+ } // End Method PCRW
+
+ //
+ // PCR Dword Or
+ // arg0: PID
+ // arg1: Offset
+ // arg2: Or data
+ //
+ Method (PCRO, 3, Serialized) {
+ Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
+ Store(Or(Local0,arg2),Local1) // Or data
+ PCRW(arg0,arg1,Local1) // Write data back
+ }
+
+ //
+ // PCR Dword And
+ // arg0: PID
+ // arg1: Offset
+ // arg2: And data
+ //
+ Method (PCRA, 3, Serialized) {
+ Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
+ Store(And(Local0,arg2),Local1) // And data
+ PCRW(arg0,arg1,Local1) // Write data back
+ }
+
+ //
+ // PCR Dword AndThenOr
+ // arg0: PID
+ // arg1: Offset
+ // arg2: And data
+ // arg3: Or data
+ //
+ Method (PCAO, 4, Serialized) {
+ Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
+ Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr
+ PCRW(arg0,arg1,Local1) // Write data back
+ }
+
+ Name (PMBV, 0) // ACPI I/O base address value
+ Method (PMB1, 0) {
+ If (LEqual(PMBV, 0)) {
+ Store (ShiftLeft (\_SB.PC00.PMC1.ACBA, 8), PMBV)
+ }
+ Return (PMBV)
+ }
+
+ Name (PWRV, 0) // PWRM base address value
+ Method (PWRM, 0) {
+ If (LEqual(PWRV, 0)) {
+ Store (ShiftLeft (\_SB.PC00.PMC1.PWBA, 12), PWRV)
+ }
+ Return (PWRV)
+ }
+
+
+ //
+ // Define PCH ACPIBASE I/O as an ACPI operating region. The base address
+ // can be found in Device 31, Function 2, Offset 40h.
+ //
+ OperationRegion(PMIO, SystemIo, PMB1, 0x80)
+ Field(PMIO, ByteAcc, NoLock, Preserve) {
+ , 8,
+ PBSS, 1, // Power Button Status
+ Offset(0x40), // General Purpose Event Control
+ , 17,
+ GPEC, 1 // Software GPE Control
+ }
+ OperationRegion(PMLP, SystemIo, Add(\PMB1,0x80), 0x20)
+ Field(PMLP, ByteAcc, NoLock, Preserve) {
+ Offset(0x10), // GPE0 Enable
+ , 8,
+ GE08, 1,
+ , 8,
+ GE17, 1,
+ , 17,
+ GE35, 1,
+ , 9,
+ GE45, 1,
+ , 2,
+ GE48, 1,
+ , 2,
+ GE51, 1,
+ , 76,
+ }
+ Field(PMLP, ByteAcc, NoLock, WriteAsZeros) {
+ Offset(0x00), // GPE0 Status
+ , 8,
+ GS08, 1,
+ , 8,
+ GS17, 1,
+ , 17,
+ GS35, 1,
+ , 9,
+ GS45, 1,
+ , 2,
+ GS48, 1,
+ , 2,
+ GS51, 1,
+ , 2,
+ GS54, 1,
+ GS55, 1,
+ , 42,
+ GS98, 1,
+ , 29,
+ }
+
+
+
+ //
+ // PWRM register definitions
+ //
+ OperationRegion(PWMR, SystemMemory, \PWRM, 0x800)
+ Field(PWMR, AnyAcc, NoLock, Preserve) {
+ Offset(0x0E0),
+ , 16,
+ DWLE, 1, // Deep-Sx WLAN Phy Power Enable
+ HWLE, 1, // Host Wireless LAN Phy Power Enable
+ }
+
+ //
+ //
+ OperationRegion(PMST, SystemMemory, PWRV, 0x80)
+ Field(PMST, DWordAcc, NoLock, Preserve) {
+ Offset(0x18), // Power Management Configuration Reg 1 (PM_CFG)
+ , 25, //
+ USBP, 1, // Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG)
+ Offset(0x1C), // PCH Power Management Status (PCH_PM_STS)
+ , 24, //
+ PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS)
+ Offset(0x20), // Message to PMC (MTPMC)
+ MPMC, 32, // Message to PMC (MTPMC)
+ Offset(0x24), // PCH Power Management Status (PCH_PM_STS2)
+ , 20, //
+ UWAB, 1, // USB2 Workaround Available Bit
+ }
+
+} //end Scope(\)
+
+Scope (\_SB.PC00) {
+ Name(LTRN, 0)
+ Name(OBFN, 0)
+
+ Name(LMSL, 0)
+ Name(LNSL, 0)
+
+ //
+ // LAN Controller - Device 31, Function 6
+ //
+ Scope(\_SB.PC00.GBE1) {
+ Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
+ OperationRegion(GLBA, PCI_Config, 0,0x100)
+ Field(GLBA,AnyAcc,NoLock,Preserve)
+ {
+ DVID, 16,
+ Offset(0xCC),
+ , 8,
+ PMEE, 1, // PME Enable
+ , 6,
+ PMES, 1, // PME Status
+ }
+
+ Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state
+
+ Method(_DSW, 3)
+ {
+ Store(Arg0, PMEE)
+ }
+
+ //
+ // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME
+ //
+ Method(GPEH)
+ {
+ If(LEqual(DVID, 0xFFFF)) {
+ Return()
+ }
+ If(LAnd(PMEE, PMES)) {
+ Store(1, PMES) // clear PME Status
+ Notify(GBE1, 0x02)
+ }
+ }
+ } // end "GbE Controller"
+
+} //scope
+
+//
+// xHCI Controller - Device 20, Function 0
+//
+Include("PchXhci.asl")
+
+// xDCI (OTG) Controller is not used in Server
+// Comment out as ifdefs don't work at Trim stage of ASL preparation
+
+Scope(\_SB_.PC00) {
+ //
+ // High Definition Audio Controller - Device 31, Function 3
+ //
+ include("PchHda.asl")
+
+ //
+ // PCIE Root Port #01
+ //
+ Scope(\_SB.PC00.RP01) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR1, LTRN)
+ Store (PML1, LMSL)
+ Store (PNL1, LNSL)
+ Store (OBF1, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #01"
+
+ //
+ // PCIE Root Port #02
+ //
+ Scope(\_SB.PC00.RP02) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR2, LTRN)
+ Store (PML2, LMSL)
+ Store (PNL2, LNSL)
+ Store (OBF2, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #02"
+
+ //
+ // PCIE Root Port #03
+ //
+ Scope(\_SB.PC00.RP03) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR3, LTRN)
+ Store (PML3, LMSL)
+ Store (PNL3, LNSL)
+ Store (OBF3, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #03"
+
+ //
+ // PCIE Root Port #04
+ //
+ Scope(\_SB.PC00.RP04) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR4, LTRN)
+ Store (PML4, LMSL)
+ Store (PNL4, LNSL)
+ Store (OBF4, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #04"
+
+ //
+ // PCIE Root Port #05
+ //
+ Scope(\_SB.PC00.RP05) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR5, LTRN)
+ Store (PML5, LMSL)
+ Store (PNL5, LNSL)
+ Store (OBF5, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #05"
+
+ //
+ // PCIE Root Port #06
+ //
+ Scope(\_SB.PC00.RP06) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR6, LTRN)
+ Store (PML6, LMSL)
+ Store (PNL6, LNSL)
+ Store (OBF6, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #06"
+
+ //
+ // PCIE Root Port #07
+ //
+ Scope(\_SB.PC00.RP07) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR7, LTRN)
+ Store (PML7, LMSL)
+ Store (PNL7, LNSL)
+ Store (OBF7, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #07"
+
+ //
+ // PCIE Root Port #08
+ //
+ Scope(\_SB.PC00.RP08) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR8, LTRN)
+ Store (PML8, LMSL)
+ Store (PNL8, LNSL)
+ Store (OBF8, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #08"
+
+ //
+ // PCIE Root Port #09
+ //
+ Scope(\_SB.PC00.RP09) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTR9, LTRN)
+ Store (PML9, LMSL)
+ Store (PNL9, LNSL)
+ Store (OBF9, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #09"
+
+ //
+ // PCIE Root Port #10
+ //
+ Scope(\_SB.PC00.RP10) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRA, LTRN)
+ Store (PMLA, LMSL)
+ Store (PNLA, LNSL)
+ Store (OBFA, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #10"
+
+ //
+ // PCIE Root Port #11
+ //
+ Scope(\_SB.PC00.RP11) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRB, LTRN)
+ Store (PMLB, LMSL)
+ Store (PNLB, LNSL)
+ Store (OBFB, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #11"
+
+ //
+ // PCIE Root Port #12
+ //
+ Scope(\_SB.PC00.RP12) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRC, LTRN)
+ Store (PMLC, LMSL)
+ Store (PNLC, LNSL)
+ Store (OBFC, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #12"
+
+ //
+ // PCIE Root Port #13
+ //
+ Scope(\_SB.PC00.RP13) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRD, LTRN)
+ Store (PMLD, LMSL)
+ Store (PNLD, LNSL)
+ Store (OBFD, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #13"
+
+ //
+ // PCIE Root Port #14
+ //
+ Scope(\_SB.PC00.RP14) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRE, LTRN)
+ Store (PMLE, LMSL)
+ Store (PNLE, LNSL)
+ Store (OBFE, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #14"
+
+ //
+ // PCIE Root Port #15
+ //
+ Scope(\_SB.PC00.RP15) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRF, LTRN)
+ Store (PMLF, LMSL)
+ Store (PNLF, LNSL)
+ Store (OBFF, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #15"
+
+ //
+ // PCIE Root Port #16
+ //
+ Scope(\_SB.PC00.RP16) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRG, LTRN)
+ Store (PMLG, LMSL)
+ Store (PNLG, LNSL)
+ Store (OBFG, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #16"
+
+ //
+ // PCIE Root Port #17
+ //
+ Scope(\_SB.PC00.RP17) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRH, LTRN)
+ Store (PMLH, LMSL)
+ Store (PNLH, LNSL)
+ Store (OBFH, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #17"
+
+ //
+ // PCIE Root Port #18
+ //
+ Scope(\_SB.PC00.RP18) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRI, LTRN)
+ Store (PMLI, LMSL)
+ Store (PNLI, LNSL)
+ Store (OBFI, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #18"
+
+ //
+ // PCIE Root Port #19
+ //
+ Scope(\_SB.PC00.RP19) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRJ, LTRN)
+ Store (PMLJ, LMSL)
+ Store (PNLJ, LNSL)
+ Store (OBFJ, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #19"
+
+ //
+ // PCIE Root Port #20
+ //
+ Scope(\_SB.PC00.RP20) {
+ //
+ // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
+ //
+ Method(_INI)
+ {
+ Store (LTRK, LTRN)
+ Store (PMLK, LMSL)
+ Store (PNLK, LNSL)
+ Store (OBFK, OBFN)
+ }
+ Include("PchPcie.asl")
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ } // end "PCIE Root Port #20"
+
+ //
+ // Serial ATA Host Controller - Device 31, Function 2
+ //
+External(\_SB.PC00.SAT0.SDSM, MethodObj)
+
+Scope (\_SB.PC00.SAT1) {
+ Include ("PchSata.asl")
+ Device(PRT6)
+ {
+ Name(_ADR,0x0006FFFF) // Port 6
+ }
+ Device(PRT7)
+ {
+ Name(_ADR,0x0007FFFF) // Port 7
+ }
+}
+Scope (\_SB.PC00.SAT2) {
+ Include ("PchSata.asl")
+}
+ //Server does not support CIO Camera I/O
+
+ //
+ // Thermal Device
+ //
+ Scope(\_SB.PC00.TERM) {
+ Name (_HID, "INT3536")
+ Name (_UID, 1)
+ Name (RBUF, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFE03C000, 0x00001000, BAR0)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { 18 }
+ })
+
+ CreateDWordField(RBUF,IRQ._INT,IRQN)
+ Method (_CRS, 0x0, NotSerialized) {
+ Store(TIRQ, IRQN)
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI mode
+ If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated
+ Return(0xF)
+ }
+ }
+}
+
+// Comment out as ifdefs don't work at Trim stage of ASL preparation
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl
new file mode 100644
index 0000000000..ab5b5c42dd
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl
@@ -0,0 +1,307 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Bit Difinitions
+//
+#ifndef BIT0
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#endif //BIT0
+
+//
+// High Definition Audio Controller - Device 31, Function 3
+//
+Scope(\_SB.PC00.CAVS) {
+
+#ifndef BIT0
+#define BIT0 0x00000001
+#endif
+#ifndef BIT1
+#define BIT1 0x00000002
+#endif
+#ifndef BIT2
+#define BIT2 0x00000004
+#endif
+#ifndef BIT3
+#define BIT3 0x00000008
+#endif
+#ifndef BIT4
+#define BIT4 0x00000010
+#endif
+#ifndef BIT5
+#define BIT5 0x00000020
+#endif
+#ifndef BIT6
+#define BIT6 0x00000040
+#endif
+#ifndef BIT7
+#define BIT7 0x00000080
+#endif
+#ifndef BIT8
+#define BIT8 0x00000100
+#endif
+#ifndef BIT9
+#define BIT9 0x00000200
+#endif
+#ifndef BIT10
+#define BIT10 0x00000400
+#endif
+#ifndef BIT11
+#define BIT11 0x00000800
+#endif
+#ifndef BIT12
+#define BIT12 0x00001000
+#endif
+#ifndef BIT13
+#define BIT13 0x00002000
+#endif
+#ifndef BIT14
+#define BIT14 0x00004000
+#endif
+#ifndef BIT15
+#define BIT15 0x00008000
+#endif
+#ifndef BIT16
+#define BIT16 0x00010000
+#endif
+#ifndef BIT17
+#define BIT17 0x00020000
+#endif
+#ifndef BIT18
+#define BIT18 0x00040000
+#endif
+#ifndef BIT19
+#define BIT19 0x00080000
+#endif
+#ifndef BIT20
+#define BIT20 0x00100000
+#endif
+#ifndef BIT21
+#define BIT21 0x00200000
+#endif
+#ifndef BIT22
+#define BIT22 0x00400000
+#endif
+#ifndef BIT23
+#define BIT23 0x00800000
+#endif
+#ifndef BIT24
+#define BIT24 0x01000000
+#endif
+#ifndef BIT25
+#define BIT25 0x02000000
+#endif
+#ifndef BIT26
+#define BIT26 0x04000000
+#endif
+#ifndef BIT27
+#define BIT27 0x08000000
+#endif
+#ifndef BIT28
+#define BIT28 0x10000000
+#endif
+#ifndef BIT29
+#define BIT29 0x20000000
+#endif
+#ifndef BIT30
+#define BIT30 0x40000000
+#endif
+#ifndef BIT31
+#define BIT31 0x80000000
+#endif
+
+ //
+ // Define a Memory Region that will allow access to the HDA PCI Configuration Space
+ //
+ OperationRegion(HDAR, PCI_Config, 0x00, 0x100)
+ Field(HDAR,WordAcc,NoLock,Preserve) {
+ VDID,32, // 0x00, VID DID
+ Offset(0x48), // 0x48, CGCTL - Clock Gating Control
+ ,6,
+ MBCG,1, // MISCBDCGE [BIT6]
+ Offset(0x54), // 0x54, Power Management Control and Status Register
+ ,8,
+ PMEE,1,
+ ,6,
+ PMES,1 // PME Status
+ }
+
+ Name(_S0W, 3) // Device can wake itself from D3 in S0
+
+ Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable
+
+
+ Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state
+
+ // GPE handler for HDA, this is part of _Lxx handler for bus 0 PME
+ Method(GPEH) {
+ If(LEqual(VDID, 0xFFFFFFFF)) {
+ Return()
+ }
+
+ If(LAnd(PMEE, PMES)) {
+ ADBG("HDAS GPEH")
+ Store(1, PMES) // clear PME Status
+ Notify(CAVS, 0x02)
+ }
+ }
+
+ // NHLT Table memory descriptor, returned from _DSM
+ Name(NBUF, ResourceTemplate () {
+ // NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN - 1) and length (_LEN)
+ QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheable, ReadOnly,
+ 0x1, // AddressGranularity
+ 0x0000000000000000, // AddressMinimum _MIN
+ 0x0000000000000000, // AddressMaximum _MAX
+ 0x0,
+ 0x0, // RangeLength _LEN
+ , , NHLT, AddressRangeACPI,)
+ })
+
+ Method(AUWA,0,Serialized)
+ {
+ If(LEqual(PCHS, 1)) {
+ If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-H A0 stepping (RevID = 0x0)
+ } else {
+ If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP A0 stepping (RevID = 0x0)
+ If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP A1 stepping (RevID = 0x1)
+ If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP A2 stepping (RevID = 0x9)
+ }
+ Return (0)
+ }
+
+ Method(_INI) {
+ // Update resource according to NVS
+ ADBG("HDAS _INI")
+
+ // Set NHLT base address and length
+ CreateQWordField(NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField(NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField(NBUF, ^NHLT._LEN, NLEN)
+ Store(NHLA, NBAS)
+ Add(NHLA, Subtract(NHLL, 1), NMAS)
+ Store(NHLL, NLEN)
+
+ If(LEqual(AUWA(), 1)) {
+ Store(0, \_SB.PC00.CAVS.MBCG)
+ }
+ }
+
+ Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
+ // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer)
+ // Arg1 - Revision ID: 0x01 (Integer)
+ // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details.
+ // Arg3 - Depends on Function Index - See below for details.
+ // Return - Depends on Function Index - See below for details.
+
+ ADBG("HDAS _DSM")
+
+ if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+
+ // Verify UUID
+ If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) {
+
+ Switch(ToInteger(Arg2)) {
+
+ // Function 0: Function Support Query
+ // Arg2 - Function Index: 0x00 (Integer)
+ // Arg3: Unused
+ // Return: Bitmask of functions supported. (Buffer)
+ Case(0) {
+ // Supports function 0 - 3
+ Return(Buffer(One) { 0x0F })
+ }
+
+ // Function 1: Query Non HD Audio Descriptor Table
+ // Used by the Intel Offload Engine Driver to discover the
+ // non HD Audio devices supported by the Audio DSP.
+ // Arg2 - Function Index: 0x01 (Integer)
+ // Arg3 - Unused
+ // Return - ACPI Table describing the non HD Audio links and devices supported by the ADSP (ResourceBuffer)
+ Case(1) {
+ ADBG("_DSM Fun 1 NHLT")
+ // NBUF - Memory Resource Descriptor buffer with address and length of NHLT
+ Return(NBUF)
+ }
+
+ // Function 2: Query Feature Mask
+ // Used by the Intel Offload Engine Driver to retrieve a bitmask
+ // of features allowable on this platform.
+ // Arg2 - Function Index: 0x02 (Integer)
+ // Arg3: Unused
+ // Return: Bitmask of supported features.
+ Case (2) {
+ ADBG("_DSM Fun 2 FMSK")
+ // Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported
+ // Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported
+ // Bit 2 == '1', codec based VAD support allowable
+ // Bit 3 - 4 Reserved
+ // Bit 5 == '1', BT Intel HFP SCO is supported
+ // Bit 6 == '1', BT Intel A2DP is supported
+ // Bit 7 == '1', DSP based speech pre-processing disabled
+ // Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on Voice
+ // Bit 9 - 31 Reserved, shall be set to '0'
+ // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy
+ Return(ADFM)
+ }
+
+ // Function 3: Query Pre/Post Processing Module Support
+ // Used by the Intel Offload Engine Driver to determine if a
+ // specified PP Module is allowed to be supported on this platform
+ // Arg2 - Function Index: 0x03 (Integer)
+ // Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer)
+ // Return - TRUE if PP Module supported, else FALSE.
+ Case (3) {
+ ADBG("_DSM Fun 3 PPMS")
+ // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated from PchPolicy: HdaConfig->DspPpModuleMask
+
+ //
+ // Example (to be updated with real GUIDs of supported 3rd party IP):
+ //
+ // 3rd Party DSP Processing Module 1 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT0)
+ // Check PP module with GUID AABBCCDD-EEFF-1122-3344-556677889900
+ // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-556677889900"))){
+ // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] / ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true)
+ // }
+ //
+ // 3rd Party DSP Processing Module 5 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT5)
+ // Check PP module with GUID 11111111-2222-3333-4444-AABBCCDDEEFF
+ // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-AABBCCDDEEFF"))){
+ // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] / ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true)
+ // }
+ //
+ // Implement for all supported PP modules
+ //
+ Return(Buffer() {0x00}) // Is not supported
+ }
+
+ Default {
+ // Function not supported (Arg2)
+ ADBG("_DSM Fun NOK")
+ Return(Buffer(One) { 0x00 })
+ }
+ } // Switch(Arg2) End
+ } // If(Arg0, UUID) End
+
+
+ // UUID not supported (Arg0)
+ ADBG("_DSM UUID NOK")
+ //Fix warning: not all control paths return a value
+ Return(Buffer() {0x00})
+ } // _DSM End
+
+} // end "High Definition Audio Controller"
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl
new file mode 100644
index 0000000000..bd27ca7342
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl
@@ -0,0 +1,271 @@
+/** @file
+
+ @copyright
+ Copyright 2013 - 2016 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // Define PCH NVS Area operatino region.
+ //
+
+
+
+ OperationRegion(PNVA,SystemMemory,PNVB,PNVL)
+ Field(PNVA,AnyAcc,Lock,Preserve)
+ {
+ Offset(0), RCRV, 32, // Offset(0), RC Revision
+ Offset(4), PCHS, 16, // Offset(4), PCH Series
+ Offset(6), PCHG, 16, // Offset(6), PCH Generation
+ Offset(8), RPA1, 32, // Offset(8), Root Port address 1
+ Offset(12), RPA2, 32, // Offset(12), Root Port address 2
+ Offset(16), RPA3, 32, // Offset(16), Root Port address 3
+ Offset(20), RPA4, 32, // Offset(20), Root Port address 4
+ Offset(24), RPA5, 32, // Offset(24), Root Port address 5
+ Offset(28), RPA6, 32, // Offset(28), Root Port address 6
+ Offset(32), RPA7, 32, // Offset(32), Root Port address 7
+ Offset(36), RPA8, 32, // Offset(36), Root Port address 8
+ Offset(40), RPA9, 32, // Offset(40), Root Port address 9
+ Offset(44), RPAA, 32, // Offset(44), Root Port address 10
+ Offset(48), RPAB, 32, // Offset(48), Root Port address 11
+ Offset(52), RPAC, 32, // Offset(52), Root Port address 12
+ Offset(56), RPAD, 32, // Offset(56), Root Port address 13
+ Offset(60), RPAE, 32, // Offset(60), Root Port address 14
+ Offset(64), RPAF, 32, // Offset(64), Root Port address 15
+ Offset(68), RPAG, 32, // Offset(68), Root Port address 16
+ Offset(72), RPAH, 32, // Offset(72), Root Port address 17
+ Offset(76), RPAI, 32, // Offset(76), Root Port address 18
+ Offset(80), RPAJ, 32, // Offset(80), Root Port address 19
+ Offset(84), RPAK, 32, // Offset(84), Root Port address 20
+ Offset(88), NHLA, 64, // Offset(88), HD-Audio NHLT ACPI address
+ Offset(96), NHLL, 32, // Offset(96), HD-Audio NHLT ACPI length
+ Offset(100), ADFM, 32, // Offset(100), HD-Audio DSP Feature Mask
+ Offset(104), SBRG, 32, // Offset(104), SBREG_BAR
+ Offset(108), GPEM, 32, // Offset(108), GPP_X to GPE_DWX mapping
+ Offset(112), G2L0, 32, // Offset(112), GPE 2-tier level edged enabled Gpio pads (Group Index 0)
+ Offset(116), G2L1, 32, // Offset(116), GPE 2-tier level edged enabled Gpio pads (Group Index 1)
+ Offset(120), G2L2, 32, // Offset(120), GPE 2-tier level edged enabled Gpio pads (Group Index 2)
+ Offset(124), G2L3, 32, // Offset(124), GPE 2-tier level edged enabled Gpio pads (Group Index 3)
+ Offset(128), G2L4, 32, // Offset(128), GPE 2-tier level edged enabled Gpio pads (Group Index 4)
+ Offset(132), G2L5, 32, // Offset(132), GPE 2-tier level edged enabled Gpio pads (Group Index 5)
+ Offset(136), G2L6, 32, // Offset(136), GPE 2-tier level edged enabled Gpio pads (Group Index 6)
+ Offset(140), G2L7, 32, // Offset(140), GPE 2-tier level edged enabled Gpio pads (Group Index 7)
+ Offset(144), G2L8, 32, // Offset(144), GPE 2-tier level edged enabled Gpio pads (Group Index 8)
+ Offset(148), G2L9, 32, // Offset(148), GPE 2-tier level edged enabled Gpio pads (Group Index 9)
+ Offset(152), G2LA, 32, // Offset(152), GPE 2-tier level edged enabled Gpio pads (Group Index 10)
+ Offset(156), G2LB, 32, // Offset(156), GPE 2-tier level edged enabled Gpio pads (Group Index 11)
+ Offset(160), G2LC, 32, // Offset(160), GPE 2-tier level edged enabled Gpio pads (Groip Index 12)
+
+ Offset(164), PML1, 16, // Offset(164), PCIE LTR max snoop Latency 1
+ Offset(166), PML2, 16, // Offset(166), PCIE LTR max snoop Latency 2
+ Offset(168), PML3, 16, // Offset(168), PCIE LTR max snoop Latency 3
+ Offset(170), PML4, 16, // Offset(170), PCIE LTR max snoop Latency 4
+ Offset(172), PML5, 16, // Offset(172), PCIE LTR max snoop Latency 5
+ Offset(174), PML6, 16, // Offset(174), PCIE LTR max snoop Latency 6
+ Offset(176), PML7, 16, // Offset(176), PCIE LTR max snoop Latency 7
+ Offset(178), PML8, 16, // Offset(178), PCIE LTR max snoop Latency 8
+ Offset(180), PML9, 16, // Offset(180), PCIE LTR max snoop Latency 9
+ Offset(182), PMLA, 16, // Offset(182), PCIE LTR max snoop Latency 10
+ Offset(184), PMLB, 16, // Offset(184), PCIE LTR max snoop Latency 11
+ Offset(186), PMLC, 16, // Offset(186), PCIE LTR max snoop Latency 12
+ Offset(188), PMLD, 16, // Offset(188), PCIE LTR max snoop Latency 13
+ Offset(190), PMLE, 16, // Offset(190), PCIE LTR max snoop Latency 14
+ Offset(192), PMLF, 16, // Offset(192), PCIE LTR max snoop Latency 15
+ Offset(194), PMLG, 16, // Offset(194), PCIE LTR max snoop Latency 16
+ Offset(196), PMLH, 16, // Offset(196), PCIE LTR max snoop Latency 17
+ Offset(198), PMLI, 16, // Offset(198), PCIE LTR max snoop Latency 18
+ Offset(200), PMLJ, 16, // Offset(200), PCIE LTR max snoop Latency 19
+ Offset(202), PMLK, 16, // Offset(202), PCIE LTR max snoop Latency 20
+ Offset(204), PNL1, 16, // Offset(204), PCIE LTR max no snoop Latency 1
+ Offset(206), PNL2, 16, // Offset(206), PCIE LTR max no snoop Latency 2
+ Offset(208), PNL3, 16, // Offset(208), PCIE LTR max no snoop Latency 3
+ Offset(210), PNL4, 16, // Offset(210), PCIE LTR max no snoop Latency 4
+ Offset(212), PNL5, 16, // Offset(212), PCIE LTR max no snoop Latency 5
+ Offset(214), PNL6, 16, // Offset(214), PCIE LTR max no snoop Latency 6
+ Offset(216), PNL7, 16, // Offset(216), PCIE LTR max no snoop Latency 7
+ Offset(218), PNL8, 16, // Offset(218), PCIE LTR max no snoop Latency 8
+ Offset(220), PNL9, 16, // Offset(220), PCIE LTR max no snoop Latency 9
+ Offset(222), PNLA, 16, // Offset(222), PCIE LTR max no snoop Latency 10
+ Offset(224), PNLB, 16, // Offset(224), PCIE LTR max no snoop Latency 11
+ Offset(226), PNLC, 16, // Offset(226), PCIE LTR max no snoop Latency 12
+ Offset(228), PNLD, 16, // Offset(228), PCIE LTR max no snoop Latency 13
+ Offset(230), PNLE, 16, // Offset(230), PCIE LTR max no snoop Latency 14
+ Offset(232), PNLF, 16, // Offset(232), PCIE LTR max no snoop Latency 15
+ Offset(234), PNLG, 16, // Offset(234), PCIE LTR max no snoop Latency 16
+ Offset(236), PNLH, 16, // Offset(236), PCIE LTR max no snoop Latency 17
+ Offset(238), PNLI, 16, // Offset(238), PCIE LTR max no snoop Latency 18
+ Offset(240), PNLJ, 16, // Offset(240), PCIE LTR max no snoop Latency 19
+ Offset(242), PNLK, 16, // Offset(242), PCIE LTR max no snoop Latency 20
+ Offset(244), U0C0, 32, // Offset(244), SerialIo Hidden UART0 BAR 0
+ Offset(248), U1C0, 32, // Offset(248), SerialIo Hidden UART1 BAR 0
+ Offset(252), ADPM, 32, // Offset(252), HD-Audio DSP Post-Processing Module Mask
+ Offset(256), XHPC, 8, // Offset(256), Number of HighSpeed ports implemented in XHCI controller
+ Offset(257), XRPC, 8, // Offset(257), Number of USBR ports implemented in XHCI controller
+ Offset(258), XSPC, 8, // Offset(258), Number of SuperSpeed ports implemented in XHCI controller
+ Offset(259), XSPA, 8, // Offset(259), Address of 1st SuperSpeed port
+ Offset(260), HPTB, 32, // Offset(260), HPET base address
+ Offset(264), HPTE, 8, // Offset(264), HPET enable
+ //110-bytes large SerialIo block
+ Offset(265), SMD0, 8, // Offset(265), SerialIo controller 0 (sdma) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(266), SMD1, 8, // Offset(266), SerialIo controller 1 (i2c0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(267), SMD2, 8, // Offset(267), SerialIo controller 2 (i2c1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(268), SMD3, 8, // Offset(268), SerialIo controller 3 (spi0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(269), SMD4, 8, // Offset(269), SerialIo controller 4 (spi1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(270), SMD5, 8, // Offset(270), SerialIo controller 5 (ua00) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(271), SMD6, 8, // Offset(271), SerialIo controller 6 (ua01) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(272), SMD7, 8, // Offset(272), SerialIo controller 7 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(273), SMD8, 8, // Offset(273), SerialIo controller 8 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(274), SMD9, 8, // Offset(274), SerialIo controller 9 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(275), SMDA, 8, // Offset(275), SerialIo controller A (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
+ Offset(276), SIR0, 8, // Offset(276), SerialIo controller 0 (sdma) irq number
+ Offset(277), SIR1, 8, // Offset(277), SerialIo controller 1 (i2c0) irq number
+ Offset(278), SIR2, 8, // Offset(278), SerialIo controller 2 (i2c1) irq number
+ Offset(279), SIR3, 8, // Offset(279), SerialIo controller 3 (spi0) irq number
+ Offset(280), SIR4, 8, // Offset(280), SerialIo controller 4 (spi1) irq number
+ Offset(281), SIR5, 8, // Offset(281), SerialIo controller 5 (ua00) irq number
+ Offset(282), SIR6, 8, // Offset(282), SerialIo controller 6 (ua01) irq number
+ Offset(283), SIR7, 8, // Offset(283), SerialIo controller 7 (shdc) irq number
+ Offset(284), SIR8, 8, // Offset(284), SerialIo controller 8 (shdc) irq number
+ Offset(285), SIR9, 8, // Offset(285), SerialIo controller 9 (shdc) irq number
+ Offset(286), SIRA, 8, // Offset(286), SerialIo controller A (shdc) irq number
+ Offset(287), SB00, 32, // Offset(287), SerialIo controller 0 (sdma) BAR0
+ Offset(291), SB01, 32, // Offset(291), SerialIo controller 1 (i2c0) BAR0
+ Offset(295), SB02, 32, // Offset(295), SerialIo controller 2 (i2c1) BAR0
+ Offset(299), SB03, 32, // Offset(299), SerialIo controller 3 (spi0) BAR0
+ Offset(303), SB04, 32, // Offset(303), SerialIo controller 4 (spi1) BAR0
+ Offset(307), SB05, 32, // Offset(307), SerialIo controller 5 (ua00) BAR0
+ Offset(311), SB06, 32, // Offset(311), SerialIo controller 6 (ua01) BAR0
+ Offset(315), SB07, 32, // Offset(315), SerialIo controller 7 (shdc) BAR0
+ Offset(319), SB08, 32, // Offset(319), SerialIo controller 8 (shdc) BAR0
+ Offset(323), SB09, 32, // Offset(323), SerialIo controller 9 (shdc) BAR0
+ Offset(327), SB0A, 32, // Offset(327), SerialIo controller A (shdc) BAR0
+ Offset(331), SB10, 32, // Offset(331), SerialIo controller 0 (sdma) BAR1
+ Offset(335), SB11, 32, // Offset(335), SerialIo controller 1 (i2c0) BAR1
+ Offset(339), SB12, 32, // Offset(339), SerialIo controller 2 (i2c1) BAR1
+ Offset(343), SB13, 32, // Offset(343), SerialIo controller 3 (spi0) BAR1
+ Offset(347), SB14, 32, // Offset(347), SerialIo controller 4 (spi1) BAR1
+ Offset(351), SB15, 32, // Offset(351), SerialIo controller 5 (ua00) BAR1
+ Offset(355), SB16, 32, // Offset(355), SerialIo controller 6 (ua01) BAR1
+ Offset(359), SB17, 32, // Offset(359), SerialIo controller 7 (shdc) BAR1
+ Offset(363), SB18, 32, // Offset(363), SerialIo controller 8 (shdc) BAR1
+ Offset(367), SB19, 32, // Offset(367), SerialIo controller 9 (shdc) BAR1
+ Offset(371), SB1A, 32, // Offset(371), SerialIo controller A (shdc) BAR1
+ //end of SerialIo block
+ Offset(375), GPEN, 8, // Offset(375), GPIO enabled
+ Offset(376), SGIR, 8, // Offset(376), GPIO IRQ
+ Offset(377), NIT1, 8, // Offset(377), RST PCIe Storage Cycle Router#1 Interface Type
+ Offset(378), NIT2, 8, // Offset(378), RST PCIe Storage Cycle Router#2 Interface Type
+ Offset(379), NIT3, 8, // Offset(379), RST PCIe Storage Cycle Router#3 Interface Type
+ Offset(380), NPM1, 8, // Offset(380), RST PCIe Storage Cycle Router#1 Power Management Capability Pointer
+ Offset(381), NPM2, 8, // Offset(381), RST PCIe Storage Cycle Router#2 Power Management Capability Pointer
+ Offset(382), NPM3, 8, // Offset(382), RST PCIe Storage Cycle Router#3 Power Management Capability Pointer
+ Offset(383), NPC1, 8, // Offset(383), RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer
+ Offset(384), NPC2, 8, // Offset(384), RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer
+ Offset(385), NPC3, 8, // Offset(385), RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer
+ Offset(386), NL11, 16, // Offset(386), RST PCIe Storage Cycle Router#1 L1SS Capability Pointer
+ Offset(388), NL12, 16, // Offset(388), RST PCIe Storage Cycle Router#2 L1SS Capability Pointer
+ Offset(390), NL13, 16, // Offset(390), RST PCIe Storage Cycle Router#3 L1SS Capability Pointer
+ Offset(392), ND21, 8, // Offset(392), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2
+ Offset(393), ND22, 8, // Offset(393), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2
+ Offset(394), ND23, 8, // Offset(394), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2
+ Offset(395), ND11, 32, // Offset(395), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1
+ Offset(399), ND12, 32, // Offset(399), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1
+ Offset(403), ND13, 32, // Offset(403), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1
+ Offset(407), NLR1, 16, // Offset(407), RST PCIe Storage Cycle Router#1 LTR Capability Pointer
+ Offset(409), NLR2, 16, // Offset(409), RST PCIe Storage Cycle Router#2 LTR Capability Pointer
+ Offset(411), NLR3, 16, // Offset(411), RST PCIe Storage Cycle Router#3 LTR Capability Pointer
+ Offset(413), NLD1, 32, // Offset(413), RST PCIe Storage Cycle Router#1 Endpoint LTR Data
+ Offset(417), NLD2, 32, // Offset(417), RST PCIe Storage Cycle Router#2 Endpoint LTR Data
+ Offset(421), NLD3, 32, // Offset(421), RST PCIe Storage Cycle Router#3 Endpoint LTR Data
+ Offset(425), NEA1, 16, // Offset(425), RST PCIe Storage Cycle Router#1 Endpoint LCTL Data
+ Offset(427), NEA2, 16, // Offset(427), RST PCIe Storage Cycle Router#2 Endpoint LCTL Data
+ Offset(429), NEA3, 16, // Offset(429), RST PCIe Storage Cycle Router#3 Endpoint LCTL Data
+ Offset(431), NEB1, 16, // Offset(431), RST PCIe Storage Cycle Router#1 Endpoint DCTL Data
+ Offset(433), NEB2, 16, // Offset(433), RST PCIe Storage Cycle Router#2 Endpoint DCTL Data
+ Offset(435), NEB3, 16, // Offset(435), RST PCIe Storage Cycle Router#3 Endpoint DCTL Data
+ Offset(437), NEC1, 16, // Offset(437), RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data
+ Offset(439), NEC2, 16, // Offset(439), RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data
+ Offset(441), NEC3, 16, // Offset(441), RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data
+ Offset(443), NRA1, 16, // Offset(443), RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data
+ Offset(445), NRA2, 16, // Offset(445), RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data
+ Offset(447), NRA3, 16, // Offset(447), RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data
+ Offset(449), NMB1, 32, // Offset(449), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR
+ Offset(453), NMB2, 32, // Offset(453), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR
+ Offset(457), NMB3, 32, // Offset(457), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR
+ Offset(461), NMV1, 32, // Offset(461), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value
+ Offset(465), NMV2, 32, // Offset(465), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value
+ Offset(469), NMV3, 32, // Offset(469), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value
+ Offset(473), NPB1, 32, // Offset(473), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR
+ Offset(477), NPB2, 32, // Offset(477), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR
+ Offset(481), NPB3, 32, // Offset(481), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR
+ Offset(485), NPV1, 32, // Offset(485), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value
+ Offset(489), NPV2, 32, // Offset(489), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value
+ Offset(493), NPV3, 32, // Offset(493), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value
+ Offset(497), , 8, // Offset(497), Flag indicating Exit Boot Service, to inform SMM
+ Offset(498), SXRB, 32, // Offset(498), Sx handler reserved MMIO base
+ Offset(502), SXRS, 32, // Offset(502), Sx handler reserved MMIO size
+ Offset(506), CIOE, 8, // Offset(506), Cio2 Device Enabled as ACPI device
+ Offset(507), CIOI, 8, // Offset(507), Cio2 Interrupt Number
+ Offset(508), TAEN, 8, // Offset(508), Thermal Device Acpi mode enabled
+ Offset(509), TIRQ, 8, // Offset(509), Thermal Device IRQ number
+ Offset(510), XWMB, 32, // Offset(510), XHCI memory base address
+ Offset(514), EMH4, 8, // Offset(514), eMMC HS400 mode enabled
+ Offset(515), CSKU, 8, // Offset(515), CPU SKU
+ Offset(516), ITA0, 16, // Offset(516),
+ Offset(518), ITA1, 16, // Offset(518),
+ Offset(520), ITA2, 16, // Offset(520),
+ Offset(522), ITA3, 16, // Offset(522),
+ Offset(524), ITS0, 8, // Offset(524),
+ Offset(525), ITS1, 8, // Offset(525),
+ Offset(526), ITS2, 8, // Offset(526),
+ Offset(527), ITS3, 8, // Offset(527),
+ Offset(528), LTR1, 8, // Offset(528), Latency Tolerance Reporting Enable
+ Offset(529), LTR2, 8, // Offset(529), Latency Tolerance Reporting Enable
+ Offset(530), LTR3, 8, // Offset(530), Latency Tolerance Reporting Enable
+ Offset(531), LTR4, 8, // Offset(531), Latency Tolerance Reporting Enable
+ Offset(532), LTR5, 8, // Offset(532), Latency Tolerance Reporting Enable
+ Offset(533), LTR6, 8, // Offset(533), Latency Tolerance Reporting Enable
+ Offset(534), LTR7, 8, // Offset(534), Latency Tolerance Reporting Enable
+ Offset(535), LTR8, 8, // Offset(535), Latency Tolerance Reporting Enable
+ Offset(536), LTR9, 8, // Offset(536), Latency Tolerance Reporting Enable
+ Offset(537), LTRA, 8, // Offset(537), Latency Tolerance Reporting Enable
+ Offset(538), LTRB, 8, // Offset(538), Latency Tolerance Reporting Enable
+ Offset(539), LTRC, 8, // Offset(539), Latency Tolerance Reporting Enable
+ Offset(540), LTRD, 8, // Offset(540), Latency Tolerance Reporting Enable
+ Offset(541), LTRE, 8, // Offset(541), Latency Tolerance Reporting Enable
+ Offset(542), LTRF, 8, // Offset(542), Latency Tolerance Reporting Enable
+ Offset(543), LTRG, 8, // Offset(543), Latency Tolerance Reporting Enable
+ Offset(544), LTRH, 8, // Offset(544), Latency Tolerance Reporting Enable
+ Offset(545), LTRI, 8, // Offset(545), Latency Tolerance Reporting Enable
+ Offset(546), LTRJ, 8, // Offset(546), Latency Tolerance Reporting Enable
+ Offset(547), LTRK, 8, // Offset(547), Latency Tolerance Reporting Enable
+ Offset(548), OBF1, 8, // Offset(548), Optimized Buffer Flush and Fill
+ Offset(549), OBF2, 8, // Offset(549), Optimized Buffer Flush and Fill
+ Offset(550), OBF3, 8, // Offset(550), Optimized Buffer Flush and Fill
+ Offset(551), OBF4, 8, // Offset(551), Optimized Buffer Flush and Fill
+ Offset(552), OBF5, 8, // Offset(552), Optimized Buffer Flush and Fill
+ Offset(553), OBF6, 8, // Offset(553), Optimized Buffer Flush and Fill
+ Offset(554), OBF7, 8, // Offset(554), Optimized Buffer Flush and Fill
+ Offset(555), OBF8, 8, // Offset(555), Optimized Buffer Flush and Fill
+ Offset(556), OBF9, 8, // Offset(556), Optimized Buffer Flush and Fill
+ Offset(557), OBFA, 8, // Offset(557), Optimized Buffer Flush and Fill
+ Offset(558), OBFB, 8, // Offset(558), Optimized Buffer Flush and Fill
+ Offset(559), OBFC, 8, // Offset(559), Optimized Buffer Flush and Fill
+ Offset(560), OBFD, 8, // Offset(560), Optimized Buffer Flush and Fill
+ Offset(561), OBFE, 8, // Offset(561), Optimized Buffer Flush and Fill
+ Offset(562), OBFF, 8, // Offset(562), Optimized Buffer Flush and Fill
+ Offset(563), OBFG, 8, // Offset(563), Optimized Buffer Flush and Fill
+ Offset(564), OBFH, 8, // Offset(564), Optimized Buffer Flush and Fill
+ Offset(565), OBFI, 8, // Offset(565), Optimized Buffer Flush and Fill
+ Offset(566), OBFJ, 8, // Offset(566), Optimized Buffer Flush and Fill
+ Offset(567), OBFK, 8, // Offset(567), Optimized Buffer Flush and Fill
+ Offset(568), ECR1, 8, // Offset(568), External Change Request
+ Offset(569), AG1L, 64, // Offset(569), HDA PP module custom GUID 1 - first 64bit [0-63]
+ Offset(577), AG1H, 64, // Offset(577), HDA PP module custom GUID 1 - second 64bit [64-127]
+ Offset(585), AG2L, 64, // Offset(585), HDA PP module custom GUID 2 - first 64bit [0-63]
+ Offset(593), AG2H, 64, // Offset(593), HDA PP module custom GUID 2 - second 64bit [64-127]
+ Offset(601), AG3L, 64, // Offset(601), HDA PP module custom GUID 3 - first 64bit [0-63]
+ Offset(609), AG3H, 64, // Offset(609), HDA PP module custom GUID 3 - second 64bit [64-127]
+ Offset(617), MCFG, 32 // Offset(617), PcieMmCfgBaseAddress
+ }
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl
new file mode 100644
index 0000000000..21d68c55bc
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl
@@ -0,0 +1,203 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ OperationRegion(PXCS,PCI_Config,0x00,0x480)
+ Field(PXCS,AnyAcc, NoLock, Preserve)
+ {
+ Offset(0),
+ VDID, 32,
+ Offset(0x50), // LCTL - Link Control Register
+ L0SE, 1, // 0, L0s Entry Enabled
+ , 3,
+ LDIS, 1,
+ , 3,
+ Offset(0x52), // LSTS - Link Status Register
+ , 13,
+ LASX, 1, // 0, Link Active Status
+ Offset(0x5A), // SLSTS[7:0] - Slot Status Register
+ ABPX, 1, // 0, Attention Button Pressed
+ , 2,
+ PDCX, 1, // 3, Presence Detect Changed
+ , 2,
+ PDSX, 1, // 6, Presence Detect State
+ , 1,
+ Offset(0x60), // RSTS - Root Status Register
+ , 16,
+ PSPX, 1, // 16, PME Status
+ Offset(0xA4),
+ D3HT, 2, // Power State
+ Offset(0xD8), // MPC - Miscellaneous Port Configuration Register
+ , 30,
+ HPEX, 1, // 30, Hot Plug SCI Enable
+ PMEX, 1, // 31, Power Management SCI Enable
+ Offset(0xE2), // RPPGEN - Root Port Power Gating Enable
+ , 2,
+ L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
+ L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
+ Offset(0x324),
+ , 3,
+ LEDM, 1, // PCIEDBG.DMIL1EDM
+ Offset(0x420), // Offset 420h: PCIEPMECTL - PCIe PM Extension Control
+ , 30,
+ DPGE, 1, // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane Power Gating Enable (DLSULPPGE):
+ }
+ Field(PXCS,AnyAcc, NoLock, WriteAsZeros)
+ {
+ Offset(0xDC), // SMSCS - SMI/SCI Status Register
+ , 30,
+ HPSX, 1, // 30, Hot Plug SCI Status
+ PMSX, 1 // 31, Power Management SCI Status
+ }
+
+
+ Name(LTRV, Package(){0,0,0,0})
+
+ //
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index (0 = Return Supported Functions)
+ // Arg3: Package Parameters
+ Method(_DSM, 4, Serialized) {
+ //
+ // Switch based on which unique function identifier was passed in
+ //
+ If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+ //
+ // _DSM Definitions for Latency Tolerance Reporting
+ //
+ // Arguments:
+ // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+ // Arg1: Revision ID: 2
+ // Arg2: Function Index: 1, 4 or 6
+ // Arg3: Empty Package
+ //
+ // Return:
+ // A Package of four integers corresponding with the LTR encoding defined
+ // in the PCI Express Base Specification, as follows:
+ // Integer 0: Maximum Snoop Latency Scale
+ // Integer 1: Maximum Snoop Latency Value
+ // Integer 2: Maximum No-Snoop Latency Scale
+ // Integer 3: Maximum No-Snoop Latency Value
+ // These values correspond directly to the LTR Extended Capability Structure
+ // fields described in the PCI Express Base Specification.
+ //
+ //
+ // Switch by function index
+ //
+ Switch(ToInteger(Arg2)) {
+ //
+ // Function Index:0
+ // Standard query - A bitmask of functions supported
+ //
+ Case (0) {
+ Name(OPTS,Buffer(2){0,0})
+ CreateBitField(OPTS,0,FUN0)
+ CreateBitField(OPTS,4,FUN4)
+ CreateBitField(OPTS,6,FUN6)
+ CreateBitField(OPTS,8,FUN8)
+ CreateBitField(OPTS,9,FUN9)
+
+ if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+ Store(1,FUN0)
+ if (LTRE){
+ Store(1,Fun6)
+ }
+ if (OBFF){
+ Store(1,Fun4)
+ }
+ if(LEqual(ECR1,1)){
+ if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3
+ Store(1,Fun8)
+ Store(1,Fun9)
+ }
+ }
+ }
+ Return (OPTS)
+ }
+ //
+ // Function Index: 4
+ //
+ Case(4) {
+ if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+ if (OBFN){
+ Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h]
+ } else {
+ Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0})
+ }
+ }
+ }
+ //
+ // Function Index: 6
+ // LTR Extended Capability Structure
+ //
+ Case(6) {
+ if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
+ if (LTRN){
+ if (LOr(LEqual(LMSL, 0),LEqual(LNSL, 0)))
+ {
+ if (LEqual (PCHS, SPTH)) {
+ Store (0x0846, LMSL)
+ Store (0x0846, LNSL)
+ } elseif (LEqual (PCHS, SPTL)) {
+ Store (0x1003, LMSL)
+ Store (0x1003, LNSL)
+ }
+ }
+ Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))
+ Store(And(LMSL,0x3FF), Index(LTRV, 1))
+ Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))
+ Store(And(LNSL,0x3FF), Index(LTRV, 3))
+
+ Return (LTRV)
+ } else {
+ Return (0)
+ }
+ }
+ }
+ Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume
+ if(LEqual(ECR1,1)){
+ if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
+ return (1)
+ }
+ }
+ }
+ Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for Specifying Device Readiness Durations
+ if(LEqual(ECR1,1)){
+ if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
+ return(Package(5){50000,Ones,Ones,50000,Ones})
+ }
+ }
+ }
+ } // End of switch(Arg2)
+ } // End of if
+ return (Buffer() {0x00})
+ } // End of _DSM
+
+ Device(PXSX)
+ {
+ Name(_ADR, 0x00000000)
+
+ // NOTE: Any PCIE Hot-Plug dependency for this port is
+ // specific to the CRB. Please modify the code based on
+ // your platform requirements.
+ Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state
+ }
+
+ //
+ // PCI_EXP_STS Handler for PCIE Root Port
+ //
+ Method(HPME,0,Serialized) {
+ If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists and has PME SCI Status set...
+ Notify (PXSX, 0x2) //notify child device; this will cause its driver to clear PME_Status from device
+ Store(1,PMSX) // clear rootport's PME SCI status
+ Store(1,PSPX) // consume one pending PME notification to prevent it from blocking the queue
+ }
+ }
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl
new file mode 100644
index 0000000000..4150833906
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl
@@ -0,0 +1,50 @@
+/** @file
+
+ @copyright
+ Copyright 2013 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#define ROOTPORT_READ 0
+#define ROOTPORT_WRITE 1
+#define ENDPOINT_READ 2
+#define ENDPOINT_WRITE 3
+
+//
+// SDSM is Device Specific Method supporting AHCI DEVSLP
+// It is not guaranteed to be available on every boot
+//
+// move one level up to Pch.asl
+
+ Method(_DSM,4,serialized){
+ if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) };
+ if(CondRefOf(\_SB.PC00.SAT0.SDSM)) { return (\_SB.PC00.SAT0.SDSM(Arg0,Arg1,Arg2,Arg3)) };
+ Return(Buffer() {0})
+ }
+
+ Device(PRT0)
+ {
+ Name(_ADR,0x0000FFFF) // Port 0
+ }
+ Device(PRT1)
+ {
+ Name(_ADR,0x0001FFFF) // Port 1
+ }
+ Device(PRT2)
+ {
+ Name(_ADR,0x0002FFFF) // Port 2
+ }
+ Device(PRT3)
+ {
+ Name(_ADR,0x0003FFFF) // Port 3
+ }
+ Device(PRT4)
+ {
+ Name(_ADR,0x0004FFFF) // Port 4
+ }
+ Device(PRT5)
+ {
+ Name(_ADR,0x0005FFFF) // Port 5
+ }
+
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl
new file mode 100644
index 0000000000..5b9d7ed57e
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl
@@ -0,0 +1,558 @@
+/** @file
+
+ @copyright
+ Copyright 2010 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+External(\_SB.PC00.XHCI.PS0X, MethodObj)
+External(\_SB.PC00.XHCI.PS3X, MethodObj)
+External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj)
+External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj)
+External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj)
+External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj)
+
+
+Scope(\_SB_.PC00.XHCI) {
+
+ OperationRegion(XPRT,PCI_Config,0x00,0x100)
+ Field(XPRT,AnyAcc,NoLock,Preserve)
+ {
+ DVID, 16,
+ Offset(0x74),
+ D0D3, 2, // 0x74 BIT[1:0]
+ , 6,
+ PMEE, 1, // PME Enable
+ , 6,
+ PMES, 1, // PME Status
+ Offset(0xA8), // SSCFG Reg for WPTLP
+ , 13,
+ MW13, 1, // 0xA8 BIT[13]
+ MW14, 1, // 0xA8 BIT[14]
+ , 17,
+ Offset(0xB0), // SSCFG Reg for LPTLP
+ , 13,
+ MB13, 1, // 0xB0 BIT[13]
+ MB14, 1, // 0xB0 BIT[14]
+ , 17,
+ Offset(0xD0),
+ PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
+ PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
+ PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
+ PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
+ }
+
+ //
+ // Variable to store the maximum D state supported in S0.
+ //
+ Name (XFLT, 0)
+ //
+ // XHCI controller won't go into D3Hot during S0 until _DSM method is evaluated by filter driver.
+ //
+ Method(_DSM,4,serialized){
+ If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+ //
+ // Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23
+ //
+ If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 }))
+ {
+ //
+ // Only Supported value is "0x3"
+ //
+ If(LEqual(Arg1, 0x3))
+ {
+ Store(Arg1,XFLT)
+ }
+ }
+ Return(Buffer() {0})
+ }
+
+ Method(_S3D, 0, NotSerialized)
+ {
+ Return(3)
+ }
+ Method(_S4D, 0, NotSerialized)
+ {
+ Return(3)
+ }
+ Method(_S3W, 0, NotSerialized)
+ {
+ Return(3)
+ }
+ Method(_S4W, 0, NotSerialized)
+ {
+ Return(3)
+ }
+
+ //
+ // Once the filter driver is installed, D3 is allowed.
+ //
+ Method(_S0W, 0x0, NotSerialized)
+ {
+ If(LEqual(XFLT, Zero))
+ {
+ Return(0x0)
+ }
+ Else
+ {
+ Return(0x3)
+ }
+ }
+
+ Method(_PRW, 0)
+ {
+ Return(GPRW(0x6D, 4)) // can wakeup from S4 state
+ }
+
+ Method(_DSW, 3)
+ {
+ Store(Arg0, PMEE)
+ }
+
+ Method(_INI) {
+ // _INI for RTD3 run conditionally if implemented in platform specific code
+ If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3
+ \_SB.PC00.XHCI.RHUB.INIR()
+ }
+ }
+
+ //
+ // GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME
+ //
+ Method(GPEH)
+ {
+ If(LEqual(DVID, 0xFFFF)) {
+ Return()
+ }
+ Store(PMES, Local0)
+ Store(1, PMES) // clear PME Status
+ If(LAnd(PMEE, Local0)) {
+ Notify(XHCI, 0x02)
+ }
+ }
+
+ OperationRegion(XHCP, SystemMemory, Add(MCFG, 0xA0000), 0x100)
+ Field(XHCP,AnyAcc,Lock,Preserve)
+ {
+ Offset(0x4),
+ PDBM, 16,
+ Offset(0x10),
+ MEMB, 64
+ }
+
+ //
+ // USRA (USbR port Address), method for calculating address of first USBR port in XHCI controller
+ //
+ Method(USRA,0,Serialized) {
+ If(LEqual(PCHV, SPTH)) { // SPT-H
+ Return (15)
+ } Else { // SPT-LP
+ Return (11)
+ }
+ }
+
+ //
+ // SSPA (SuperSpeed Port Address), method for calculating address of first SS port in XHCI controller
+ //
+ Method(SSPA,0,Serialized) {
+ If(LEqual(PCHV, SPTH)) { // SPT-H
+ Return (17)
+ } Else { // SPT-LP
+ Return (13)
+ }
+ }
+
+ Name(XRST, Zero)
+
+ Method(_PS0,0,Serialized)
+ {
+
+ If(LEqual(^DVID,0xFFFF))
+ {
+ Return()
+ }
+
+ Store(^MEMB,Local2) // Save MBAR
+ Store(^PDBM,Local1) // Save CMD
+
+ And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
+
+ //
+ // Switch to D0
+ //
+ Store(0,^D0D3)
+
+ Store(\XWMB,^MEMB) // Set MBAR
+ Or(Local1,0x0002,^PDBM) // Set MSE
+
+ //
+ //
+ //
+
+ And(^PDBM,Not(0x02),^PDBM) // Clear MSE
+
+ Store(Local2,^MEMB) // Restore MBAR
+ Store(Local1,^PDBM) // Restore CMD
+
+ //
+ // Call platform XHC PS0 method if present
+ //
+ If(CondRefOf(\_SB.PC00.XHCI.PS0X))
+ {
+ \_SB.PC00.XHCI.PS0X()
+ }
+ //
+ //
+ If(LAnd(UWAB,LEqual(D0D3,0))) {
+
+ //
+ // If the USB WA Bit is set and any XHCI or XDCI controller is in D0
+ //
+ //
+ // USB2 PHPY Power Gating - SW WA
+ //
+ // 1. BIOS writes a new command to the MTPMC register to cause the PMC to disable power gating
+ Store(1,MPMC)
+
+ // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
+ // In parallel and in response to the previous command from BIOS, PMC FW will:
+ // * Make the USB2 force common lane PG match the BIOS policy (common lane PG disallowed)
+ // * Disable SUS power gating in XHCI
+ // * Wait for USB2 PHY side_pok to be 1
+ // * Disable core power gating in USB2 PHY
+ // * Disable common lane power gating in USB2 PHY (probably not necessary, consider removal)
+ // * Wait for USB2 SUS restoration status to be set, and do USB2 SUS power gating restoration
+ // * Get the PHY in the correct state before allowing transition to D0.
+ // * Clear MSG_FULL_STS
+ // BIOS sees MSG_FULL_STS clear and exits the method
+ //
+ While(PMFS) {
+ Sleep(10)
+ }
+ } // End If(UWAB)
+
+ }
+
+ Method(_PS3,0,Serialized)
+ {
+
+ If(LEqual(^DVID,0xFFFF))
+ {
+ Return()
+ }
+
+ Store(^MEMB,Local2) // Save MBAR
+ Store(^PDBM,Local1) // Save CMD
+
+ And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
+
+ //
+ // Switch back to D0
+ //
+ Store(0,^D0D3)
+
+ Store(\XWMB,^MEMB) // Set MBAR
+ Or(Local1,0x0002,^PDBM) // Set MSE
+
+ //
+ //
+ //
+
+ And(^PDBM,Not(0x02),^PDBM) // Clear MSE
+
+ //
+ // Switch back to D3
+ //
+ Store(3,^D0D3)
+
+ Store(Local2,^MEMB) // Restore MBAR
+ Store(Local1,^PDBM) // Restore CMD
+
+ //
+ // Call platform XHC PS3 method if present
+ //
+ If(CondRefOf(\_SB.PC00.XHCI.PS3X))
+ {
+ \_SB.PC00.XHCI.PS3X()
+ }
+ If(LAnd(UWAB,LEqual(D0D3,3))) {
+ //
+ // If the USB WA Bit is set and XHCI is in D3
+ //
+
+ // 1. BIOS writes a new command to the MTPMC register to enable power gating
+ Store(3,MPMC)
+
+ // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
+ // In parallel and in response to the previous command from BIOS, PMC FW will:
+ // * Make the USB2 force common lane PG match the BIOS policy (common lane PG allowed)
+ // * Enable SUS power gating in XHCI
+ // * Enable core power gating in USB2 PHY
+ // * Enable common lane power gating in the USB2 PHY
+ // * Clear MSG_FULL_STS
+ // BIOS sees MSG_FULL_STS clear and exits the method
+ //
+ While(PMFS) {
+ Sleep(10)
+ }
+ } // End If(UWAB)
+ }
+
+
+ // Apply S3 workaround.
+ // Arguments :
+ // None
+ // Changes 8090 Bit 10 before S3.
+ //
+ Method(XHCS,0, Serialized) {
+ Store(^MEMB,Local2) // Save MBAR
+ Store(^PDBM,Local1) // Save CMD
+
+ And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
+
+ Store(\XWMB,^MEMB) // Set MBAR
+ Or(Local1,0x0002,^PDBM) // Set MSE
+
+ OperationRegion(MC11,SystemMemory,\XWMB,0x9000)
+ Field(MC11,DWordAcc,Lock,Preserve)
+ {
+ Offset(0x8090), // HC Transfer Manager - TRM
+ , 10,
+ UCLI, 1, // CLEAR IN EP
+ }
+
+ Store(0x1,UCLI)
+
+ And(^PDBM,Not(0x02),^PDBM) // Clear MSE
+
+ Store(Local2,^MEMB) // Restore MBAR
+ Store(Local1,^PDBM) // Restore CMD
+
+ }
+
+ //
+ //
+ // Check for XHCI switch UUID
+ //
+ // Arguments:
+ // Arg0 (Buffer) : UUID
+ //
+ // Returns:
+ // 1: It's valid UUID
+ // 0: Invalid UUID
+ //
+ Method(CUID,1,Serialized) {
+ If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ Device(RHUB)
+ {
+ Name(_ADR, Zero)
+
+ // PS0 Method for xHCI Root Hub
+ Method(_PS0,0,Serialized)
+ {
+ If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
+ {
+ Return()
+ }
+ //
+ // Call platform XHC.RHUB PS0 method if present.
+ //
+ If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X))
+ {
+ \_SB.PC00.XHCI.RHUB.PS0X()
+ }
+ }
+
+ // PS2 Method for xHCI Root Hub
+ Method(_PS2,0,Serialized)
+ {
+ If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
+ {
+ Return()
+ }
+ //
+ // Call platform XHC.RHUB PS2 method if present.
+ //
+ If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X))
+ {
+ \_SB.PC00.XHCI.RHUB.PS2X()
+ }
+ }
+
+ // PS3 Method for xHCI Root Hub
+ Method(_PS3,0,Serialized)
+ {
+ If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
+ {
+ Return()
+ }
+ //
+ // Call platform XHC.RHUB PS3 method if present.
+ //
+ If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X))
+ {
+ \_SB.PC00.XHCI.RHUB.PS3X()
+ }
+ }
+
+ //
+ // High Speed Ports (without USBR)
+ //
+ Device(HS01)
+ {
+ Name(_ADR, 0x01)
+ }
+
+ Device(HS02)
+ {
+ Name(_ADR, 0x02)
+ }
+
+ Device(HS03)
+ {
+ Name(_ADR, 0x03)
+ }
+
+ Device(HS04)
+ {
+ Name(_ADR, 0x04)
+ }
+
+ Device(HS05)
+ {
+ Name(_ADR, 0x05)
+ }
+
+ Device(HS06)
+ {
+ Name(_ADR, 0x06)
+ }
+
+ Device(HS07)
+ {
+ Name(_ADR, 0x07)
+ }
+
+ Device(HS08)
+ {
+ Name(_ADR, 0x08)
+ }
+
+ Device(HS09)
+ {
+ Name(_ADR, 0x09)
+ }
+
+ Device(HS10)
+ {
+ Name(_ADR, 0x0A)
+ }
+
+ //
+ // USBR port will be known as USBR instead of HS09 / HS15
+ //
+ Device(USR1)
+ {
+ Method(_ADR) { Return (Add(USRA(),0)) }
+ }
+
+ //
+ // USBR port 2 will be known as USBR instead of xxxx
+ //
+ Device(USR2)
+ {
+ Method(_ADR) { Return (Add(USRA(),1)) }
+ }
+
+ //
+ // Super Speed Ports
+ //
+ Device(SS01)
+ {
+ Method(_ADR) { Return (Add(SSPA(),0)) }
+ }
+
+ Device(SS02)
+ {
+ Method(_ADR) { Return (Add(SSPA(),1)) }
+ }
+
+ Device(SS03)
+ {
+ Method(_ADR) { Return (Add(SSPA(),2)) }
+ }
+
+ Device(SS04)
+ {
+ Method(_ADR) { Return (Add(SSPA(),3)) }
+ }
+
+ Device(SS05)
+ {
+ Method(_ADR) { Return (Add(SSPA(),4)) }
+ }
+
+ Device(SS06)
+ {
+ Method(_ADR) { Return (Add(SSPA(),5)) }
+ }
+
+ } // device rhub
+} //scope
+
+//
+// SPT-H
+//
+
+ Scope(\_SB_.PC00.XHCI.RHUB) {
+
+
+
+ Device(HS11)
+ {
+ Name(_ADR, 0xB)
+ }
+
+
+ Device(HS12)
+ {
+ Name(_ADR, 0xC)
+ }
+
+ Device(HS13)
+ {
+ Name(_ADR, 0xD)
+ }
+
+ Device(HS14)
+ {
+ Name(_ADR, 0xE)
+ }
+
+ Device(SS07)
+ {
+ Method(_ADR) { Return (Add(SSPA(),6)) }
+ }
+
+ Device(SS08)
+ {
+ Method(_ADR) { Return (Add(SSPA(),7)) }
+ }
+
+ Device(SS09)
+ {
+ Method(_ADR) { Return (Add(SSPA(),8)) }
+ }
+
+ Device(SS10)
+ {
+ Method(_ADR) { Return (Add(SSPA(),9)) }
+ }
+
+ } //scope
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl
new file mode 100644
index 0000000000..cfacfdbfd4
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA1,0)) {
+ Return (RPA1)
+ } Else {
+ Return (0x001C0000)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl
new file mode 100644
index 0000000000..14d239597c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA2,0)) {
+ Return (RPA2)
+ } Else {
+ Return (0x001C0001)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl
new file mode 100644
index 0000000000..e116aa3fcf
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA3,0)) {
+ Return (RPA3)
+ } Else {
+ Return (0x001C0002)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl
new file mode 100644
index 0000000000..a89ba41f87
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA4,0)) {
+ Return (RPA4)
+ } Else {
+ Return (0x001C0003)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl
new file mode 100644
index 0000000000..82ac284b8c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA5,0)) {
+ Return (RPA5)
+ } Else {
+ Return (0x001C0004)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl
new file mode 100644
index 0000000000..153b4b3fce
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA6,0)) {
+ Return (RPA6)
+ } Else {
+ Return (0x001C0005)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl
new file mode 100644
index 0000000000..b8f93ff22b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA7,0)) {
+ Return (RPA7)
+ } Else {
+ Return (0x001C0006)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl
new file mode 100644
index 0000000000..ad786680b1
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA8,0)) {
+ Return (RPA8)
+ } Else {
+ Return (0x001C0007)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl
new file mode 100644
index 0000000000..8fea09fb6d
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPA9,0)) {
+ Return (RPA9)
+ } Else {
+ Return (0x001D0000)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl
new file mode 100644
index 0000000000..e5faa36089
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAA,0)) {
+ Return (RPAA)
+ } Else {
+ Return (0x001D0001)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl
new file mode 100644
index 0000000000..f35101300c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAB,0)) {
+ Return (RPAB)
+ } Else {
+ Return (0x001D0002)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl
new file mode 100644
index 0000000000..b8b8b305cd
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAC,0)) {
+ Return (RPAC)
+ } Else {
+ Return (0x001D0003)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl
new file mode 100644
index 0000000000..c81ce74af9
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAD,0)) {
+ Return (RPAD)
+ } Else {
+ Return (0x001D0004)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl
new file mode 100644
index 0000000000..3a79d7b90b
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAE,0)) {
+ Return (RPAE)
+ } Else {
+ Return (0x001D0005)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl
new file mode 100644
index 0000000000..6c5e812a02
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAF,0)) {
+ Return (RPAF)
+ } Else {
+ Return (0x001D0006)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl
new file mode 100644
index 0000000000..0099005840
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAG,0)) {
+ Return (RPAG)
+ } Else {
+ Return (0x001D0007)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl
new file mode 100644
index 0000000000..745d5523b0
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAH,0)) {
+ Return (RPAH)
+ } Else {
+ Return (0x001B0000)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl
new file mode 100644
index 0000000000..e32e1ab276
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAI,0)) {
+ Return (RPAI)
+ } Else {
+ Return (0x001B0001)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl
new file mode 100644
index 0000000000..06b8a23ab4
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAJ,0)) {
+ Return (RPAJ)
+ } Else {
+ Return (0x001B0002)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl
new file mode 100644
index 0000000000..baa96d405c
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl
@@ -0,0 +1,15 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (_ADR, 0) {
+ If (LNotEqual(RPAK,0)) {
+ Return (RPAK)
+ } Else {
+ Return (0x001B0003)
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl
new file mode 100644
index 0000000000..4c1dd36692
--- /dev/null
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl
@@ -0,0 +1,150 @@
+/** @file
+ Trace Hub debug library for ASL code.
+
+ @copyright
+ Copyright 2015 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+External(PTHM, IntObj)
+External(\_SB.PC00.PTHT.THEN, MethodObj, IntObj)
+External(\_SB.PTHH.THEN, MethodObj, IntObj)
+
+Name (THMN, 0x20) // Master number should align with gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster
+Name (THCN, 0x16) // Channel number could be different from gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel, 0~80h are available
+
+//
+// @note Only include register definition macros in ASL.
+// GCC will leak C function definitions in to ASL
+// code, causing compilation errors in some cases.
+//
+#include <PchReservedResources.h>
+#include <Register/PchRegsTraceHub.h>
+
+Scope(\) {
+ // Trace Hub debug address
+ // This is internal helper runtine of THDS
+ // Arg0 : Master number
+ // Arg1 : Channel number
+ Method (THDA, 2, Serialized) {
+ // Local0 = PCH_TRACE_HUB_SW_BASE_ADDRESS + 0x40 * (V_PCH_TRACE_HUB_MTB_CHLCNT * (Master - V_PCH_TRACE_HUB_MTB_STHMSTR)) + 0x40 * Channel;
+ Store (PCH_TRACE_HUB_SW_BASE_ADDRESS, Local0)
+ Add (Local0, Multiply (0x40, Multiply (V_PCH_TRACE_HUB_MTB_CHLCNT, Subtract (Arg0, V_PCH_TRACE_HUB_MTB_STHMSTR))), Local0)
+ Add (Local0, Multiply (0x40, Arg1), Local0)
+ Return (Local0)
+ }
+
+ // String to raw data
+ // This is internal helper runtine of THDS
+ // Arg0 : string
+ // Arg1 : Index
+ // Arg2 : size
+ Method (STRD, 3, Serialized) {
+ If (LGreater (Add (Arg1, Arg2), SizeOf (Arg0))) {
+ Return (0)
+ }
+ // Local0 is return value
+ // Lccal1 is loop index
+ // Local2 is char of string
+ // Local3 is buffer of string
+ ToBuffer (Arg0, Local3)
+ Store (0, Local0)
+ Store (0, Local1)
+ While (LLess (Local1, Arg2)) {
+ Store (DeRefOf (Index (Local3, Add (Arg1, Local1))), Local2)
+ Add (Local0, ShiftLeft (Local2, Multiply (8, Local1)), Local0)
+ Increment (Local1)
+ }
+ Return (Local0)
+ }
+
+ // Trace Hub debug string
+ // Arg0 : debug string
+ Method (THDS, 1, Serialized) {
+ //
+ // Check if BIOS trace is enabled.
+ //
+ If (LEqual (PTHM, 0)) {
+ Return
+ } ElseIf (LEqual (PTHM, 1)) {
+ If (LNot (\_SB.PC00.PTHT.THEN())) {
+ Return
+ }
+ } ElseIf (LEqual (PTHM, 2)) {
+ If (LNot (\_SB.PTHH.THEN())) {
+ Return
+ }
+ } Else {
+ Return
+ }
+
+ // Local0 is the length of string
+ // Local1 is the debug base address
+ Store (Sizeof (Arg0), Local0)
+ Store (THDA (THMN, THCN), Local1)
+ OperationRegion (THBA, SystemMemory, local1, 0x40)
+ Field (THBA, QWordAcc, NoLock, Preserve) {
+ Offset (0x00),
+ QO00, 64,
+ }
+ Field (THBA, DWordAcc, NoLock, Preserve) {
+ Offset (0x00),
+ DO00, 32,
+ Offset (0x10),
+ DO10, 32,
+ offset (0x30),
+ DO30, 32,
+ }
+ Field (THBA, WordAcc, NoLock, Preserve) {
+ Offset (0x00),
+ WO00, 16,
+ }
+ Field (THBA, ByteAcc, NoLock, Preserve) {
+ Offset (0x00),
+ BO00, 8,
+ }
+
+ // time stamp
+ Store (0x01000242, DO10)
+ // length of string
+ Store (Local0, WO00)
+ // string
+ Store (0, Local6)
+ Store (Local0, Local7)
+ while (LGreaterEqual(Local7, 8)) {
+ Store (STRD (Arg0, Local6, 8), QO00)
+ Add (Local6, 8, Local6)
+ Subtract (Local7, 8, Local7)
+ }
+ If (LGreaterEqual(Local7, 4)) {
+ Store (STRD (Arg0, Local6, 4), DO00)
+ Add (Local6, 4, Local6)
+ Subtract (Local7, 4, Local7)
+ }
+ If (LGreaterEqual(Local7, 2)) {
+ Store (STRD (Arg0, Local6, 2), WO00)
+ Add (Local6, 2, Local6)
+ Subtract (Local7, 2, Local7)
+ }
+ If (LGreaterEqual(Local7, 1)) {
+ Store (STRD (Arg0, Local6, 1), BO00)
+ Add (Local6, 1, Local6)
+ Subtract (Local7, 1, Local7)
+ }
+ // flag
+ Store (0, DO30)
+ }
+
+ // Trace Hub debug Hex string
+ // Arg0 : Integer, buffer
+ Method (THDH, 1, Serialized) {
+ THDS (ToHexString (Arg0))
+ }
+
+ // Trace Hub debug decimal string
+ // Arg0 : Integer, buffer
+ Method (THDD, 1, Serialized) {
+ THDS (ToDecimalString (Arg0))
+ }
+}
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index c4993cb897..e03ee6d5d8 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -19,6 +19,7 @@
Security/Include
Pch/SouthClusterLbg
Pch/SouthClusterLbg/Include
+ Pch/SouthClusterLbg/AcpiTables/Dsdt
Cpu/Include
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
` (2 preceding siblings ...)
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Oram, Isaac W
` (3 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
Static ACPI tables for WilsonCityRvp
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc | 54 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc | 81 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc | 72 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc | 171 ++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc | 972 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc | 61 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc | 74 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc | 68 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc | 137 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc | 44 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc | 136 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc | 89 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc | 53 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc | 74 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc | 74 ++
16 files changed, 2208 insertions(+)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc
new file mode 100644
index 0000000000..734f11200f
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc
@@ -0,0 +1,54 @@
+/** @file
+
+ @copyright
+ Copyright 2005 - 2012 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Bdat.h>
+
+//
+// Bdat Access Handler instance data structure
+//
+STATIC
+EFI_BDAT_ACPI_DESCRIPTION_TABLE mBdatAcpiTable = \
+{
+ {EFI_BDAT_TABLE_SIGNATURE, // Signature
+ sizeof (EFI_BDAT_ACPI_DESCRIPTION_TABLE), // Length
+ 0x01, // Revision [01]
+ //
+ // Checksum will be updated during boot
+ //
+ 0, // Checksum
+ {' ', // OEM ID
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '},
+ 0, // OEM Table ID
+ 0, // OEM Revision [0x00000000]
+ 0, // Creator ID
+ 0}, // Creator Revision
+ {0, // System Memory Address Space ID
+ 0,
+ 0,
+ 0,
+ //
+ // Pointer will be updated during boot
+ //
+ EFI_BDAT_ACPI_POINTER}
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ return (VOID*)&mBdatAcpiTable;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc
new file mode 100644
index 0000000000..dcad37ac05
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc
@@ -0,0 +1,81 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Acpi/Dbg2.h>
+
+
+DBG2_DEBUG_TABLE DBG2 =
+{
+ {
+ {EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE,
+ sizeof (DBG2_DEBUG_TABLE),
+ 0,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ {' ', ' ', ' ', ' ', ' ', ' '},
+
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ //
+ // Beginning of DBG2 specific fields
+ //
+ sizeof(EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE),
+ 1
+ },
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT),
+ 1,
+ 2,
+ sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT) + sizeof(EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE) + 4,
+ 0,
+ 0,
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550,
+ {0, 0},
+ sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT),
+ sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT) + sizeof(EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE)
+ },
+ {
+ EFI_ACPI_6_2_SYSTEM_IO,
+ 16,
+ 0,
+ EFI_ACPI_6_2_BYTE,
+ 0x3F8
+ },
+ 4,
+ "."
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&DBG2;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc
new file mode 100644
index 0000000000..48753f7939
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc
@@ -0,0 +1,72 @@
+/** @file
+
+ @copyright
+ Copyright 1996 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Facs.h>
+
+//
+// Firmware ACPI Control Structure
+// Please modify all values in Facs.h only.
+//
+EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+ //
+ // Hardware Signature will be updated at runtime
+ //
+ 0x00000000,
+
+ EFI_ACPI_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_GLOBAL_LOCK,
+ EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
+ EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ {EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE},
+ EFI_ACPI_OSPM_FLAGS,
+ {EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE}
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Facs;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc
new file mode 100644
index 0000000000..f37cf0a508
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc
@@ -0,0 +1,171 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+
+#include <Acpi/Fadt.h>
+
+//
+// Fixed ACPI Description Table
+// Please modify all values in Fadt.h only.
+//
+EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ {EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ {' ', ' ', ' ', ' ', ' ', ' '}, // OEMID
+ 0, // OEM Table ID
+ EFI_ACPI_OEM_FADT_REVISION,
+ 0, // Creator ID
+ 0}, // Creator Revision
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x00000000, // FIRMWARE_CTRL
+ 0x00000000, // DSDT
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_PREFERRED_PM_PROFILE,
+ EFI_ACPI_SCI_INT,
+ EFI_ACPI_SMI_CMD,
+ EFI_ACPI_ACPI_ENABLE,
+ EFI_ACPI_ACPI_DISABLE,
+ EFI_ACPI_S4_BIOS_REQ,
+ EFI_ACPI_PSTATE_CNT,
+
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS,
+ EFI_ACPI_GPE0_BLK_ADDRESS,
+ EFI_ACPI_GPE1_BLK_ADDRESS,
+ EFI_ACPI_PM1_EVT_LEN,
+ EFI_ACPI_PM1_CNT_LEN,
+ EFI_ACPI_PM2_CNT_LEN,
+ EFI_ACPI_PM_TMR_LEN,
+ EFI_ACPI_GPE0_BLK_LEN,
+ EFI_ACPI_GPE1_BLK_LEN,
+ EFI_ACPI_GPE1_BASE,
+
+ EFI_ACPI_CST_CNT,
+ EFI_ACPI_P_LVL2_LAT,
+ EFI_ACPI_P_LVL3_LAT,
+ EFI_ACPI_FLUSH_SIZE,
+ EFI_ACPI_FLUSH_STRIDE,
+ EFI_ACPI_DUTY_OFFSET,
+ EFI_ACPI_DUTY_WIDTH,
+ EFI_ACPI_DAY_ALRM,
+ EFI_ACPI_MON_ALRM,
+ EFI_ACPI_CENTURY,
+ EFI_ACPI_IAPC_BOOT_ARCH,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_FIXED_FEATURE_FLAGS | EFI_ACPI_6_2_SLP_BUTTON,
+ //
+ // Reset Register Block
+ //
+ {EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
+ EFI_ACPI_RESET_REG_BIT_WIDTH,
+ EFI_ACPI_RESET_REG_BIT_OFFSET,
+ EFI_ACPI_6_2_BYTE,
+ EFI_ACPI_RESET_REG_ADDRESS},
+
+ EFI_ACPI_RESET_VALUE,
+ EFI_ACPI_RESERVED_WORD, // EFI_ACPI_6_2_ARM_BOOT_ARCH
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x0000000000000000, // X_FIRMWARE_CTRL
+ 0x0000000000000000, // X_DSDT
+ //
+ // X_PM1a Event Register Block
+ //
+ {EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_WORD,
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS},
+ //
+ // X_PM1b Event Register Block
+ //
+ {EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_UNDEFINED,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS},
+ //
+ // X_PM1a Control Register Block
+ //
+ {EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_WORD,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS},
+ //
+ // X_PM1b Control Register Block
+ //
+ {EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_UNDEFINED,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS},
+ //
+ // X_PM2 Control Register Block
+ //
+ {EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_UNDEFINED,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS},
+ //
+ // X_PM Timer Control Register Block
+ //
+ {EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
+ EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_DWORD,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS},
+ //
+ // X_General Purpose Event 0 Register Block
+ //
+ {EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_GPE0_BLK_BIT_WIDTH,
+ EFI_ACPI_GPE0_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_BYTE,
+ EFI_ACPI_GPE0_BLK_ADDRESS},
+ //
+ // X_General Purpose Event 1 Register Block
+ //
+ {EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_GPE1_BLK_BIT_WIDTH,
+ EFI_ACPI_GPE1_BLK_BIT_OFFSET,
+ EFI_ACPI_6_2_UNDEFINED,
+ EFI_ACPI_GPE1_BLK_ADDRESS}
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable.
+ //
+ return (VOID*)&Fadt;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc
new file mode 100644
index 0000000000..ae6efeaee5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc
@@ -0,0 +1,972 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include "Acpi/Hmat.h"
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
+ {
+ // EFI_ACPI_DESCRIPTION_HEADER
+ {
+ EFI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE),
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION,
+ 0x00, // Checksum, updated at runtime
+ {' ', ' ', ' ', ' ', ' ', ' '}, // OEM ID, programmed at runtime
+ 0,
+ EFI_ACPI_OEM_HMAT_REVISION,
+ 0,
+ 0
+ }, // EFI_ACPI_DESCRIPTION_HEADER
+ (UINT32) 0
+ }, // EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
+
+ // Beginning of HMAT substructures
+#if EFI_ACPI_HMAT_MSARS_COUNT > 0
+ { // MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE[EFI_ACPI_HMAT_MSARS_COUNT]
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#if MC_MAX_NODE > 1
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 2
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 3
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 4
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 5
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 6
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 7
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 8
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 9
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 10
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 11
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 12
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 13
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 14
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+#if MC_MAX_NODE > 15
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+ MSARS_INIT()
+#endif
+ }, // MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE[EFI_ACPI_HMAT_MSARS_COUNT]
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 0
+ { // LATENCY_BANDWIDTH_INFO_STRUCTURE Lbis[EFI_ACPI_HMAT_LBIS_COUNT]
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#if EFI_ACPI_HMAT_LBIS_COUNT > 1
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 2
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 3
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 4
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 5
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 6
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 7
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 8
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 9
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 10
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+#if EFI_ACPI_HMAT_LBIS_COUNT > 11
+ LBIS_START()
+ RELATIVE_DISTANCE()
+#if MC_MAX_NODE > 1
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 2
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 3
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 4
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 5
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 6
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 7
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 8
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 9
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 10
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 11
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 12
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 13
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 14
+ RELATIVE_DISTANCE()
+#endif
+#if MC_MAX_NODE > 15
+ RELATIVE_DISTANCE()
+#endif
+ LBIS_END()
+#endif
+ }, // LATENCY_BANDWIDTH_INFO_STRUCTURE Lbis[EFI_ACPI_HMAT_LBIS_COUNT]
+#endif
+#if EFI_ACPI_HMAT_MSCIS_COUNT > 0
+ { // MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT]
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#if MC_MAX_NODE > 1
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 2
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 3
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 4
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 5
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 6
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 7
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 8
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 9
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 10
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 11
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 12
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 13
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 14
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+#if MC_MAX_NODE > 15
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+ MSCIS_INIT()
+#endif
+ }, // MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT]
+#endif
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Hmat;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc
new file mode 100644
index 0000000000..37b680ad6b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc
@@ -0,0 +1,61 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Hpet.h>
+
+//
+// High Precision Event Timer Table
+// Please modify all values in Hpet.h only.
+//
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = {
+ {EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, // Signature
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), // Length
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, // Revision [01]
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00, // Checksum
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ {' ',
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '},
+ 0,
+ EFI_ACPI_OEM_HPET_REVISION, // OEM Revision [0x00000001]
+ 0, // Creator ID
+ 0}, // Creator Revision
+ EFI_ACPI_EVENT_TIMER_BLOCK_ID, // Event Timer Block ID (4B) [0x8086A201]
+ {EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID, // 2 [EFI_ACPI_6_2_SYSTEM_MEMORY]
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH, // 3 [0x00]
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET, // 4 [0x00]
+ EFI_ACPI_EVENT_TIMER_ACCESS_SIZE, // [0x00]
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS}, // HPET Block BASE_ADDRESS (12B) [0x00000000FED00000]
+ EFI_ACPI_HPET_NUMBER, // HPET Number [00]
+ EFI_ACPI_MIN_CLOCK_TICK, // Main Counter Minimum Clock tick [0x0080]
+ EFI_ACPI_HPET_ATTRIBUTES // Page Protection & OEM attribute [0x00]
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Hpet;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc
new file mode 100644
index 0000000000..6e9a84aa49
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc
@@ -0,0 +1,74 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Mcfg.h>
+
+//
+// MCFG Table definition
+//
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE Mcfg = {
+ {{EFI_ACPI_6_2_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE),
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ {' ',
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '},
+
+ 0,
+ EFI_ACPI_OEM_MCFG_REVISION,
+ 0,
+ 0},
+ //
+ // Beginning of MCFG specific fields
+ //
+ EFI_ACPI_RESERVED_QWORD},
+ //
+ // Sample Memory Mapped Configuration Space Base Address Structure
+ //
+ // 0x0, // Base Address
+ // 0x0, // PCI Segment Group Number
+ // 0x0, // Start Bus Number
+ // 0x0, // End Bus Number
+ // EFI_ACPI_RESERVED_DWORD, // Reserved
+ //
+ // Memory Mapped Configuration Space Base Address Structure
+ //
+#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0
+ {{0x0, // Base Address, will be updated by AcpiPlatform
+ 0x0, // PCI Segment Group Number
+ 0x0, // Start Bus Number
+ 0xff, // End Bus Number
+ EFI_ACPI_RESERVED_DWORD}} // Reserved
+#endif // EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Mcfg;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc
new file mode 100644
index 0000000000..5efe5afee1
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc
@@ -0,0 +1,68 @@
+/** @file
+
+ @copyright
+ Copyright 2005 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Migt.h>
+
+//
+// Please modify all values in Migt.h only.
+//
+EFI_MIGT_ACPI_DESCRIPTION_TABLE Migt = {
+ {EFI_MIGT_ACPI_TABLE_SIGNATURE, // Signature
+ sizeof (EFI_MIGT_ACPI_DESCRIPTION_TABLE), // Length
+ EFI_MIGT_ACPI_DESCRIPTION_TABLE_REVISION, // Revision
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00, // Checksum
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ {' ',
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '},
+ 0,
+ EFI_MIGT_ACPI_OEM_REVISION, // OEM Revision
+ 0, // Creator ID
+ 0}, // Creator Revision
+ //
+ // MIGT Speicific Entries
+ // Control Register GAS structure
+ //
+ {EFI_MIGT_CR_ACPI_ADDRESS_SPACE_ID, // IO Type ID.
+ EFI_MIGT_CR_ACPI_REGISTER_BIT_WIDTH,
+ EFI_MIGT_CR_ACPI_REGISTER_BIT_OFFSET,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_MIGT_CR_ACPI_SMI_ADDRESS},
+
+ MIGT_SMI_SERVICE_ID, // SMI Door Bell
+
+ //
+ // Action Region GAS structure
+ //
+ {EFI_MIGT_AR_ACPI_ADDRESS_SPACE_ID, // Memory Type ID
+ EFI_MIGT_AR_ACPI_REGISTER_BIT_WIDTH,
+ EFI_MIGT_AR_ACPI_REGISTER_BIT_OFFSET,
+ EFI_ACPI_RESERVED_BYTE,
+ // update during boot
+ EFI_MIGT_AR_ACPI_MEMORY_ADDRESS}
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ return (VOID*)&Migt;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc
new file mode 100644
index 0000000000..e0e1bebd0a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc
@@ -0,0 +1,137 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Msct.h>
+
+//
+// Maximum System Characteristics Table definition
+//
+EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE Msct = {
+ {EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE), // Length
+ EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION, // Revision
+ 0x00, // Checksum will be updated at runtime
+ {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
+ 0, // OemTableId
+ EFI_ACPI_OEM_MSCT_REVISION, // OemRevision
+ EFI_ACPI_CREATOR_ID, // CreaterId
+ EFI_ACPI_CREATOR_REVISION}, // CreaterRevision
+ //
+ // Beginning of MSCT specific fields
+ //
+ 0x00000038, // OffsetProxDomInfo
+ MAX_SOCKET - 1, // MaxNumProxDom
+ 0x00000000, // MaxNumClockDom
+ 0x0000000000000000, // MaxPhysicalAddress
+ //
+ // Proximity Domain Information Structure 0
+ //
+ {{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+
+#if MAX_SOCKET > 1
+ //
+ // Proximity Domain Information Structure 1
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 2
+ //
+ // Proximity Domain Information Structure 2
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 3
+ //
+ // Proximity Domain Information Structure 3
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 4
+ //
+ // Proximity Domain Information Structure 4
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 5
+ //
+ // Proximity Domain Information Structure 5
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 6
+ //
+ // Proximity Domain Information Structure 6
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+
+#if MAX_SOCKET > 7
+ //
+ // Proximity Domain Information Structure 7
+ //
+ ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION, // Revision
+ sizeof (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE), // Length
+ 0x00000000, // ProxDomRangeLow
+ 0x00000000, // ProxDomRangeHigh
+ 0x00000000, // MaxProcessorCapacity
+ 0x0000000000000000} // MaxMemoryCapacity
+#endif
+ }
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ return (VOID*)&Msct;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc
new file mode 100644
index 0000000000..389c43ce3c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc
@@ -0,0 +1,48 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Nfit.h>
+
+//
+// NFIT Table
+// Please modify all values in Nfit.h only.
+//
+NVDIMM_FW_INTERFACE_TABLE Nfit = {
+ NVDIMM_FW_INTERFACE_TABLE_SIGNATURE, // Signature
+ sizeof (NVDIMM_FW_INTERFACE_TABLE), // Length
+ NVDIMM_FW_INTERFACE_TABLE_REVISION, // Revision [01]
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00, // Checksum
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ {' ', // TODO any other static values to be filled in?
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '}
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Nfit;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc
new file mode 100644
index 0000000000..e43c865c64
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc
@@ -0,0 +1,44 @@
+/** @file
+
+ @copyright
+ Copyright 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Pcat.h>
+
+//
+// PCAT Table
+// Please modify all values in Pcat.h only.
+//
+NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE Pcat = {
+ NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_SIGNATURE, // Signature
+ sizeof (NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE), // Length
+ NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_REVISION, // Revision
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00, // Checksum
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ {' '}, // TODO any other static values?
+
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Pcat;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc
new file mode 100644
index 0000000000..a0b4dc2756
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc
@@ -0,0 +1,136 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Pmtt.h>
+//
+// PMTT Table
+//
+#define PHYSICAL_COMP_IDENTIFIER \
+ {PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_DIMM_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ 0xFFFFFFFF}
+
+#define SLOT \
+ {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_SLOT_DEVICE) - sizeof(ACPI_PMTT_DIMM_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ PMTT_TYPE_SLOT_GUID, \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ PHYSICAL_COMP_IDENTIFIER}
+
+#define CHANNEL \
+ {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_CHANNEL_DEVICE) - MAX_DIMM * sizeof(ACPI_PMTT_SLOT_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ PMTT_TYPE_CHANNEL_GUID, \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ {SLOT, \
+ SLOT} \
+ }
+
+#define MEM_IMC \
+ {ACPI_TOP_LEVEL_IMC, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_IMC_DEVICE) - MAX_MC_CH * sizeof(ACPI_PMTT_CHANNEL_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ {CHANNEL, \
+ CHANNEL} \
+ }
+
+#define DIE \
+ {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_DIE_DEVICE) - MAX_IMC * sizeof(ACPI_PMTT_IMC_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ PMTT_TYPE_DIE_GUID, \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ {MEM_IMC, \
+ MEM_IMC, \
+ MEM_IMC, \
+ MEM_IMC}}
+
+#define SKT_LEVEL \
+ {ACPI_TOP_LEVEL_SOCKET, \
+ EFI_ACPI_RESERVED_BYTE, \
+ sizeof (ACPI_PMTT_SOCKET_DEVICE) - sizeof(ACPI_PMTT_DIE_DEVICE), \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ 0x00000000, \
+ 0x00000000, \
+ EFI_ACPI_RESERVED_BYTE, \
+ {DIE} \
+ },
+#pragma pack(1)
+
+ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE mPmttTable = {
+ {ACPI_PMTT_TABLE_SIGNATURE, // Signature 'PMTT'
+ sizeof (ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE), // Length
+ ACPI_PMTT_TABLE_REVISION, // Revision
+ 0x00, // CheckSum
+ {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
+ 0, // OemTableId
+ ACPI_PMTT_OEM_REVISION, // OemRevision
+ EFI_ACPI_CREATOR_ID, // CreaterId
+ EFI_ACPI_CREATOR_REVISION}, // CreaterRevision
+ 0, // NumOfMemoryDevices
+ { SKT_LEVEL
+#if MAX_SOCKET > 1
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 2
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 3
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 4
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 5
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 6
+ SKT_LEVEL
+#endif
+#if MAX_SOCKET > 7
+ SKT_LEVEL
+#endif
+ }
+};
+
+#pragma pack()
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+{
+ return (VOID*)&mPmttTable;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc
new file mode 100644
index 0000000000..26603102a2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc
@@ -0,0 +1,89 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2002 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Acpi/Spcr.h>
+
+//
+// Serial Port Console Redirection Table
+// Please modify all values in Spcr.h only.
+//
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ {EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE),
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ {' ', ' ', ' ', ' ', ' ', ' '},
+
+ 0,
+ EFI_ACPI_OEM_SPCR_REVISION,
+ 0,
+ 0},
+
+ //
+ // Beginning of SPCR specific fields
+ //
+ EFI_ACPI_INTERFACE_TYPE,
+ {EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE},
+
+ //
+ // Base Address Block
+ //
+ {EFI_ACPI_BASE_ADDRESS_ADDRESS_SPACE_ID,
+ EFI_ACPI_BASE_ADDRESS_BIT_WIDTH,
+ EFI_ACPI_BASE_ADDRESS_BIT_OFFSET,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_BASE_ADDRESS_ADDRESS},
+
+ EFI_ACPI_INTERRUPT_TYPE,
+ EFI_ACPI_IRQ,
+ EFI_ACPI_GLOBAL_SYSTEM_INTERRUPT,
+ EFI_ACPI_BAUD_RATE,
+ EFI_ACPI_PARITY,
+ EFI_ACPI_STOP_BITS,
+ EFI_ACPI_FLOW_CONTROL,
+ EFI_ACPI_TERMINAL_TYPE,
+ EFI_ACPI_LANGUAGE,
+ EFI_ACPI_PCI_DEVICE_ID,
+ EFI_ACPI_PCI_VENDOR_ID,
+ EFI_ACPI_PCI_BUS_NUMBER,
+ EFI_ACPI_PCI_DEVICE_NUMBER,
+ EFI_ACPI_PCI_FUNCTION_NUMBER,
+ EFI_ACPI_PCI_FLAGS,
+ EFI_ACPI_PCI_SEGMENT,
+ EFI_ACPI_RESERVED_DWORD
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Spcr;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc
new file mode 100644
index 0000000000..74855daee4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc
@@ -0,0 +1,53 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/Spmi.h>
+
+//
+// Server processor management interface table definition
+//
+EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE Spmi = {
+ {EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE), // Length
+ EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION, // Revision
+ 0x00, // Checksum will be updated at runtime
+ {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
+ 0, // OemTableId
+ EFI_ACPI_OEM_SPMI_REVISION, // OemRevision
+ 0, // CreaterId
+ 0}, // CreaterRevision
+ //
+ // Beginning of Spmi specific fields
+ //
+ 0x00, // InterfaceType
+ 0x01, // Reserved37, always 1
+ EFI_ACPI_SPMI_SPECIFICATION_REVISION, // SpecificationRevision
+ 0x00, // InterruptType
+ 0x00, // GPE
+ 0x00, // Reserved42
+ 0x00, // PciDeviceFlag
+ 0x00000000, // GlobalSystemInterrupt
+ {0x00, 0x00, 0x00, 0x00, 0x00}, // GAS
+ 0x00, // UidByte1
+ 0x00, // UidByte2
+ 0x00, // UidByte3
+ 0x00, // UidByte4
+ 0x00 // Reserved64
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ return (VOID*)&Spmi;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc
new file mode 100644
index 0000000000..fe0db504fd
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc
@@ -0,0 +1,74 @@
+/** @file
+
+ @copyright
+ Copyright 1999 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Statements that include other files
+//
+#include <Acpi/WatchdogDescriptionTable.h>
+#include <Acpi/Wddt.h>
+
+//
+// Watchdog Description Table , ACPI 6.2 compliant
+//
+EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE Wddt = {
+ {EFI_ACPI_WDDT_SIGNATURE,
+ sizeof (EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE),
+ EFI_ACPI_WDDT_DESCRIPTION_TABLE_REVISION,
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ {' ',
+ ' ',
+ ' ',
+ ' ',
+ ' ',
+ ' '},
+ 0,
+ 0,
+ 0,
+ 0},
+ //
+ // WDDT specific fields
+ //
+ //
+ // This is LPC bridge VID it must be patched in
+ //
+ 0,
+ EFI_ACPI_WDDT_SPEC_VERSION,
+ EFI_ACPI_WDDT_TABLE_VERSION,
+ //
+ // Base Address
+ //
+ {0x01,
+ 0xff,
+ 0x00,
+ 0x00,
+ //
+ // This is AcpiBase(PmBase)+60 and must be patched in
+ //
+ 0000},
+ EFI_ACPI_WDDT_TIMER_MAX_COUNT,
+ EFI_ACPI_WDDT_TIMER_MIN_VALUE,
+ EFI_ACPI_WDDT_TIMER_PERIOD_COUNT,
+ EFI_ACPI_WDDT_STATUS_AVAILABLE,
+ 00
+
+};
+
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ return (VOID*)&Wddt;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc
new file mode 100644
index 0000000000..83484b7cd7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc
@@ -0,0 +1,74 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2020 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+ //
+ // Statements that include other files
+ //
+
+#include <Acpi/Wsmt.h>
+
+ //
+ // Windows SMM Security Mitigations Table
+ // Please modify all values in Wsmt.h only.
+ //
+
+ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE Wsmt = {
+ //
+ // Header
+ //
+ {
+ ACPI_WSMT_SIGNATURE,
+ ACPI_WSMT_LENGTH,
+ EFI_ACPI_WSMT_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+ 0,
+ ACPI_OEM_WSMT_REVISION,
+ 0,
+ 0
+ },
+ //
+ // Protection Flags
+ //
+ {
+ { 0 }
+ }
+
+};
+
+#if defined (__GNUC__)
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Wsmt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+
+{
+}
+#endif
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
` (3 preceding siblings ...)
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options Oram, Isaac W
` (2 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
DSDT for WilsonCityRvp
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl | 20 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi | 346 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi | 205 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi | 730 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl | 61 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl | 19 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi | 137 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi | 183 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl | 1322 +++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi | 328 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi | 270 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi | 164 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi | 25 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi | 66 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi | 427 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi | 18 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi | 669 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl | 91 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi | 191 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi | 5388 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi | 219 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi | 163 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 1 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 1 +
39 files changed, 11912 insertions(+)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
new file mode 100644
index 0000000000..5480040545
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2009 - 2022 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformAcpiTable
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Fadt/Fadt62.aslc
+ Facs/Facs62.aslc
+ Dsdt/EPRPPlatform10nm.asl
+ Mcfg/Mcfg.aslc
+ Hpet/Hpet.aslc
+ NFIT/Nfit.aslc
+ PCAT/Pcat.aslc
+
+ SPCR/Spcr.aslc
+ Msct/Msct.aslc
+ Wddt/Wddt1.0.aslc
+ Bdat/Bdat.aslc
+
+ Migt/Migt.aslc
+ DBG2/DBG2.aslc
+ Spmi/Spmi.aslc
+ Pmtt/Pmtt10nm.aslc
+ Hmat/Hmat.aslc
+
+ Wsmt/Wsmt.aslc
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount
+ gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl
new file mode 100644
index 0000000000..3b46dd84df
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl
@@ -0,0 +1,20 @@
+/** @file
+ ACPI DSDT table
+
+ @copyright
+ Copyright 2011 - 2014 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+///////////////////////////////////////////////////////////////////////////////////
+//Values are set like this to have ASL compiler reserve enough space for objects
+///////////////////////////////////////////////////////////////////////////////////
+//
+// Available Sleep states
+//
+Name(SS1,0)
+Name(SS2,0)
+Name(SS3,1)
+Name(SS4,1)
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi
new file mode 100644
index 0000000000..4e49adc10c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi
@@ -0,0 +1,346 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // BIOS parameters region left in memory for ASL by POST code, defined as BIOS_ACPI_PARAM in GlobalNvsArea.h.
+ //
+ OperationRegion (PSYS, SystemMemory, 0x30584946, 0x800) // (FIX0 - Patched by ACPI Platform Driver during POST)
+ Field (PSYS, ByteAcc, NoLock, Preserve) {
+ // IOAPIC Start
+ PLAT , 32, // Platform ID
+
+ Offset (0x04), //
+ APCE , 1, // PCH IOAPIC Enable
+ AP00 , 1, // PC00 IOAPIC Enable S0
+ AP01 , 1, // PC01 IOAPIC Enable
+ AP02 , 1, // PC02 IOAPIC Enable
+ AP03 , 1, // PC03 IOAPIC Enable
+ AP04 , 1, // PC04 IOAPIC Enable
+ AP05 , 1, // PC05 IOAPIC Enable
+ AP06 , 1, // PC06 IOAPIC Enable S1
+ AP07 , 1, // PC07 IOAPIC Enable
+ AP08 , 1, // PC08 IOAPIC Enable
+ AP09 , 1, // PC09 IOAPIC Enable
+ AP10 , 1, // PC10 IOAPIC Enable
+ AP11 , 1, // PC11 IOAPIC Enable
+ AP12 , 1, // PC12 IOAPIC Enable S2
+ AP13 , 1, // PC13 IOAPIC Enable
+ AP14 , 1, // PC14 IOAPIC Enable
+ AP15 , 1, // PC15 IOAPIC Enable
+ AP16 , 1, // PC16 IOAPIC Enable
+ AP17 , 1, // PC17 IOAPIC Enable
+ AP18 , 1, // PC18 IOAPIC Enable S3
+ AP19 , 1, // PC19 IOAPIC Enable
+ AP20 , 1, // PC20 IOAPIC Enable
+ AP21 , 1, // PC21 IOAPIC Enable
+ AP22 , 1, // PC22 IOAPIC Enable
+ AP23 , 1, // PC23 IOAPIC Enable
+ AP24 , 1, // PC24 IOAPIC Enable S4
+ AP25 , 1, // PC25 IOAPIC Enable
+ AP26 , 1, // PC26 IOAPIC Enable
+ AP27 , 1, // PC27 IOAPIC Enable
+ AP28 , 1, // PC28 IOAPIC Enable
+ AP29 , 1, // PC29 IOAPIC Enable
+ AP30 , 1, // PC30 IOAPIC Enable S5
+ AP31 , 1, // PC31 IOAPIC Enable
+ AP32 , 1, // PC32 IOAPIC Enable
+ AP33 , 1, // PC33 IOAPIC Enable
+ AP34 , 1, // PC34 IOAPIC Enable
+ AP35 , 1, // PC35 IOAPIC Enable
+ AP36 , 1, // PC36 IOAPIC Enable S6
+ AP37 , 1, // PC37 IOAPIC Enable
+ AP38 , 1, // PC38 IOAPIC Enable
+ AP39 , 1, // PC39 IOAPIC Enable
+ AP40 , 1, // PC40 IOAPIC Enable
+ AP41 , 1, // PC41 IOAPIC Enable
+ AP42 , 1, // PC42 IOAPIC Enable S7
+ AP43 , 1, // PC43 IOAPIC Enable
+ AP44 , 1, // PC44 IOAPIC Enable
+ AP45 , 1, // PC45 IOAPIC Enable
+ AP46 , 1, // PC46 IOAPIC Enable
+ AP47 , 1, // PC47 IOAPIC Enable
+ RESA , 15,
+
+ Offset (0x0C),
+ SKOV , 1, // Override ApicId socket field
+ P119 , 1, // PCH IOAPIC 24_119 enabled
+ CPX4 , 1, // 1 = CPX4, 0 = CPX6
+ RES0 , 5, // Unused
+ // IOAPIC End
+
+ // Power Managment Start
+ Offset (0x0D),
+ TPME , 1, // TPM Enable
+ CSEN , 1, // C State Enable
+ C3EN , 1, // OS C3 Report Enbale
+ C6EN , 1, // C6 Enable
+ C7EN , 1, // C7 Enable
+ MWOS , 1, // MWAIT support Enable
+ PSEN , 1, // P State Enable
+ EMCA , 1, // EMCA Enable
+ Offset (0x0E),
+ HWAL , 2, // PSD HW_ALL Enable
+ KPRS , 1, // KB present Flag
+ MPRS , 1, // Mouse present Flag
+ TSEN , 1, // T State Enable Flag
+ FGTS , 1, // Fine grained T state Flag
+ OSCX , 1, // OS C States
+ RESX , 1, // Unused
+ // Power Management End
+
+ // RAS Start
+ Offset (0x0F),
+ CPHP , 8, // Bit field for determining CPU hotplug event is happening, Update every time CPU Hotpug event is registered as valid
+ // Bit0 CPU0 O*L Request
+ // Bit1 CPU1 O*L Request
+ // Bit2 CPU2 O*L Request
+ // Bit3 CPU3 O*L Request
+ // Bit4 CPU4 O*L Request
+ // Bit5 CPU5 O*L Request
+ // Bit6 CPU6 O*L Request
+ // Bit7 CPU7 O*L Request
+ IIOP , 8, // Bit field for determining IIO hotplug event is happening, Update every time IIO Hotpug event is registered as valid
+ // Bit0 IIO1 O*L Request
+ // Bit1 IIO2 O*L Request
+ // Bit2 IIO3 O*L Request
+ // Bit3-7 Reserved
+ SPB0 , 16, // Stack Present Bitmask in socket0, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB1 , 16, // Stack Present Bitmask in socket1, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB2 , 16, // Stack Present Bitmask in socket2, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB3 , 16, // Stack Present Bitmask in socket3, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB4 , 16, // Stack Present Bitmask in socket4, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB5 , 16, // Stack Present Bitmask in socket5, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB6 , 16, // Stack Present Bitmask in socket6, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ SPB7 , 16, // Stack Present Bitmask in socket7, what stacks are present for STA method (Patched by ACPI Platform Driver during POST)
+ PRBM , 32, // Processor Bit mask, what sockets are present for STA method, Update every time hotplug event happen and at boot time (Patched by ACPI Platform Driver during POST)
+ CTHC , 8, // CPU Core Thread Count
+ P0ID , 32, // Processor 0 APIC ID base
+ P1ID , 32, // Processor 1 APIC ID base
+ P2ID , 32, // Processor 2 APIC ID base
+ P3ID , 32, // Processor 3 APIC ID base
+ P4ID , 32, // Processor 4 APIC ID base
+ P5ID , 32, // Processor 5 APIC ID base
+ P6ID , 32, // Processor 6 APIC ID base
+ P7ID , 32, // Processor 7 APIC ID base
+ P0BM , 64, // Processor 0 Bit mask, what cores (0-63) are present for STA method
+ P1BM , 64, // Processor 1 Bit mask, what cores (0-63) are present for STA method
+ P2BM , 64, // Processor 2 Bit mask, what cores (0-63) are present for STA method
+ P3BM , 64, // Processor 3 Bit mask, what cores (0-63) are present for STA method
+ P4BM , 64, // Processor 4 Bit mask, what cores (0-63) are present for STA method
+ P5BM , 64, // Processor 5 Bit mask, what cores (0-63) are present for STA method
+ P6BM , 64, // Processor 6 Bit mask, what cores (0-63) are present for STA method
+ P7BM , 64, // Processor 7 Bit mask, what cores (0-63) are present for STA method
+ P0BH , 64, // Processor 0 Bit mask, what cores (64-127) are present for STA method
+ P1BH , 64, // Processor 1 Bit mask, what cores (64-127) are present for STA method
+ P2BH , 64, // Processor 2 Bit mask, what cores (64-127) are present for STA method
+ P3BH , 64, // Processor 3 Bit mask, what cores (64-127) are present for STA method
+ P4BH , 64, // Processor 4 Bit mask, what cores (64-127) are present for STA method
+ P5BH , 64, // Processor 5 Bit mask, what cores (64-127) are present for STA method
+ P6BH , 64, // Processor 6 Bit mask, what cores (64-127) are present for STA method
+ P7BH , 64, // Processor 7 Bit mask, what cores (64-127) are present for STA method
+ CFMM , 32, // MMCFG Base
+ TSSZ , 32, // TSEG Size.
+ SMI0 , 32, // Parameter0 used for faked SMI request
+ SMI1 , 32, // Parameter1 used for faked SMI request
+ SMI2 , 32, // Parameter2 used for faked SMI request
+ SMI3 , 32, // Parameter3 used for faked SMI request
+ SCI0 , 32, // Parameter0 used for faked SCI request
+ SCI1 , 32, // Parameter1 used for faked SCI request
+ SCI2 , 32, // Parameter2 used for faked SCI request
+ SCI3 , 32, // Parameter3 used for faked SCI request
+ MADD , 64, // Migration ActionRegion GAS address. (Migration support written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 are invalid.)
+ CUU0 , 128, // CPU0 UUID
+ CUU1 , 128, // CPU1 UUID
+ CUU2 , 128, // CPU2 UUID
+ CUU3 , 128, // CPU3 UUID
+ CUU4 , 128, // CPU4 UUID
+ CUU5 , 128, // CPU5 UUID
+ CUU6 , 128, // CPU6 UUID
+ CUU7 , 128, // CPU7 UUID
+ CPSP , 8, // CPU spare bitmap. 1 == IsSpare.
+ ME00 , 128, // MEM0 UUID
+ ME01 , 128, // MEM1 UUID
+ ME10 , 128, // MEM2 UUID
+ ME11 , 128, // MEM3 UUID
+ ME20 , 128, // MEM4 UUID
+ ME21 , 128, // MEM5 UUID
+ ME30 , 128, // MEM6 UUID
+ ME31 , 128, // MEM7 UUID
+ ME40 , 128, // MEM8 UUID
+ ME41 , 128, // MEM9 UUID
+ ME50 , 128, // MEM10 UUID
+ ME51 , 128, // MEM11 UUID
+ ME60 , 128, // MEM12 UUID
+ ME61 , 128, // MEM13 UUID
+ ME70 , 128, // MEM14 UUID
+ ME71 , 128, // MEM15 UUID
+ LDIR , 64, // L1 Directory Address
+ PRID , 32, // Processor ID
+ AHPE , 8, // ACPI PCIe hot plug enable.
+ WHEN , 8,
+ WSCI , 8,
+ SERR , 8, // Propogate SERR
+ PERR , 8, // Propogate PERR
+ // RAS End
+
+ // VTD Start
+ DHRD , 192, // DHRD
+ ATSR , 192, // ATSR
+ RHSA , 192, // RHSA
+ // VTD End
+
+ // SR-IOV WA Start
+ WSIC , 8,
+ WSIS , 16,
+ WSIB , 8,
+ WSID , 8,
+ WSIF , 8,
+ WSTS , 8,
+ WHEA , 8,
+ // SR-IOV WA End
+
+ // BIOS Guard Start
+ BGMA , 64, // BIOS Guard Memory Address
+ BGMS , 8, // BIOS Guard Memory Size
+ BGIO , 16, // BIOS Guard IO Trap Address
+ CNBS , 8, // CPU SKU number bit shift
+ // BIOS Guard End
+
+ // USB3 Start
+ XHMD , 8, // copy of setup item PchUsb30Mode
+ SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1)
+ SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2)
+ // USB3 End
+
+ // HWPM Start
+ HWEN , 2, // HWPM State Enable option from setup
+ RES2 , 1, // Reserved bit
+ HWPI , 1, // HWP Interrupt
+ RES1 , 4, // Reserved bits
+ // HWPM End
+
+ // SGX Start
+ EPCS , 8, // EPC Status
+ ELN0 , 64, // EPC0 Length
+ ELN1 , 64, // EPC1 Length
+ ELN2 , 64, // EPC2 Length
+ ELN3 , 64, // EPC3 Length
+ ELN4 , 64, // EPC4 Length
+ ELN5 , 64, // EPC5 Length
+ ELN6 , 64, // EPC6 Length
+ ELN7 , 64, // EPC7 Length
+ EBA0 , 64, // EPC0 Base Address
+ EBA1 , 64, // EPC1 Base Address
+ EBA2 , 64, // EPC2 Base Address
+ EBA3 , 64, // EPC3 Base Address
+ EBA4 , 64, // EPC4 Base Address
+ EBA5 , 64, // EPC5 Base Address
+ EBA6 , 64, // EPC6 Base Address
+ EBA7 , 64, // EPC7 Base Address
+ // SGX End
+
+ // PCIe Multi-Seg Start
+ // Stack bus base numbers for up to 14 stacks in up to 8 socket. Name is 'BB<skt><stk>', where <skt> and <stk> are hex.
+ BB00, 8, BB01, 8, BB02, 8, BB03, 8, BB04, 8, BB05, 8, BB06, 8, BB07, 8, BB08, 8, BB09, 8, BB0A, 8, BB0B, 8, BB0C, 8, BB0D, 8,
+ BB10, 8, BB11, 8, BB12, 8, BB13, 8, BB14, 8, BB15, 8, BB16, 8, BB17, 8, BB18, 8, BB19, 8, BB1A, 8, BB1B, 8, BB1C, 8, BB1D, 8,
+ BB20, 8, BB21, 8, BB22, 8, BB23, 8, BB24, 8, BB25, 8, BB26, 8, BB27, 8, BB28, 8, BB29, 8, BB2A, 8, BB2B, 8, BB2C, 8, BB2D, 8,
+ BB30, 8, BB31, 8, BB32, 8, BB33, 8, BB34, 8, BB35, 8, BB36, 8, BB37, 8, BB38, 8, BB39, 8, BB3A, 8, BB3B, 8, BB3C, 8, BB3D, 8,
+ BB40, 8, BB41, 8, BB42, 8, BB43, 8, BB44, 8, BB45, 8, BB46, 8, BB47, 8, BB48, 8, BB49, 8, BB4A, 8, BB4B, 8, BB4C, 8, BB4D, 8,
+ BB50, 8, BB51, 8, BB52, 8, BB53, 8, BB54, 8, BB55, 8, BB56, 8, BB57, 8, BB58, 8, BB59, 8, BB5A, 8, BB5B, 8, BB5C, 8, BB5D, 8,
+ BB60, 8, BB61, 8, BB62, 8, BB63, 8, BB64, 8, BB65, 8, BB66, 8, BB67, 8, BB68, 8, BB69, 8, BB6A, 8, BB6B, 8, BB6C, 8, BB6D, 8,
+ BB70, 8, BB71, 8, BB72, 8, BB73, 8, BB74, 8, BB75, 8, BB76, 8, BB77, 8, BB78, 8, BB79, 8, BB7A, 8, BB7B, 8, BB7C, 8, BB7D, 8,
+
+ SGEN , 8, // PCIe_MultiSeg_Support enable/disable
+ SG00 , 8, // PCI segment ID for socket 0
+ SG01 , 8, // PCI segment ID for socket 1
+ SG02 , 8, // PCI segment ID for socket 2
+ SG03 , 8, // PCI segment ID for socket 3
+ SG04 , 8, // PCI segment ID for socket 4
+ SG05 , 8, // PCI segment ID for socket 5
+ SG06 , 8, // PCI segment ID for socket 6
+ SG07 , 8, // PCI segment ID for socket 7
+ // PCIe Multi-Seg End
+
+ // Sub-NUMA Cluster support
+ CLOD , 8, // 0 - SNC disabled, 2 - SNC enabled with 2 clusters, 4 - SNC enabled with 4 clusters
+
+ // XTU Start
+ XTUB , 32,
+ XTUS , 32,
+ XMBA , 32,
+ DDRF , 8,
+ RT3S , 8,
+ RTP0 , 8,
+ RTP3 , 8,
+ // XTU End
+
+ // FPGA Root Port Bus
+ FBB0 , 8, // FPGA Bus Base for Socket 0
+ FBB1 , 8, // FPGA Bus Base for Socket 1
+ FBB2 , 8, // FPGA Bus Base for Socket 2
+ FBB3 , 8, // FPGA Bus Base for Socket 3
+ FBB4 , 8, // FPGA Bus Base for Socket 4
+ FBB5 , 8, // FPGA Bus Base for Socket 5
+ FBB6 , 8, // FPGA Bus Base for Socket 6
+ FBB7 , 8, // FPGA Bus Base for Socket 7
+
+ FBL0 , 8, // FPGA Bus limit for Socket 0
+ FBL1 , 8, // FPGA Bus limit for Socket 1
+ FBL2 , 8, // FPGA Bus limit for Socket 2
+ FBL3 , 8, // FPGA Bus limit for Socket 3
+ FBL4 , 8, // FPGA Bus limit for Socket 4
+ FBL5 , 8, // FPGA Bus limit for Socket 5
+ FBL6 , 8, // FPGA Bus limit for Socket 6
+ FBL7 , 8, // FPGA Bus limit for Socket 7
+
+ // FPGA present bit
+ P0FB , 8, // FPGA present in Socket 0
+ P1FB , 8, // FPGA present in Socket 1
+ P2FB , 8, // FPGA present in Socket 2
+ P3FB , 8, // FPGA present in Socket 3
+ P4FB , 8, // FPGA present in Socket 4
+ P5FB , 8, // FPGA present in Socket 5
+ P6FB , 8, // FPGA present in Socket 6
+ P7FB , 8, // FPGA present in Socket 7
+
+ // FPGA Resource Allocation
+ FMB0 , 32,
+ FMB1 , 32,
+ FMB2 , 32,
+ FMB3 , 32,
+ FMB4 , 32,
+ FMB5 , 32,
+ FMB6 , 32,
+ FMB7 , 32,
+
+ FML0 , 32,
+ FML1 , 32,
+ FML2 , 32,
+ FML3 , 32,
+ FML4 , 32,
+ FML5 , 32,
+ FML6 , 32,
+ FML7 , 32,
+
+ // FPGA KTI present bitmap
+ FKPB , 32,
+ // FPGA Bus for KTI
+ FKB0 , 8, // FPGA Bus Base for Socket 0 KTI Link
+ FKB1 , 8, // FPGA Bus Base for Socket 1 KTI Link
+ FKB2 , 8, // FPGA Bus Base for Socket 2 KTI Link
+ FKB3 , 8, // FPGA Bus Base for Socket 3 KTI Link
+ FKB4 , 8, // FPGA Bus Base for Socket 4 KTI Link
+ FKB5 , 8, // FPGA Bus Base for Socket 5 KTI Link
+ FKB6 , 8, // FPGA Bus Base for Socket 6 KTI Link
+ FKB7 , 8, // FPGA Bus Base for Socket 7 KTI Link
+
+ PMBA , 16, // ACPI IO Base Address
+ DBGM , 8, // Debug Mode Indicator
+ IRPC , 8, // IIO PCIe root port PCIe Capability offset
+ ATSC , 8, // Flag to indicate if TSC is linked to ART
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
new file mode 100644
index 0000000000..28a997b102
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
@@ -0,0 +1,205 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "MaxSocket.h"
+
+ //
+ // External declarations
+ // HECI-1/HECI-2 are in 10nmServerPlatformPkg\Me\Sps\Acpi\SpsNm.asl
+ //
+ External(\_SB.PC00.HEC2.HPTS, MethodObj)
+ External(\_SB.PC00.HEC2.HWAK, MethodObj)
+
+ External(\_SB.OSPC, MethodObj)
+ //
+ // System Sleep States
+ //
+ Name (\_S0,Package (){0,0,0,0})
+ Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in Setup
+ Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in Setup
+ Name (\_S5,Package (){7,0,0,0})
+
+ //
+ // Native OS hot plug support, 0->ACPI, 1->OS
+ //
+ Name (\OSHF, 0)
+
+ Name (\HWPS, 0) // CPC capability from platform _OSC
+
+ //
+ // OS flag
+ //
+ #include "Os.asi"
+
+ //
+ // for determing PIC mode
+ //
+ Name (\PICM,Zero)
+ Method (\_PIC, 1, NotSerialized) {
+ Store(Arg0,\PICM)
+ }
+
+ OperationRegion (DBG0, SystemIO, 0x80, 2)
+ Field (DBG0, ByteAcc,NoLock,Preserve) {
+ IO80, 8,
+ IO81, 8
+ }
+
+ //
+ // Access CMOS range
+ //
+ OperationRegion (ACMS, SystemIO, 0x72, 2)
+ Field ( ACMS, ByteAcc, NoLock, Preserve) {
+ INDX, 8,
+ DATA, 8
+ }
+
+
+ //
+ // BIOS parameter BIOS_ACPI_PARAM
+ //
+ #include "BiosParameterRegion.asi"
+
+ //
+ // SWGPE_CTRL
+ //
+ OperationRegion (GPCT, SystemIO, Add (PMBA, 0x42), 1)
+ Field (GPCT, ByteAcc, NoLock, Preserve) {
+ , 1,
+ SGPC , 1,
+ }
+
+ //
+ // GPE0 Enable
+ //
+ OperationRegion (GPE0, SystemIO, Add (PMBA, 0x9C), 4)
+ Field (GPE0, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPEH,1,
+ ,7,
+ PCIE,1,
+ ,1,
+ PMEE,1,
+ ,1,
+ PMB0,1,
+ ,18,
+ }
+
+ //
+ // GPE0 Status
+ //
+ OperationRegion (GPES, SystemIO, Add (PMBA, 0x8C), 4)
+ Field (GPES, ByteAcc,NoLock,Preserve) {
+ ,1,
+ GPSH,1,
+ SGPS,1,
+ ,6,
+ PEES,1,
+ ,1,
+ PMES,1,
+ ,1,
+ PMEB,1,
+ ,18,
+ }
+
+ //
+ // System sleep down
+ //
+ Method (_PTS, 1, NotSerialized)
+ {
+ Store (0x72, IO80) // Sync with EfiPostCode.h
+
+ //
+ // Clear wake event status.
+ //
+ Store(1,PMES)
+ Store(1,PMEB)
+
+ //
+ // Enable SCI and wake event sources.
+ //
+ Store(1,GPEH)
+ Store(1,PCIE)
+ Store(1,PMEE)
+ Store(1,PMB0)
+
+ //
+ // If HECI-2 exist call its prepare-to-sleep handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HPTS))
+ {
+ \_SB.PC00.HEC2.HPTS()
+ }
+
+ /// WA for S3 on XHCI
+ \_SB.PC00.XHCI.XHCS()
+ }
+
+
+ //
+ // System Wake up
+ //
+ Method (_WAK, 1, Serialized)
+ {
+ Store (0x73, IO80) // Sync with EfiPostCode.h
+
+ //
+ // If HECI-2 exist call its wake-up handler.
+ // The handler checks whether HECI-2 is enabled.
+ //
+ If (CondRefOf(\_SB.PC00.HEC2.HWAK))
+ {
+ \_SB.PC00.HEC2.HWAK()
+ }
+
+ //
+ // If waking from S3
+ //
+ If (LEqual(Arg0, 3)) {
+ }
+
+ Return(Package(){0, 0})
+ }
+
+ Scope(\_SB) {
+
+ // Information on CPU and Memory for hotplug SKUs
+ #include "CpuMemHp.asi"
+
+ OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
+ Field (IOB2, ByteAcc, NoLock, Preserve) {
+ SMIC, 8, // SW-SMI ctrl port
+ SMIS, 8, // SW-SMI status port
+ }
+
+ Method(_OSC , 4) {
+ Store(Arg3,Local0)
+ CreateDWordField(Local0,4,CPBF)
+ If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) {
+ //Save Platform OSC HWPM capabilities
+ If(LEqual(And(CPBF, 0x00000040), 0x00000040)) {
+ Store(1,HWPS)
+ }
+ }
+ If (CondRefOf (\_SB.OSPC)) {
+ Return (\_SB.OSPC(Arg0, Arg1, Arg2, Arg3))
+ }
+ Return (Local0)
+ }
+ //
+ // SGX
+ //
+ #include "Sgx.asi"
+ //
+ // Common Hot Plug for PCxx devices
+ //
+ #include "IioRootBridgeIcx.asi"
+ } // end _SB scope
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi
new file mode 100644
index 0000000000..a0824a30c0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi
@@ -0,0 +1,730 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "MaxSocket.h"
+
+#define HECI_CMD_CPUHOTPLUG 1
+#define HECI_CMD_CPUHOTREMOVE 2
+
+#define SIZE_LAPIC_STRUC 8
+#define LAPIC_TYPE 0
+
+#define SIZE_X2LAPIC_STRUC 16
+#define X2LAPIC_TYPE 9
+
+#define MAK_STR(x) #x
+
+//
+// This macro creates method that calculates
+// number of active threads for its socket
+//
+#define CPU_THREADS_NUM(socket) \
+ Method(THNU, 0) { \
+ Store(0, Local0) \
+ Store(P##socket##BM, Local1) \
+ While (Local1) { \
+ Add(Local0, And(Local1, 1), Local0) \
+ ShiftRight(Local1, 1, Local1) \
+ } \
+ return (Or(ShiftLeft(socket, 8), Local0)) \
+ }
+
+//
+//set DevName ProcId field and IO to C##thread
+//
+#define CPU_THREAD_DEV(socket, thread) \
+ Device(C##thread) { \
+ Name(_HID, "ACPI0007") \
+ Method (_UID) { \
+ Return (\_SB.CUID(0x0##socket, 0x##thread)) \
+ } \
+ Method(_PXM) { \
+ if (LEqual (CLOD, 0)) { \
+ Return(0x0##socket) \
+ } else { \
+ Store(DerefOf(Index(\_SB.APT##socket, 0x##thread)), Local0) \
+ Store(CNBS, Local1) \
+ Subtract(Local1, 1, Local1) \
+ ShiftRight(Local0, Local1, Local0) \
+ And(Local0, 1, Local0) \
+ Store(0x##socket, Local1) \
+ Multiply(Local1, 2, Local1) \
+ if(LEqual(Local0, 1)) { \
+ Add(Local1, 1, Local1) \
+ } \
+ Return(Local1) \
+ } \
+ } \
+ Method(_STA) { \
+ if(LEqual(\_SB.CSTA(0x0##socket, 0x##thread), 0x00)) { \
+ Return(0x00) \
+ } else { \
+ If (LGreaterEqual (\_SB.OSYS, 12)) { \
+ Return(0x0F) \
+ } Else { \
+ Return(0x0B) \
+ } \
+ } \
+ } \
+ Method(_MAT) { \
+ if(SKOV) { \
+ Return(\_SB.X2AP(0x0##socket, 0x##thread)) \
+ } else { \
+ Return(\_SB.LAPC(0x0##socket, 0x##thread)) \
+ } \
+ } \
+ }
+
+#define CPU_SOCKET_DEV(socket) \
+ Device(\_SB.SCK##socket) { \
+ Name (_HID, "ACPI0004") \
+ Name (_UID, MAK_STR(CPUSCK##socket)) \
+ Name (LSTA, 0xff) \
+ Method(_STA) { \
+ Store(MAK_STR(CPUSCK##socket), CUU##socket) \
+ Store(\_SB.PSTA(0x0##socket), Local0) \
+ And(Local0, 0x03, Local1) \
+ If (LAnd(LNotEqual(LSTA, 0xff), LNotEqual(Local1, LSTA))) { \
+ If (LEqual(Local1, 0x03)) { \
+ /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTPLUG, socket, THNU) TODO: Obsolete with _PUR?*/\
+ } Else { \
+ /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTREMOVE, socket, THNU) TODO: Obsolete with _PUR?*/\
+ } \
+ } \
+ Store(Local1, LSTA) \
+ return(Local0) \
+ } \
+ \
+ CPU_THREADS_NUM(socket) \
+ CPU_THREAD_DEV (socket, 000) \
+ CPU_THREAD_DEV (socket, 001) \
+ CPU_THREAD_DEV (socket, 002) \
+ CPU_THREAD_DEV (socket, 003) \
+ CPU_THREAD_DEV (socket, 004) \
+ CPU_THREAD_DEV (socket, 005) \
+ CPU_THREAD_DEV (socket, 006) \
+ CPU_THREAD_DEV (socket, 007) \
+ CPU_THREAD_DEV (socket, 008) \
+ CPU_THREAD_DEV (socket, 009) \
+ CPU_THREAD_DEV (socket, 00A) \
+ CPU_THREAD_DEV (socket, 00B) \
+ CPU_THREAD_DEV (socket, 00C) \
+ CPU_THREAD_DEV (socket, 00D) \
+ CPU_THREAD_DEV (socket, 00E) \
+ CPU_THREAD_DEV (socket, 00F) \
+ CPU_THREAD_DEV (socket, 010) \
+ CPU_THREAD_DEV (socket, 011) \
+ CPU_THREAD_DEV (socket, 012) \
+ CPU_THREAD_DEV (socket, 013) \
+ CPU_THREAD_DEV (socket, 014) \
+ CPU_THREAD_DEV (socket, 015) \
+ CPU_THREAD_DEV (socket, 016) \
+ CPU_THREAD_DEV (socket, 017) \
+ CPU_THREAD_DEV (socket, 018) \
+ CPU_THREAD_DEV (socket, 019) \
+ CPU_THREAD_DEV (socket, 01A) \
+ CPU_THREAD_DEV (socket, 01B) \
+ CPU_THREAD_DEV (socket, 01C) \
+ CPU_THREAD_DEV (socket, 01D) \
+ CPU_THREAD_DEV (socket, 01E) \
+ CPU_THREAD_DEV (socket, 01F) \
+ CPU_THREAD_DEV (socket, 020) \
+ CPU_THREAD_DEV (socket, 021) \
+ CPU_THREAD_DEV (socket, 022) \
+ CPU_THREAD_DEV (socket, 023) \
+ CPU_THREAD_DEV (socket, 024) \
+ CPU_THREAD_DEV (socket, 025) \
+ CPU_THREAD_DEV (socket, 026) \
+ CPU_THREAD_DEV (socket, 027) \
+ CPU_THREAD_DEV (socket, 028) \
+ CPU_THREAD_DEV (socket, 029) \
+ CPU_THREAD_DEV (socket, 02A) \
+ CPU_THREAD_DEV (socket, 02B) \
+ CPU_THREAD_DEV (socket, 02C) \
+ CPU_THREAD_DEV (socket, 02D) \
+ CPU_THREAD_DEV (socket, 02E) \
+ CPU_THREAD_DEV (socket, 02F) \
+ CPU_THREAD_DEV (socket, 030) \
+ CPU_THREAD_DEV (socket, 031) \
+ CPU_THREAD_DEV (socket, 032) \
+ CPU_THREAD_DEV (socket, 033) \
+ CPU_THREAD_DEV (socket, 034) \
+ CPU_THREAD_DEV (socket, 035) \
+ CPU_THREAD_DEV (socket, 036) \
+ CPU_THREAD_DEV (socket, 037) \
+ CPU_THREAD_DEV (socket, 038) \
+ CPU_THREAD_DEV (socket, 039) \
+ CPU_THREAD_DEV (socket, 03A) \
+ CPU_THREAD_DEV (socket, 03B) \
+ CPU_THREAD_DEV (socket, 03C) \
+ CPU_THREAD_DEV (socket, 03D) \
+ CPU_THREAD_DEV (socket, 03E) \
+ CPU_THREAD_DEV (socket, 03F) \
+ CPU_THREAD_DEV (socket, 040) \
+ CPU_THREAD_DEV (socket, 041) \
+ CPU_THREAD_DEV (socket, 042) \
+ CPU_THREAD_DEV (socket, 043) \
+ CPU_THREAD_DEV (socket, 044) \
+ CPU_THREAD_DEV (socket, 045) \
+ CPU_THREAD_DEV (socket, 046) \
+ CPU_THREAD_DEV (socket, 047) \
+ CPU_THREAD_DEV (socket, 048) \
+ CPU_THREAD_DEV (socket, 049) \
+ CPU_THREAD_DEV (socket, 04A) \
+ CPU_THREAD_DEV (socket, 04B) \
+ CPU_THREAD_DEV (socket, 04C) \
+ CPU_THREAD_DEV (socket, 04D) \
+ CPU_THREAD_DEV (socket, 04E) \
+ CPU_THREAD_DEV (socket, 04F) \
+ CPU_THREAD_DEV (socket, 050) \
+ CPU_THREAD_DEV (socket, 051) \
+ CPU_THREAD_DEV (socket, 052) \
+ CPU_THREAD_DEV (socket, 053) \
+ CPU_THREAD_DEV (socket, 054) \
+ CPU_THREAD_DEV (socket, 055) \
+ CPU_THREAD_DEV (socket, 056) \
+ CPU_THREAD_DEV (socket, 057) \
+ CPU_THREAD_DEV (socket, 058) \
+ CPU_THREAD_DEV (socket, 059) \
+ CPU_THREAD_DEV (socket, 05A) \
+ CPU_THREAD_DEV (socket, 05B) \
+ CPU_THREAD_DEV (socket, 05C) \
+ CPU_THREAD_DEV (socket, 05D) \
+ CPU_THREAD_DEV (socket, 05E) \
+ CPU_THREAD_DEV (socket, 05F) \
+ CPU_THREAD_DEV (socket, 060) \
+ CPU_THREAD_DEV (socket, 061) \
+ CPU_THREAD_DEV (socket, 062) \
+ CPU_THREAD_DEV (socket, 063) \
+ CPU_THREAD_DEV (socket, 064) \
+ CPU_THREAD_DEV (socket, 065) \
+ CPU_THREAD_DEV (socket, 066) \
+ CPU_THREAD_DEV (socket, 067) \
+ CPU_THREAD_DEV (socket, 068) \
+ CPU_THREAD_DEV (socket, 069) \
+ CPU_THREAD_DEV (socket, 06A) \
+ CPU_THREAD_DEV (socket, 06B) \
+ CPU_THREAD_DEV (socket, 06C) \
+ CPU_THREAD_DEV (socket, 06D) \
+ CPU_THREAD_DEV (socket, 06E) \
+ CPU_THREAD_DEV (socket, 06F) \
+ CPU_THREAD_DEV (socket, 070) \
+ CPU_THREAD_DEV (socket, 071) \
+ CPU_THREAD_DEV (socket, 072) \
+ CPU_THREAD_DEV (socket, 073) \
+ CPU_THREAD_DEV (socket, 074) \
+ CPU_THREAD_DEV (socket, 075) \
+ CPU_THREAD_DEV (socket, 076) \
+ CPU_THREAD_DEV (socket, 077) \
+ CPU_THREAD_DEV (socket, 078) \
+ CPU_THREAD_DEV (socket, 079) \
+ CPU_THREAD_DEV (socket, 07A) \
+ CPU_THREAD_DEV (socket, 07B) \
+ CPU_THREAD_DEV (socket, 07C) \
+ CPU_THREAD_DEV (socket, 07D) \
+ CPU_THREAD_DEV (socket, 07E) \
+ CPU_THREAD_DEV (socket, 07F) \
+ }
+
+ Scope(\_SB) {
+
+ //----------------------------------------------------------------
+ // Method PSTA()
+ // Return package state
+ //
+ // Inputs: Arg0 = socket number for which to return the _STA code.
+ //----------------------------------------------------------------
+ Method(PSTA, 1){ // Socket Status
+ ShiftRight(PRBM, Arg0, Local6)
+ And(Local6, 0x1, Local6)
+ if(LEqual(Local6, 0x0)) {
+ Return(0x00)
+ } else {
+ Return(0x0F)
+ }
+ } // End Method PSTA
+
+ //----------------------------------------------------------------
+ // APIC ID Map
+ // Extened APIC ID buffer to support MAX 64 core
+ //----------------------------------------------------------------
+ Name (APT0, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT1, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT2, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT3, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT4, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT5, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT6, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ Name (APT7, Buffer (128) {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ })
+
+ //----------------------------------------------------------------
+ // Method TPID()
+ // Convert the socket and thread index to the actual APIC ID
+ //
+ // Inputs: Arg0 = socket index
+ // Arg1 = thread index
+ //----------------------------------------------------------------
+ Method (TPID, 2, NotSerialized) {
+ Store (0x00, Local0)
+ If (LEqual (Arg0, 0x00))
+ {
+ Store (P0ID, Local0)
+ Add (Local0, DerefOf(Index(APT0, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x01))
+ {
+ Store (P1ID, Local0)
+ Add (Local0, DerefOf(Index(APT1, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x02))
+ {
+ Store (P2ID, Local0)
+ Add (Local0, DerefOf(Index(APT2, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x03))
+ {
+ Store (P3ID, Local0)
+ Add (Local0, DerefOf(Index(APT3, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x04))
+ {
+ Store (P4ID, Local0)
+ Add (Local0, DerefOf(Index(APT4, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x05))
+ {
+ Store (P5ID, Local0)
+ Add (Local0, DerefOf(Index(APT5, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x06))
+ {
+ Store (P6ID, Local0)
+ Add (Local0, DerefOf(Index(APT6, Arg1)), Local0)
+ }
+
+ If (LEqual (Arg0, 0x07))
+ {
+ Store (P7ID, Local0)
+ Add (Local0, DerefOf(Index(APT7, Arg1)), Local0)
+ }
+
+ Return (Local0)
+ }
+
+ //----------------------------------------------------------------
+ // Method CSTA()
+ // Get current processor state
+ // Inputs: Arg0 = Socket Number where core belongs
+ // Arg1 = Thread number for which to return the _STA code
+ // (Bit0 - Core Id, BIT1- Thread Id)
+ //----------------------------------------------------------------
+ Method(CSTA, 2){ // Core Status
+ Store(0, Local0)
+ Store(0, Local2) //for Core#
+
+ //Get ApicId per thread Index from APT#
+ if (LEqual(Arg0, 0x0)) {
+ if(LEqual(P0BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT0, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P0BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x1)) {
+ if(LEqual(P1BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT1, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P1BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x2)) {
+ if(LEqual(P2BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT2, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P2BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x3)) {
+ if(LEqual(P3BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT3, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P3BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x4)) {
+ if(LEqual(P4BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT4, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P4BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x5)) {
+ if(LEqual(P5BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT5, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P5BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x6)) {
+ if(LEqual(P6BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT6, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P6BM, Local2, Local0)
+ }
+ if (LEqual(Arg0, 0x7)) {
+ if(LEqual(P7BM, 0x0)) {
+ Return(0x00)
+ }
+
+ Add (Local2, DerefOf(Index(APT7, Arg1)), Local2)
+ if (LEqual(Local2, 0xFF)) {
+ Return(0x00)
+ }
+ //Processor Bit mask is changed for core# only
+ ShiftRight(Local2, 1, Local2)
+ ShiftRight(P7BM, Local2, Local0)
+ }
+
+ And(Local0, 0x1, Local0)
+ if(LEqual(Local0, 0x0)) {
+ Return(0x00)
+ } else {
+ Return(0x01)
+ }
+ } // End Method CSTA
+
+ //----------------------------------------------------------------
+ // Method CUID()
+ // Return MADT ACPI Processor UID, AcpiProcessorId and _UID
+ // Should match with AcpiProcessorId in C code
+ //
+ // Inputs: Arg0 = Socket ID
+ // Inputs: Arg1 = Thread ID
+ // Return _UID
+ //----------------------------------------------------------------+
+ Method (CUID, 2) {
+ Store(ShiftLeft(1, CNBS), Local1)
+ Multiply(Arg0, local1, local1)
+ Add(local1, Arg1, local1)
+
+ Return (Local1)
+ }
+
+ //----------------------------------------------------------------
+ // Method LAPC()
+ // Return the _MAT APIC data structure
+ //
+ // Inputs: Arg0 = Socket ID
+ // Inputs: Arg1 = Thread ID
+ // APID = TPID(Arg0, Arg1)
+ // PUID = Socket ID << CNBS + Thread ID
+ //----------------------------------------------------------------+
+ Method(LAPC, 2,Serialized) {
+
+ Name(APIC, Buffer(SIZE_LAPIC_STRUC) {} ) // initialize a buffer with CRST size
+
+ CreateByteField (APIC, 0x00, TYPE) // Type
+ CreateByteField (APIC, 0x01, LLEN) // Length
+ CreateByteField (APIC, 0x02, PUID) // ACPI Processor ID
+ CreateByteField (APIC, 0x03, APID) // APIC ID
+ CreateDwordField(APIC, 0x04, FLAG) // Flags
+
+ Store(LAPIC_TYPE, TYPE)
+ Store(SIZE_LAPIC_STRUC, LLEN)
+
+ // Update APIC ID
+ Store (\_SB.TPID(Arg0, Arg1), APID)
+
+ // Update Flag
+ if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) {
+ Store(0x00, FLAG)
+ Store(0xFF, PUID)
+ Store(0xFF, APID)
+ } else {
+ Store(ShiftLeft(1, CNBS), Local1)
+ Multiply(Arg0, local1, local1)
+ Add(local1, Arg1, local1)
+ Store(local1, PUID)
+
+ //set Enable flag
+ Store(0x01, FLAG)
+ }
+
+ // calculate PROCID based on APICID using same algorithm in AcpiPlatformHook.c
+
+ Return(APIC)
+ }
+
+ Method(X2AP, 2,Serialized) {
+
+ Name(APIC, Buffer(SIZE_X2LAPIC_STRUC) {} ) // initialize a buffer with CRST siz
+
+ CreateByteField (APIC, 0x00, TYPE) // Type
+ CreateByteField (APIC, 0x01, LLEN) // Length
+ CreateWordField (APIC, 0x02, RSVD) // Reserved 2 bytes
+ CreateDwordField(APIC, 0x04, APID) // APIC ID
+ CreateDwordField(APIC, 0x08, FLAG) // Flags
+ CreateDwordField(APIC, 0x0C, PUID) // ACPI Processor UID
+
+ Store(X2LAPIC_TYPE, TYPE)
+ Store(SIZE_X2LAPIC_STRUC, LLEN)
+ Store(0, RSVD)
+
+ // Update APIC ID
+ Store (\_SB.TPID(Arg0, Arg1), APID)
+
+ // Update Flag
+ if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) {
+ Store(0x00, FLAG)
+ Store(0xFFFFFFFF, APID)
+ } else {
+ //ProcId = socket# * MAX_THREADS_PER_SOCKET + thread#
+ Store(ShiftLeft(1, CNBS), Local1)
+ Multiply(Arg0, local1, local1)
+ Add(local1, Arg1, local1)
+ Store(local1, PUID)
+
+ //set Enable flag
+ Store(0x01, FLAG)
+
+ }
+
+ Return(APIC)
+
+ }
+
+ CPU_SOCKET_DEV(0)
+
+#if MAX_SOCKET > 1
+ CPU_SOCKET_DEV(1)
+#endif
+
+#if MAX_SOCKET > 2
+ CPU_SOCKET_DEV(2)
+#endif
+
+#if MAX_SOCKET > 3
+ CPU_SOCKET_DEV(3)
+#endif
+
+#if MAX_SOCKET > 4
+ CPU_SOCKET_DEV(4)
+#endif
+
+#if MAX_SOCKET > 5
+ CPU_SOCKET_DEV(5)
+#endif
+
+#if MAX_SOCKET > 6
+ CPU_SOCKET_DEV(6)
+#endif
+
+#if MAX_SOCKET > 7
+ CPU_SOCKET_DEV(7)
+#endif
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl
new file mode 100644
index 0000000000..b3f96f8ddb
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl
@@ -0,0 +1,61 @@
+/** @file
+ ACPI DSDT table
+
+ @copyright
+ Copyright 2011 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// @NOTE: This should be read from hardware to reflect
+// real PCI exress base. Currently we do not have such
+// capability so hardcode is used instead.
+//
+#define PCI_EXPRESS_BASE 0x80000000
+
+Scope(\_SB.PC00) {
+
+ //
+ // PCI-specific method's GUID
+ //
+ Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
+ //
+ // PCI's _DSM - an attempt at modular _DSM implementation
+ // When writing your own _DSM function that needs to include PCI-specific methods, do this:
+ //
+ // Method(_YOUR_DSM,4){
+ // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
+ // ...continue your _DSM by checking different GUIDs...
+ // else { return(0) }
+ // }
+ //
+ Method(PCID, 4, Serialized) {
+ If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
+ If(LGreaterEqual(Arg1,3)) { // revision at least 3
+ If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
+ If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
+ If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
+ }
+ }
+ return (Buffer(1){0})
+ }
+
+ Method(PCIC,1,Serialized) {
+ If(LEqual(ECR1,1)) {
+ If(LEqual(Arg0, PCIG)) {
+ return (1)
+ }
+ }
+ return (0)
+ }
+
+ //
+ // Get the PCI express base address.
+ // Currently hardcoded.
+ //
+ Method (GPCB) {
+ Return (PCI_EXPRESS_BASE)
+ }
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
new file mode 100644
index 0000000000..386fbdac59
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
@@ -0,0 +1,19 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+DefinitionBlock ("EPRPPlatform10nm.asl","DSDT",2,"INTEL","EPRP10NM",3)
+{
+ #include "CommonPlatform10nm.asi"
+ #include "PlatformPciTree10nm_EPRP.asi"
+ #include "AMLUPD.asl"
+ #include "DSDT.asl"
+ #include "Pch.asl" //This is in another package (PchPkg)
+ #include "Platform.asl"
+ #include "PlatformGpe10nm.asi"
+ #include "IioPcieEdpcNotify10nm.asi"
+} // end of DSDT
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi
new file mode 100644
index 0000000000..235e60650c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi
@@ -0,0 +1,158 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2016 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //And (CTRL, 0x1C, CTRL)
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ }
+
+ Method(_STA){
+ // Check if Virtual FPGA is present
+ if(LEqual(P0FB, 0x1)) {
+ // Virtual FPGA present and logically online
+ Return(0x0F)
+ }
+ // Virtual FPGA logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name (RBUF, ResourceTemplate () {
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1
+ ,
+ ,
+ FBUS
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FPGM // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIXZ // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ })
+
+ Method(_CRS, 0x0, NotSerialized) {
+ ///
+ /// Patch 32b memory
+ ///
+ CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
+ CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
+ CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
+ Store(FMB0, FMN1)
+ Store(FML0, FMX1)
+ Subtract (FMX1, FMN1, FLN1)
+ Add (FLN1, 1, FLN1)
+
+ ///
+ /// Patch _BBN
+ ///
+ If(LGreater(FBL0, FBB0)) {
+ CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
+ CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
+ CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
+ Store(FBB0, BMIN)
+ Store(FBL0, BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Add (BLEN, 1, BLEN)
+ }
+ Return (RBUF)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi
new file mode 100644
index 0000000000..cecf469c9d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi
@@ -0,0 +1,158 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2016 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //And (CTRL, 0x1C, CTRL)
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ }
+
+ Method(_STA){
+ // Check if Virtual FPGA is present
+ if(LEqual(P1FB, 0x1)) {
+ // Virtual FPGA present and logically online
+ Return(0x0F)
+ }
+ // Virtual FPGA logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name (RBUF, ResourceTemplate () {
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1
+ ,
+ ,
+ FBUS
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FPGM // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIXZ // DescriptorName populated so iASL outputs offset for it in a .h file
+
+ )
+ })
+
+ Method(_CRS, 0x0, NotSerialized) {
+ ///
+ /// Patch 32b memory
+ ///
+ CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
+ CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
+ CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
+ Store(FMB1, FMN1)
+ Store(FML1, FMX1)
+ Subtract (FMX1, FMN1, FLN1)
+ Add (FLN1, 1, FLN1)
+
+ ///
+ /// Patch _BBN
+ ///
+ If(LGreater(FBL1, FBB1)) {
+ CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
+ CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
+ CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
+ Store(FBB1, BMIN)
+ Store(FBL1, BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Add (BLEN, 1, BLEN)
+ }
+ Return (RBUF)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi
new file mode 100644
index 0000000000..e4731a63c1
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi
@@ -0,0 +1,157 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2016 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //And (CTRL, 0x1C, CTRL)
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ }
+
+ Method(_STA){
+ // Check if Virtual FPGA is present
+ if(LEqual(P2FB, 0x1)) {
+ // Virtual FPGA present and logically online
+ Return(0x0F)
+ }
+ // Virtual FPGA logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name (RBUF, ResourceTemplate () {
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1
+ ,
+ ,
+ FBUS
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FPGM // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIXZ // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ })
+
+ Method(_CRS, 0x0, NotSerialized) {
+ ///
+ /// Patch 32b memory
+ ///
+ CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
+ CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
+ CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
+ Store(FMB2, FMN1)
+ Store(FML2, FMX1)
+ Subtract (FMX1, FMN1, FLN1)
+ Add (FLN1, 1, FLN1)
+
+ ///
+ /// Patch _BBN
+ ///
+ If(LGreater(FBL2, FBB2)) {
+ CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
+ CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
+ CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
+ Store(FBB2, BMIN)
+ Store(FBL2, BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Add (BLEN, 1, BLEN)
+ }
+ Return (RBUF)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi
new file mode 100644
index 0000000000..51be7989ac
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi
@@ -0,0 +1,157 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2016 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //And (CTRL, 0x1C, CTRL)
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ Store (0xEE, IO80)
+ Return(Arg3)
+ }
+ }
+
+ Method(_STA){
+ // Check if Virtual FPGA is present
+ if(LEqual(P3FB, 0x1)) {
+ // Virtual FPGA present and logically online
+ Return(0x0F)
+ }
+ // Virtual FPGA logically offline
+ Return(0x00)
+
+ } // End Method STA
+
+ Name (RBUF, ResourceTemplate () {
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0000, // Max
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1
+ ,
+ ,
+ FBUS
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX7 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FPGM // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIXZ - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIXZ // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ })
+
+ Method(_CRS, 0x0, NotSerialized) {
+ ///
+ /// Patch 32b memory
+ ///
+ CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
+ CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
+ CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
+ Store(FMB3, FMN1)
+ Store(FML3, FMX1)
+ Subtract (FMX1, FMN1, FLN1)
+ Add (FLN1, 1, FLN1)
+
+ ///
+ /// Patch _BBN
+ ///
+ If(LGreater(FBL3, FBB3)) {
+ CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
+ CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
+ CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
+ Store(FBB3, BMIN)
+ Store(FBL3, BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Add (BLEN, 1, BLEN)
+ }
+ Return (RBUF)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi
new file mode 100644
index 0000000000..d695b13df9
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi
@@ -0,0 +1,137 @@
+/** @file
+ ACPI DSDT table
+
+@copyright
+ Copyright 2011 - 2018 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // General Purpose Events. This Scope handles the Run-time and
+ // Wake-time SCIs. The specific method called will be determined by
+ // the _Lxx value, where xx equals the bit location in the General
+ // Purpose Event register(s).
+
+
+ //
+ // If the Root Port is enabled, run PCI_EXP_STS handler
+ //
+ If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP01.HPME()
+ Notify(\_SB.PC00.RP01, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP02.HPME()
+ Notify(\_SB.PC00.RP02, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP03.HPME()
+ Notify(\_SB.PC00.RP03, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP04.HPME()
+ Notify(\_SB.PC00.RP04, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP05.HPME()
+ Notify(\_SB.PC00.RP05, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP06.HPME()
+ Notify(\_SB.PC00.RP06, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP07.HPME()
+ Notify(\_SB.PC00.RP07, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP08.HPME()
+ Notify(\_SB.PC00.RP08, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP09.HPME()
+ Notify(\_SB.PC00.RP09, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP10.HPME()
+ Notify(\_SB.PC00.RP10, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP11.HPME()
+ Notify(\_SB.PC00.RP11, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP12.HPME()
+ Notify(\_SB.PC00.RP12, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP13.HPME()
+ Notify(\_SB.PC00.RP13, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP14.HPME()
+ Notify(\_SB.PC00.RP14, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP15.HPME()
+ Notify(\_SB.PC00.RP15, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP16.HPME()
+ Notify(\_SB.PC00.RP16, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP17.HPME()
+ Notify(\_SB.PC00.RP17, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP18.HPME()
+ Notify(\_SB.PC00.RP18, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP19.HPME()
+ Notify(\_SB.PC00.RP19, 0x02)
+ }
+
+ If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF))
+ {
+ \_SB.PC00.RP20.HPME()
+ Notify(\_SB.PC00.RP20, 0x02)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi
new file mode 100644
index 0000000000..7180f6d607
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi
@@ -0,0 +1,16 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+ External(\_SB.EDGH, MethodObj)
+
+ //
+ // Handle eDPC SWGPE event
+ //
+ If (CondRefOf (\_SB.EDGH))
+ {
+ \_SB.EDGH ()
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi
new file mode 100644
index 0000000000..78759e32f3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi
@@ -0,0 +1,183 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+External(\_SB.EDTM, MethodObj)
+External (\_SB.EDNT, FieldUnitObj)
+External (\_SB.EDVD, FieldUnitObj)
+
+#define PCIE_EDPC_NOTIFY(stack, port) \
+ store (\_SB.stack._SEG, Local0) \
+ store (\_SB.stack._BBN, Local1) \
+ store (\_SB.stack.port._ADR, Local2) \
+ And (Local2, 0xffff, Local3) \
+ ShiftRight (Local2, 16, Local4) \
+ If (\_SB.EDTM(Local0, Local1, Local4, Local3)) { \
+ If (\_SB.EDNT) { \
+ /* \
+ we are going to notify this device, set the valid flag to EDPC_INFO_NOTIFIED \
+ */ \
+ store (2, \_SB.EDVD) \
+ Notify(\_SB.stack.port, 0xf) /*Error Eject*/ \
+ } else { \
+ /* \
+ we are going to notify this device, set the valid flag to EDPC_INFO_NOTIFIED \
+ */ \
+ store (2, \_SB.EDVD) \
+ Notify(\_SB.stack.port, 0) /*Bus Check*/ \
+ } \
+ }
+
+Scope (\_SB) {
+ //
+ // eDPC Notify Method
+ //
+ Method (EDNM, 0) {
+ // PC01 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC01, BR1A)
+ PCIE_EDPC_NOTIFY(PC01, BR1B)
+ PCIE_EDPC_NOTIFY(PC01, BR1C)
+ PCIE_EDPC_NOTIFY(PC01, BR1D)
+
+ // PC02 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC02, BR2A)
+ PCIE_EDPC_NOTIFY(PC02, BR2B)
+ PCIE_EDPC_NOTIFY(PC02, BR2C)
+ PCIE_EDPC_NOTIFY(PC02, BR2D)
+
+ // PC03 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC03, BR3A)
+ PCIE_EDPC_NOTIFY(PC03, BR3B)
+ PCIE_EDPC_NOTIFY(PC03, BR3C)
+ PCIE_EDPC_NOTIFY(PC03, BR3D)
+
+ // PC04 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC04, BR4A)
+ PCIE_EDPC_NOTIFY(PC04, BR4B)
+ PCIE_EDPC_NOTIFY(PC04, BR4C)
+ PCIE_EDPC_NOTIFY(PC04, BR4D)
+
+ // PC05 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC05, BR5A)
+ PCIE_EDPC_NOTIFY(PC05, BR5B)
+ PCIE_EDPC_NOTIFY(PC05, BR5C)
+ PCIE_EDPC_NOTIFY(PC05, BR5D)
+
+ #if MAX_SOCKET > 1
+ // PC07 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC07, QR1A)
+ PCIE_EDPC_NOTIFY(PC07, QR1B)
+ PCIE_EDPC_NOTIFY(PC07, QR1C)
+ PCIE_EDPC_NOTIFY(PC07, QR1D)
+
+ // PC08 Port 2A PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC08, QR2A)
+ PCIE_EDPC_NOTIFY(PC08, QR2B)
+ PCIE_EDPC_NOTIFY(PC08, QR2C)
+ PCIE_EDPC_NOTIFY(PC08, QR2D)
+
+ // PC09 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC09, QR3A)
+ PCIE_EDPC_NOTIFY(PC09, QR3B)
+ PCIE_EDPC_NOTIFY(PC09, QR3C)
+ PCIE_EDPC_NOTIFY(PC09, QR3D)
+
+ // PC08 Port 2A PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC10, QR4A)
+ PCIE_EDPC_NOTIFY(PC10, QR4B)
+ PCIE_EDPC_NOTIFY(PC10, QR4C)
+ PCIE_EDPC_NOTIFY(PC10, QR4D)
+
+ // PC09 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC11, QR5A)
+ PCIE_EDPC_NOTIFY(PC11, QR5B)
+ PCIE_EDPC_NOTIFY(PC11, QR5C)
+ PCIE_EDPC_NOTIFY(PC11, QR5D)
+ #endif
+ #if MAX_SOCKET > 2
+ // PC13 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC13, RR1A)
+ PCIE_EDPC_NOTIFY(PC13, RR1B)
+ PCIE_EDPC_NOTIFY(PC13, RR1C)
+ PCIE_EDPC_NOTIFY(PC13, RR1D)
+
+ // PC14 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC14, RR2A)
+ PCIE_EDPC_NOTIFY(PC14, RR2B)
+ PCIE_EDPC_NOTIFY(PC14, RR2C)
+ PCIE_EDPC_NOTIFY(PC14, RR2D)
+
+ // PC15 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC15, RR3A)
+ PCIE_EDPC_NOTIFY(PC15, RR3B)
+ PCIE_EDPC_NOTIFY(PC15, RR3C)
+ PCIE_EDPC_NOTIFY(PC15, RR3D)
+
+ // PC16 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC16, RR4A)
+ PCIE_EDPC_NOTIFY(PC16, RR4B)
+ PCIE_EDPC_NOTIFY(PC16, RR4C)
+ PCIE_EDPC_NOTIFY(PC16, RR4D)
+
+ // PC17 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC17, RR5A)
+ PCIE_EDPC_NOTIFY(PC17, RR5B)
+ PCIE_EDPC_NOTIFY(PC17, RR5C)
+ PCIE_EDPC_NOTIFY(PC17, RR5D)
+ #endif
+ #if MAX_SOCKET > 3
+ // PC19 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC19, SR1A)
+ PCIE_EDPC_NOTIFY(PC19, SR1B)
+ PCIE_EDPC_NOTIFY(PC19, SR1C)
+ PCIE_EDPC_NOTIFY(PC19, SR1D)
+
+ // PC20 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC20, SR2A)
+ PCIE_EDPC_NOTIFY(PC20, SR2B)
+ PCIE_EDPC_NOTIFY(PC20, SR2C)
+ PCIE_EDPC_NOTIFY(PC20, SR2D)
+
+ // PC21 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC21, SR3A)
+ PCIE_EDPC_NOTIFY(PC21, SR3B)
+ PCIE_EDPC_NOTIFY(PC21, SR3C)
+ PCIE_EDPC_NOTIFY(PC21, SR3D)
+
+ // PC21 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC22, SR4A)
+ PCIE_EDPC_NOTIFY(PC22, SR4B)
+ PCIE_EDPC_NOTIFY(PC22, SR4C)
+ PCIE_EDPC_NOTIFY(PC22, SR4D)
+
+ // PC22 PCI-Ex eDPC
+ // If this is the eDPC event trigger, notify error eject or bus check
+ PCIE_EDPC_NOTIFY(PC23, SR5A)
+ PCIE_EDPC_NOTIFY(PC23, SR5B)
+ PCIE_EDPC_NOTIFY(PC23, SR5C)
+ PCIE_EDPC_NOTIFY(PC23, SR5D)
+ #endif
+ } //endof the method EDGH
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi
new file mode 100644
index 0000000000..13c76067c3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi
@@ -0,0 +1,16 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+ External(\_SB.EDOS, MethodObj)
+
+ //
+ // Handle eDPC _OST
+ //
+ If (CondRefOf (\_SB.EDOS))
+ {
+ \_SB.EDOS (Arg0, Arg1, Arg2)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl
new file mode 100644
index 0000000000..09ff73e148
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl
@@ -0,0 +1,1322 @@
+/** @file
+
+ @copyright
+ Copyright 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // Delay introduced as initial delay after entering ACPI hotplug method
+ //
+ Sleep (200)
+ Store (0x01, IO80)
+ Sleep (10)
+ Store (0,Local1)
+
+ // PC00 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) {
+ Store(\_SB.PC01.BR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC01.BR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC01.BR1A, Local0)
+ }
+
+ // PC00 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) {
+ Store(\_SB.PC01.BR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC01.BR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC01.BR1B, Local0)
+ }
+
+ // PC00 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) {
+ Store(\_SB.PC01.BR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC01.BR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC01.BR1C, Local0)
+ }
+
+ // PC00 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) {
+ Store(\_SB.PC01.BR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC01.BR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC01.BR1D, Local0)
+ }
+
+
+ // PC01 Port 2A PCI-Ex Hot Plug
+ If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) {
+ Store(\_SB.PC02.BR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC02.BR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC02.BR2A, Local0)
+ }
+
+ // PC01 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) {
+ Store(\_SB.PC02.BR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC02.BR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC02.BR2B, Local0)
+ }
+
+ // PC01 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) {
+ Store(\_SB.PC02.BR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC02.BR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC02.BR2C, Local0)
+ }
+
+ // PC01 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) {
+ Store(\_SB.PC02.BR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC02.BR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC02.BR2D, Local0)
+ }
+
+ // PC01 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) {
+ Store(\_SB.PC03.BR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC03.BR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC03.BR3A, Local0)
+ }
+
+ // PC01 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3B.PMEP,1) ) {
+ Store(\_SB.PC03.BR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC03.BR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC03.BR3B, Local0)
+ }
+
+ // PC01 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) {
+ Store(\_SB.PC03.BR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC03.BR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC03.BR3C, Local0)
+ }
+
+ // PC01 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) {
+ Store(\_SB.PC03.BR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC03.BR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC03.BR3D, Local0)
+ }
+
+ // PC02 Port 4A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC04.BR4A.PMEP,1) ) {
+ Store(\_SB.PC04.BR4A.PMEH(13), Local0)
+ } else {
+ Store (\_SB.PC04.BR4A.HPEH(13), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(13, Local1)
+ Notify(\_SB.PC04.BR4A, Local0)
+ }
+
+ // PC02 Port 4B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC04.BR4B.PMEP,1) ) {
+ Store(\_SB.PC04.BR4B.PMEH(14), Local0)
+ } else {
+ Store (\_SB.PC04.BR4B.HPEH(14), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(14, Local1)
+ Notify(\_SB.PC04.BR4B, Local0)
+ }
+
+ // PC02 Port 4C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC04.BR4C.PMEP,1) ) {
+ Store(\_SB.PC04.BR4C.PMEH(15), Local0)
+ } else {
+ Store (\_SB.PC04.BR4C.HPEH(15), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(15, Local1)
+ Notify(\_SB.PC04.BR4C, Local0)
+ }
+
+ // PC02 Port 4D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC04.BR4D.PMEP,1) ) {
+ Store(\_SB.PC04.BR4D.PMEH(16), Local0)
+ } else {
+ Store (\_SB.PC04.BR4D.HPEH(16), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(16, Local1)
+ Notify(\_SB.PC04.BR4D, Local0)
+ }
+
+ // PC02 Port 5A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC05.BR5A.PMEP,1) ) {
+ Store(\_SB.PC05.BR5A.PMEH(17), Local0)
+ } else {
+ Store (\_SB.PC05.BR5A.HPEH(17), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(17, Local1)
+ Notify(\_SB.PC05.BR5A, Local0)
+ }
+
+ // PC02 Port 5B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC05.BR5B.PMEP,1) ) {
+ Store(\_SB.PC05.BR5B.PMEH(18), Local0)
+ } else {
+ Store (\_SB.PC05.BR5B.HPEH(18), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(18, Local1)
+ Notify(\_SB.PC05.BR5B, Local0)
+ }
+
+ // PC02 Port 5C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC05.BR5C.PMEP,1) ) {
+ Store(\_SB.PC05.BR5C.PMEH(19), Local0)
+ } else {
+ Store (\_SB.PC05.BR5C.HPEH(19), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(19, Local1)
+ Notify(\_SB.PC05.BR5C, Local0)
+ }
+
+ // PC02 Port 5D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC05.BR5D.PMEP,1) ) {
+ Store(\_SB.PC05.BR5D.PMEH(20), Local0)
+ } else {
+ Store (\_SB.PC05.BR5D.HPEH(20), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(20, Local1)
+ Notify(\_SB.PC05.BR5D, Local0)
+ }
+
+#if MAX_SOCKET > 1
+
+
+ // PC06 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) {
+ Store(\_SB.PC07.QR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC07.QR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC07.QR1A, Local0)
+ }
+
+ // PC06 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) {
+ Store(\_SB.PC07.QR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC07.QR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC07.QR1B, Local0)
+ }
+
+ // PC06 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) {
+ Store(\_SB.PC07.QR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC07.QR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC07.QR1C, Local0)
+ }
+
+ // PC06 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) {
+ Store(\_SB.PC07.QR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC07.QR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC07.QR1D, Local0)
+ }
+
+ // PC04 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) {
+ Store(\_SB.PC08.QR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC08.QR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC08.QR2A, Local0)
+ }
+
+ // PC04 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) {
+ Store(\_SB.PC08.QR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC08.QR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC08.QR2B, Local0)
+ }
+
+ // PC04 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) {
+ Store(\_SB.PC08.QR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC08.QR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC08.QR2C, Local0)
+ }
+
+ // PC04 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) {
+ Store(\_SB.PC08.QR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC08.QR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC08.QR2D, Local0)
+ }
+
+ // PC04 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) {
+ Store(\_SB.PC09.QR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC09.QR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC09.QR3A, Local0)
+ }
+
+ // PC04 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) {
+ Store(\_SB.PC09.QR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC09.QR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC09.QR3B, Local0)
+ }
+
+ // PC04 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) {
+ Store(\_SB.PC09.QR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC09.QR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC09.QR3C, Local0)
+ }
+
+ // PC04 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) {
+ Store(\_SB.PC09.QR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC09.QR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC09.QR3D, Local0)
+ }
+
+ // PC10 Port 4A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC10.QR4A.PMEP,1) ) {
+ Store(\_SB.PC10.QR4A.PMEH(13), Local0)
+ } else {
+ Store (\_SB.PC10.QR4A.HPEH(13), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(13, Local1)
+ Notify(\_SB.PC10.QR4A, Local0)
+ }
+
+ // PC10 Port 4B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC10.QR4B.PMEP,1) ) {
+ Store(\_SB.PC10.QR4B.PMEH(14), Local0)
+ } else {
+ Store (\_SB.PC10.QR4B.HPEH(14), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(14, Local1)
+ Notify(\_SB.PC10.QR4B, Local0)
+ }
+
+ // PC10 Port 4C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC10.QR4C.PMEP,1) ) {
+ Store(\_SB.PC10.QR4C.PMEH(15), Local0)
+ } else {
+ Store (\_SB.PC10.QR4C.HPEH(15), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(15, Local1)
+ Notify(\_SB.PC10.QR4C, Local0)
+ }
+
+ // PC10 Port 4D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC10.QR4D.PMEP,1) ) {
+ Store(\_SB.PC10.QR4D.PMEH(16), Local0)
+ } else {
+ Store (\_SB.PC10.QR4D.HPEH(16), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(16, Local1)
+ Notify(\_SB.PC10.QR4D, Local0)
+ }
+
+ // PC10 Port 5A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC11.QR5A.PMEP,1) ) {
+ Store(\_SB.PC11.QR5A.PMEH(17), Local0)
+ } else {
+ Store (\_SB.PC11.QR5A.HPEH(17), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(17, Local1)
+ Notify(\_SB.PC11.QR5A, Local0)
+ }
+
+ // PC10 Port 5B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC11.QR5B.PMEP,1) ) {
+ Store(\_SB.PC11.QR5B.PMEH(18), Local0)
+ } else {
+ Store (\_SB.PC11.QR5B.HPEH(18), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(18, Local1)
+ Notify(\_SB.PC11.QR5B, Local0)
+ }
+
+ // PC10 Port 5C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC11.QR5C.PMEP,1) ) {
+ Store(\_SB.PC11.QR5C.PMEH(19), Local0)
+ } else {
+ Store (\_SB.PC11.QR5C.HPEH(19), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(19, Local1)
+ Notify(\_SB.PC11.QR5C, Local0)
+ }
+
+ // PC10 Port 5D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC11.QR5D.PMEP,1) ) {
+ Store(\_SB.PC11.QR5D.PMEH(20), Local0)
+ } else {
+ Store (\_SB.PC11.QR5D.HPEH(20), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(20, Local1)
+ Notify(\_SB.PC11.QR5D, Local0)
+ }
+#endif
+#if MAX_SOCKET > 2
+
+ // PC06 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) {
+ Store(\_SB.PC13.RR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC13.RR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC13.RR1A, Local0)
+ }
+
+ // PC06 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) {
+ Store(\_SB.PC13.RR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC13.RR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC13.RR1B, Local0)
+ }
+
+ // PC06 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) {
+ Store(\_SB.PC13.RR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC13.RR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC13.RR1C, Local0)
+ }
+
+ // PC06 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) {
+ Store(\_SB.PC13.RR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC13.RR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC13.RR1D, Local0)
+ }
+
+ // PC07 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) {
+ Store(\_SB.PC14.RR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC14.RR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC14.RR2A, Local0)
+ }
+
+ // PC07 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) {
+ Store(\_SB.PC14.RR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC14.RR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC14.RR2B, Local0)
+ }
+
+ // PC07 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) {
+ Store(\_SB.PC14.RR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC14.RR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC14.RR2C, Local0)
+ }
+
+ // PC07 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) {
+ Store(\_SB.PC14.RR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC14.RR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC14.RR2D, Local0)
+ }
+
+ // PC07 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) {
+ Store(\_SB.PC15.RR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC15.RR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC15.RR3A, Local0)
+ }
+
+ // PC07 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) {
+ Store(\_SB.PC15.RR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC15.RR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC15.RR3B, Local0)
+ }
+
+ // PC07 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) {
+ Store(\_SB.PC15.RR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC15.RR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC15.RR3C, Local0)
+ }
+
+ // PC07 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) {
+ Store(\_SB.PC15.RR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC15.RR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC15.RR3D, Local0)
+ }
+
+ // PC08 Port 4A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC16.RR4A.PMEP,1) ) {
+ Store(\_SB.PC16.RR4A.PMEH(13), Local0)
+ } else {
+ Store (\_SB.PC16.RR4A.HPEH(13), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(13, Local1)
+ Notify(\_SB.PC16.RR4A, Local0)
+ }
+
+ // PC08 Port 4B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC16.RR4B.PMEP,1) ) {
+ Store(\_SB.PC16.RR4B.PMEH(14), Local0)
+ } else {
+ Store (\_SB.PC16.RR4B.HPEH(14), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(14, Local1)
+ Notify(\_SB.PC16.RR4B, Local0)
+ }
+
+ // PC08 Port 4C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC16.RR4C.PMEP,1) ) {
+ Store(\_SB.PC16.RR4C.PMEH(15), Local0)
+ } else {
+ Store (\_SB.PC16.RR4C.HPEH(15), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(15, Local1)
+ Notify(\_SB.PC16.RR4C, Local0)
+ }
+
+ // PC08 Port 4D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC16.RR4D.PMEP,1) ) {
+ Store(\_SB.PC16.RR4D.PMEH(16), Local0)
+ } else {
+ Store (\_SB.PC16.RR4D.HPEH(16), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(16, Local1)
+ Notify(\_SB.PC16.RR4D, Local0)
+ }
+
+ // PC08 Port 5A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC17.RR5A.PMEP,1) ) {
+ Store(\_SB.PC17.RR5A.PMEH(17), Local0)
+ } else {
+ Store (\_SB.PC17.RR5A.HPEH(17), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(17, Local1)
+ Notify(\_SB.PC17.RR5A, Local0)
+ }
+
+ // PC08 Port 5B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC17.RR5B.PMEP,1) ) {
+ Store(\_SB.PC17.RR5B.PMEH(18), Local0)
+ } else {
+ Store (\_SB.PC17.RR5B.HPEH(18), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(18, Local1)
+ Notify(\_SB.PC17.RR5B, Local0)
+ }
+
+ // PC08 Port 5C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC17.RR5C.PMEP,1) ) {
+ Store(\_SB.PC17.RR5C.PMEH(19), Local0)
+ } else {
+ Store (\_SB.PC17.RR5C.HPEH(19), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(19, Local1)
+ Notify(\_SB.PC17.RR5C, Local0)
+ }
+
+ // PC08 Port 5D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC17.RR5D.PMEP,1) ) {
+ Store(\_SB.PC17.RR5D.PMEH(20), Local0)
+ } else {
+ Store (\_SB.PC17.RR5D.HPEH(20), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(20, Local1)
+ Notify(\_SB.PC17.RR5D, Local0)
+ }
+#endif
+#if MAX_SOCKET > 3
+
+
+ // PC09 Port 1A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) {
+ Store(\_SB.PC19.SR1A.PMEH(1), Local0)
+ } else {
+ Store (\_SB.PC19.SR1A.HPEH(1), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(1, Local1)
+ Notify(\_SB.PC19.SR1A, Local0)
+ }
+
+ // PC09 Port 1B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) {
+ Store(\_SB.PC19.SR1B.PMEH(2), Local0)
+ } else {
+ Store (\_SB.PC19.SR1B.HPEH(2), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(2, Local1)
+ Notify(\_SB.PC19.SR1B, Local0)
+ }
+
+ // PC09 Port 1C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) {
+ Store(\_SB.PC19.SR1C.PMEH(3), Local0)
+ } else {
+ Store (\_SB.PC19.SR1C.HPEH(3), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(3, Local1)
+ Notify(\_SB.PC19.SR1C, Local0)
+ }
+
+ // PC09 Port 1D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) {
+ Store(\_SB.PC19.SR1D.PMEH(4), Local0)
+ } else {
+ Store (\_SB.PC19.SR1D.HPEH(4), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(4, Local1)
+ Notify(\_SB.PC19.SR1D, Local0)
+ }
+
+ // PC10 Port 2A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) {
+ Store(\_SB.PC20.SR2A.PMEH(5), Local0)
+ } else {
+ Store (\_SB.PC20.SR2A.HPEH(5), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(5, Local1)
+ Notify(\_SB.PC20.SR2A, Local0)
+ }
+
+ // PC10 Port 2B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) {
+ Store(\_SB.PC20.SR2B.PMEH(6), Local0)
+ } else {
+ Store (\_SB.PC20.SR2B.HPEH(6), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(6, Local1)
+ Notify(\_SB.PC20.SR2B, Local0)
+ }
+
+ // PC10 Port 2C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) {
+ Store(\_SB.PC20.SR2C.PMEH(7), Local0)
+ } else {
+ Store (\_SB.PC20.SR2C.HPEH(7), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(7, Local1)
+ Notify(\_SB.PC20.SR2C, Local0)
+ }
+
+ // PC10 Port 2D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) {
+ Store(\_SB.PC20.SR2D.PMEH(8), Local0)
+ } else {
+ Store (\_SB.PC20.SR2D.HPEH(8), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(8, Local1)
+ Notify(\_SB.PC20.SR2D, Local0)
+ }
+
+ // PC10 Port 3A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) {
+ Store(\_SB.PC21.SR3A.PMEH(9), Local0)
+ } else {
+ Store (\_SB.PC21.SR3A.HPEH(9), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(9, Local1)
+ Notify(\_SB.PC21.SR3A, Local0)
+ }
+
+ // PC10 Port 3B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) {
+ Store(\_SB.PC21.SR3B.PMEH(10), Local0)
+ } else {
+ Store (\_SB.PC21.SR3B.HPEH(10), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(10, Local1)
+ Notify(\_SB.PC21.SR3B, Local0)
+ }
+
+ // PC10 Port 3C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) {
+ Store(\_SB.PC21.SR3C.PMEH(11), Local0)
+ } else {
+ Store (\_SB.PC21.SR3C.HPEH(11), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(11, Local1)
+ Notify(\_SB.PC21.SR3C, Local0)
+ }
+
+ // PC10 Port 3D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) {
+ Store(\_SB.PC21.SR3D.PMEH(12), Local0)
+ } else {
+ Store (\_SB.PC21.SR3D.HPEH(12), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(12, Local1)
+ Notify(\_SB.PC21.SR3D, Local0)
+ }
+
+ // PC11 Port 4A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC22.SR4A.PMEP,1) ) {
+ Store(\_SB.PC22.SR4A.PMEH(13), Local0)
+ } else {
+ Store (\_SB.PC22.SR4A.HPEH(13), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(13, Local1)
+ Notify(\_SB.PC22.SR4A, Local0)
+ }
+
+ // PC11 Port 4B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC22.SR4B.PMEP,1) ) {
+ Store(\_SB.PC22.SR4B.PMEH(14), Local0)
+ } else {
+ Store (\_SB.PC22.SR4B.HPEH(14), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(14, Local1)
+ Notify(\_SB.PC22.SR4B, Local0)
+ }
+
+ // PC11 Port 4C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC22.SR4C.PMEP,1) ) {
+ Store(\_SB.PC22.SR4C.PMEH(15), Local0)
+ } else {
+ Store (\_SB.PC22.SR4C.HPEH(15), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(15, Local1)
+ Notify(\_SB.PC22.SR4C, Local0)
+ }
+
+ // PC11 Port 4D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC22.SR4D.PMEP,1) ) {
+ Store(\_SB.PC22.SR4D.PMEH(16), Local0)
+ } else {
+ Store (\_SB.PC22.SR4D.HPEH(16), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(16, Local1)
+ Notify(\_SB.PC22.SR4D, Local0)
+ }
+
+ // PC11 Port 5A PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC23.SR5A.PMEP,1) ) {
+ Store(\_SB.PC23.SR5A.PMEH(17), Local0)
+ } else {
+ Store (\_SB.PC23.SR5A.HPEH(17), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(17, Local1)
+ Notify(\_SB.PC23.SR5A, Local0)
+ }
+
+ // PC11 Port 5B PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC23.SR5B.PMEP,1) ) {
+ Store(\_SB.PC23.SR5B.PMEH(18), Local0)
+ } else {
+ Store (\_SB.PC23.SR5B.HPEH(18), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(18, Local1)
+ Notify(\_SB.PC23.SR5B, Local0)
+ }
+
+ // PC11 Port 5C PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC23.SR5C.PMEP,1) ) {
+ Store(\_SB.PC23.SR5C.PMEH(19), Local0)
+ } else {
+ Store (\_SB.PC23.SR5C.HPEH(19), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(19, Local1)
+ Notify(\_SB.PC23.SR5C, Local0)
+ }
+
+ // PC11 Port 5D PCI-Ex Hot Plug
+ // If PM_PME event clear INTs and AttnBtnPressed
+ If( LEqual(\_SB.PC23.SR5D.PMEP,1) ) {
+ Store(\_SB.PC23.SR5D.PMEH(20), Local0)
+ } else {
+ Store (\_SB.PC23.SR5D.HPEH(20), Local0)
+ }
+ If(Lnot(LEqual(Local0,0xFF))) {
+ Store(20, Local1)
+ Notify(\_SB.PC23.SR5D, Local0)
+ }
+#endif
+
+ //If a hotplug event was serviced check if this was generated by PM_PME
+ If (Lnot (LEqual(Local0, 0))) {
+ //Clear the status bit 16 of PMEStatus
+ //Clear the PME Pending bit 17 of PMEStatus
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC01.BR1A.PMES)
+ Store(1, \_SB.PC01.BR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC01.BR1B.PMES)
+ Store(1, \_SB.PC01.BR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC01.BR1C.PMES)
+ Store(1, \_SB.PC01.BR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC01.BR1D.PMES)
+ Store(1, \_SB.PC01.BR1D.PMEP)
+ }
+
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC02.BR2A.PMES)
+ Store(1, \_SB.PC02.BR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC02.BR2B.PMES)
+ Store(1, \_SB.PC02.BR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC02.BR2C.PMES)
+ Store(1, \_SB.PC02.BR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC02.BR2D.PMES)
+ Store(1, \_SB.PC02.BR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC03.BR3A.PMES)
+ Store(1, \_SB.PC03.BR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC03.BR3B.PMES)
+ Store(1, \_SB.PC03.BR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC03.BR3C.PMES)
+ Store(1, \_SB.PC03.BR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC03.BR3D.PMES)
+ Store(1, \_SB.PC03.BR3D.PMEP)
+ }
+ If( LEqual(Local1, 13)) {
+ Store(1, \_SB.PC04.BR4A.PMES)
+ Store(1, \_SB.PC04.BR4A.PMEP)
+ }
+ If( LEqual(Local1, 14)) {
+ Store(1, \_SB.PC04.BR4B.PMES)
+ Store(1, \_SB.PC04.BR4B.PMEP)
+ }
+ If( LEqual(Local1, 15)) {
+ Store(1, \_SB.PC04.BR4C.PMES)
+ Store(1, \_SB.PC04.BR4C.PMEP)
+ }
+ If( LEqual(Local1, 16)) {
+ Store(1, \_SB.PC04.BR4D.PMES)
+ Store(1, \_SB.PC04.BR4D.PMEP)
+ }
+ If( LEqual(Local1, 17)) {
+ Store(1, \_SB.PC05.BR5A.PMES)
+ Store(1, \_SB.PC05.BR5A.PMEP)
+ }
+ If( LEqual(Local1, 18)) {
+ Store(1, \_SB.PC05.BR5B.PMES)
+ Store(1, \_SB.PC05.BR5B.PMEP)
+ }
+ If( LEqual(Local1, 19)) {
+ Store(1, \_SB.PC05.BR5C.PMES)
+ Store(1, \_SB.PC05.BR5C.PMEP)
+ }
+ If( LEqual(Local1, 20)) {
+ Store(1, \_SB.PC05.BR5D.PMES)
+ Store(1, \_SB.PC05.BR5D.PMEP)
+ }
+
+#if MAX_SOCKET > 1
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC07.QR1A.PMES)
+ Store(1, \_SB.PC07.QR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC07.QR1B.PMES)
+ Store(1, \_SB.PC07.QR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC07.QR1C.PMES)
+ Store(1, \_SB.PC07.QR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC07.QR1D.PMES)
+ Store(1, \_SB.PC07.QR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC08.QR2A.PMES)
+ Store(1, \_SB.PC08.QR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC08.QR2B.PMES)
+ Store(1, \_SB.PC08.QR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC08.QR2C.PMES)
+ Store(1, \_SB.PC08.QR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC08.QR2D.PMES)
+ Store(1, \_SB.PC08.QR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC09.QR3A.PMES)
+ Store(1, \_SB.PC09.QR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC09.QR3B.PMES)
+ Store(1, \_SB.PC09.QR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC09.QR3C.PMES)
+ Store(1, \_SB.PC09.QR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC09.QR3D.PMES)
+ Store(1, \_SB.PC09.QR3D.PMEP)
+ }
+ If( LEqual(Local1, 13)) {
+ Store(1, \_SB.PC10.QR4A.PMES)
+ Store(1, \_SB.PC10.QR4A.PMEP)
+ }
+ If( LEqual(Local1, 14)) {
+ Store(1, \_SB.PC10.QR4B.PMES)
+ Store(1, \_SB.PC10.QR4B.PMEP)
+ }
+ If( LEqual(Local1, 15)) {
+ Store(1, \_SB.PC10.QR4C.PMES)
+ Store(1, \_SB.PC10.QR4C.PMEP)
+ }
+ If( LEqual(Local1, 16)) {
+ Store(1, \_SB.PC10.QR4D.PMES)
+ Store(1, \_SB.PC10.QR4D.PMEP)
+ }
+ If( LEqual(Local1, 17)) {
+ Store(1, \_SB.PC11.QR5A.PMES)
+ Store(1, \_SB.PC11.QR5A.PMEP)
+ }
+ If( LEqual(Local1, 18)) {
+ Store(1, \_SB.PC11.QR5B.PMES)
+ Store(1, \_SB.PC11.QR5B.PMEP)
+ }
+ If( LEqual(Local1, 19)) {
+ Store(1, \_SB.PC11.QR5C.PMES)
+ Store(1, \_SB.PC11.QR5C.PMEP)
+ }
+ If( LEqual(Local1, 20)) {
+ Store(1, \_SB.PC11.QR5D.PMES)
+ Store(1, \_SB.PC11.QR5D.PMEP)
+ }
+#endif
+#if MAX_SOCKET > 2
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC13.RR1A.PMES)
+ Store(1, \_SB.PC13.RR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC13.RR1B.PMES)
+ Store(1, \_SB.PC13.RR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC13.RR1C.PMES)
+ Store(1, \_SB.PC13.RR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC13.RR1D.PMES)
+ Store(1, \_SB.PC13.RR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC14.RR2A.PMES)
+ Store(1, \_SB.PC14.RR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC14.RR2B.PMES)
+ Store(1, \_SB.PC14.RR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC14.RR2C.PMES)
+ Store(1, \_SB.PC14.RR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC14.RR2D.PMES)
+ Store(1, \_SB.PC14.RR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC15.RR3A.PMES)
+ Store(1, \_SB.PC15.RR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC15.RR3B.PMES)
+ Store(1, \_SB.PC15.RR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC15.RR3C.PMES)
+ Store(1, \_SB.PC15.RR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC15.RR3D.PMES)
+ Store(1, \_SB.PC15.RR3D.PMEP)
+ }
+ If( LEqual(Local1, 13)) {
+ Store(1, \_SB.PC16.RR4A.PMES)
+ Store(1, \_SB.PC16.RR4A.PMEP)
+ }
+ If( LEqual(Local1, 14)) {
+ Store(1, \_SB.PC16.RR4B.PMES)
+ Store(1, \_SB.PC16.RR4B.PMEP)
+ }
+ If( LEqual(Local1, 15)) {
+ Store(1, \_SB.PC16.RR4C.PMES)
+ Store(1, \_SB.PC16.RR4C.PMEP)
+ }
+ If( LEqual(Local1, 16)) {
+ Store(1, \_SB.PC16.RR4D.PMES)
+ Store(1, \_SB.PC16.RR4D.PMEP)
+ }
+ If( LEqual(Local1, 17)) {
+ Store(1, \_SB.PC17.RR5A.PMES)
+ Store(1, \_SB.PC17.RR5A.PMEP)
+ }
+ If( LEqual(Local1, 18)) {
+ Store(1, \_SB.PC17.RR5B.PMES)
+ Store(1, \_SB.PC17.RR5B.PMEP)
+ }
+ If( LEqual(Local1, 19)) {
+ Store(1, \_SB.PC17.RR5C.PMES)
+ Store(1, \_SB.PC17.RR5C.PMEP)
+ }
+ If( LEqual(Local1, 20)) {
+ Store(1, \_SB.PC17.RR5D.PMES)
+ Store(1, \_SB.PC17.RR5D.PMEP)
+ }
+#endif
+#if MAX_SOCKET > 3
+
+ If( LEqual(Local1, 1)) {
+ Store(1, \_SB.PC19.SR1A.PMES)
+ Store(1, \_SB.PC19.SR1A.PMEP)
+ }
+ If( LEqual(Local1, 2)) {
+ Store(1, \_SB.PC19.SR1B.PMES)
+ Store(1, \_SB.PC19.SR1B.PMEP)
+ }
+ If( LEqual(Local1, 3)) {
+ Store(1, \_SB.PC19.SR1C.PMES)
+ Store(1, \_SB.PC19.SR1C.PMEP)
+ }
+ If( LEqual(Local1, 4)) {
+ Store(1, \_SB.PC19.SR1D.PMES)
+ Store(1, \_SB.PC19.SR1D.PMEP)
+ }
+ If( LEqual(Local1, 5)) {
+ Store(1, \_SB.PC20.SR2A.PMES)
+ Store(1, \_SB.PC20.SR2A.PMEP)
+ }
+ If( LEqual(Local1, 6)) {
+ Store(1, \_SB.PC20.SR2B.PMES)
+ Store(1, \_SB.PC20.SR2B.PMEP)
+ }
+ If( LEqual(Local1, 7)) {
+ Store(1, \_SB.PC20.SR2C.PMES)
+ Store(1, \_SB.PC20.SR2C.PMEP)
+ }
+ If( LEqual(Local1, 8)) {
+ Store(1, \_SB.PC20.SR2D.PMES)
+ Store(1, \_SB.PC20.SR2D.PMEP)
+ }
+ If( LEqual(Local1, 9)) {
+ Store(1, \_SB.PC21.SR3A.PMES)
+ Store(1, \_SB.PC21.SR3A.PMEP)
+ }
+ If( LEqual(Local1, 10)) {
+ Store(1, \_SB.PC21.SR3B.PMES)
+ Store(1, \_SB.PC21.SR3B.PMEP)
+ }
+ If( LEqual(Local1, 11)) {
+ Store(1, \_SB.PC21.SR3C.PMES)
+ Store(1, \_SB.PC21.SR3C.PMEP)
+ }
+ If( LEqual(Local1, 12)) {
+ Store(1, \_SB.PC21.SR3D.PMES)
+ Store(1, \_SB.PC21.SR3D.PMEP)
+ }
+ If( LEqual(Local1, 13)) {
+ Store(1, \_SB.PC22.SR4A.PMES)
+ Store(1, \_SB.PC22.SR4A.PMEP)
+ }
+ If( LEqual(Local1, 14)) {
+ Store(1, \_SB.PC22.SR4B.PMES)
+ Store(1, \_SB.PC22.SR4B.PMEP)
+ }
+ If( LEqual(Local1, 15)) {
+ Store(1, \_SB.PC22.SR4C.PMES)
+ Store(1, \_SB.PC22.SR4C.PMEP)
+ }
+ If( LEqual(Local1, 16)) {
+ Store(1, \_SB.PC22.SR4D.PMES)
+ Store(1, \_SB.PC22.SR4D.PMEP)
+ }
+ If( LEqual(Local1, 17)) {
+ Store(1, \_SB.PC23.SR5A.PMES)
+ Store(1, \_SB.PC23.SR5A.PMEP)
+ }
+ If( LEqual(Local1, 18)) {
+ Store(1, \_SB.PC23.SR5B.PMES)
+ Store(1, \_SB.PC23.SR5B.PMEP)
+ }
+ If( LEqual(Local1, 19)) {
+ Store(1, \_SB.PC23.SR5C.PMES)
+ Store(1, \_SB.PC23.SR5C.PMEP)
+ }
+ If( LEqual(Local1, 20)) {
+ Store(1, \_SB.PC23.SR5D.PMES)
+ Store(1, \_SB.PC23.SR5D.PMEP)
+ }
+#endif
+ Store(0x01,PEES) //Clear bit 9 of Status
+ Store(0x00,PMEE) //Clear bit 9 of GPE0_EN
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi
new file mode 100644
index 0000000000..3126e29de7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi
@@ -0,0 +1,328 @@
+/** @file
+
+ @copyright
+ Copyright 2008 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ External (DBGM, FieldUnitObj)
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // _BBN is ACPI method called by OS to read PCI base bus number for IIO stack.
+ //
+ Method(_BBN, 0, NotSerialized)
+ {
+ Return(CONCATENATE3(BB, SOCKET, STACK))
+ }
+
+ //
+ // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA Node) where IIO stack belongs to.
+ // Without SNC (Sub-NUMA Cluster) proximity domain is socket. If two SNC domains are enabled report
+ // PCI stacks 0..2 in the first SNC domain of a socket, and upper stacks in the second SNC domain in this socket.
+ // If four SNC domains are enabled report stacks 0,1 in first domain; stack 2 in second; 3,4 in third;
+ // and upper stacks in the fourth SNC domain in this socket.
+ //
+ Method(_PXM, 0, NotSerialized)
+ {
+ Store(SOCKET, Local0)
+ Switch (ToInteger(CLOD)) { // CLOD contains the number of SNC domains per socekt
+ Case (2) {
+ Multiply(Local0, CLOD, Local0)
+#if STACK > 2
+ Add(Local0, 1, Local0)
+#endif
+ }
+ Case (4) {
+ Multiply(Local0, CLOD, Local0)
+#if STACK > 3
+ Add(Local0, 3, Local0)
+#elif STACK > 2
+ Add(Local0, 2, Local0)
+#elif STACK > 0
+ Add(Local0, 1, Local0)
+#endif
+ }
+ }
+ Return(Local0)
+ }
+
+ //
+ // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
+ //
+ Method(_SEG, 0, NotSerialized)
+ {
+ Return(CONCATENATE2(SG0, SOCKET))
+ }
+
+ //
+ // _STA is ACPI method called by OS to read status of ACPI device, IIO stack in this case.
+ //
+ Method(_STA, 0, NotSerialized)
+ { //
+ // Check in processor present bitmap (PRBM) if processor is present, then
+ // in stack present bitmap of given processor (SPBx) if stack is present.
+ //
+ ShiftLeft(1, SOCKET, Local0)
+ If (And(PRBM, Local0)) {
+
+ ShiftLeft(1, CONCATENATE2(0x,STACK), Local1)
+ if (And(CONCATENATE2(SPB, SOCKET), Local1)) {
+ Return(0x0F)
+ }
+ }
+ Return(0x00)
+ }
+
+ Method(_OSC, 4)
+ {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x10), 0x10))) { // Conditions not met?
+ And(CTRL, Not(1), CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system), Mask bit 1
+ //
+ And(CTRL, Not(2), CTRL)
+
+
+ //
+ // Select Native PCIe AER/eDPC handling from OS or Firmware First model
+ //
+ If (CondRefOf (\_SB.OSNC))
+ {
+ //in case OS has AER capability.
+ If (LEqual ( And(CTRL, 8), 8)) {
+
+ //in case OS support multiple segment.
+ If (And (SUPP, 8)) {
+ If (CondRefof (^_SEG))
+ {
+ Store (^_SEG, Local0)
+ } Else {
+ Store (0, Local0)
+ }
+ } Else {
+ Store (0, Local0)
+ }
+
+ Store (^_BBN, Local1)
+
+ // if BIOS allows OS take. Do nothing.
+ If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) {
+
+ } Else {
+ And (CTRL, Not(0x88), CTRL)
+ }
+ } Else {
+ And (CTRL, Not(0x88), CTRL)
+ }
+ } Else {
+ //
+ //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, eDPC is bit7
+ //
+ And (CTRL, Not(0x88), CTRL)
+ }
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ \_SB.OSCM (_UID)
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ if(LEqual(DBGM, 0x01)){
+ Store (0xEE, IO80)
+ }
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Name(RBRS, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //: Off board video card not detected in device manager when it is connected to CPU
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //Off board video card not detected in device manager when it is connected to CPU
+ //Descriptor for IO space of the video card.
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0000, // Range Length
+ ,
+ ,
+ FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of PRXX Buffer
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBRS)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi
new file mode 100644
index 0000000000..1dc42a9ca8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi
@@ -0,0 +1,270 @@
+/** @file
+
+ @copyright
+ Copyright 2008 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "MaxSocket.h"
+
+ Method(OSCM, 1) {
+
+ if (LEqual(Arg0, 1)) { // PC01
+ \_SB.PC01.BR1A.OSHP ()
+ \_SB.PC01.BR1B.OSHP ()
+ \_SB.PC01.BR1C.OSHP ()
+ \_SB.PC01.BR1D.OSHP ()
+ }
+ if (LEqual(Arg0, 2)) { // PC01
+ \_SB.PC02.BR2A.OSHP ()
+ \_SB.PC02.BR2B.OSHP ()
+ \_SB.PC02.BR2C.OSHP ()
+ \_SB.PC02.BR2D.OSHP ()
+ }
+ if (LEqual(Arg0, 3)) { // PC02
+ \_SB.PC03.BR3A.OSHP ()
+ \_SB.PC03.BR3B.OSHP ()
+ \_SB.PC03.BR3C.OSHP ()
+ \_SB.PC03.BR3D.OSHP ()
+ }
+ if (LEqual(Arg0, 4)) { // PC02
+ \_SB.PC04.BR4A.OSHP ()
+ \_SB.PC04.BR4B.OSHP ()
+ \_SB.PC04.BR4C.OSHP ()
+ \_SB.PC04.BR4D.OSHP ()
+ }
+ if (LEqual(Arg0, 5)) { // PC01
+ \_SB.PC05.BR5A.OSHP ()
+ \_SB.PC05.BR5B.OSHP ()
+ \_SB.PC05.BR5C.OSHP ()
+ \_SB.PC05.BR5D.OSHP ()
+ }
+
+#if MAX_SOCKET > 1
+ if (LEqual(Arg0, 7)) { // PC07
+ \_SB.PC07.QR1A.OSHP ()
+ \_SB.PC07.QR1B.OSHP ()
+ \_SB.PC07.QR1C.OSHP ()
+ \_SB.PC07.QR1D.OSHP ()
+ }
+ if (LEqual(Arg0, 8)) { // PC08
+ \_SB.PC08.QR2A.OSHP ()
+ \_SB.PC08.QR2B.OSHP ()
+ \_SB.PC08.QR2C.OSHP ()
+ \_SB.PC08.QR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 9)) { // PC09
+ \_SB.PC09.QR3A.OSHP ()
+ \_SB.PC09.QR3B.OSHP ()
+ \_SB.PC09.QR3C.OSHP ()
+ \_SB.PC09.QR3D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 10)) { // PC10
+
+ \_SB.PC10.QR4A.OSHP ()
+ \_SB.PC10.QR4B.OSHP ()
+ \_SB.PC10.QR4C.OSHP ()
+ \_SB.PC10.QR4D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 11)) { // PC11
+ \_SB.PC11.QR5A.OSHP ()
+ \_SB.PC11.QR5B.OSHP ()
+ \_SB.PC11.QR5C.OSHP ()
+ \_SB.PC11.QR5D.OSHP ()
+ }
+
+#endif
+
+#if MAX_SOCKET > 2
+ if (LEqual(Arg0, 13)) { // PC13
+ \_SB.PC13.RR1A.OSHP ()
+ \_SB.PC13.RR1B.OSHP ()
+ \_SB.PC13.RR1C.OSHP ()
+ \_SB.PC13.RR1D.OSHP ()
+ }
+ if (LEqual(Arg0, 14)) { // PC14
+ \_SB.PC14.RR2A.OSHP ()
+ \_SB.PC14.RR2B.OSHP ()
+ \_SB.PC14.RR2C.OSHP ()
+ \_SB.PC14.RR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 15)) { // PC15
+ \_SB.PC15.RR3A.OSHP ()
+ \_SB.PC15.RR3B.OSHP ()
+ \_SB.PC15.RR3C.OSHP ()
+ \_SB.PC15.RR3D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 16)) { // PC16
+
+ \_SB.PC16.RR4A.OSHP ()
+ \_SB.PC16.RR4B.OSHP ()
+ \_SB.PC16.RR4C.OSHP ()
+ \_SB.PC16.RR4D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 17)) { // PC17
+ \_SB.PC17.RR5A.OSHP ()
+ \_SB.PC17.RR5B.OSHP ()
+ \_SB.PC17.RR5C.OSHP ()
+ \_SB.PC17.RR5D.OSHP ()
+ }
+
+#endif
+
+
+#if MAX_SOCKET > 3
+ if (LEqual(Arg0, 19)) { // PC19
+ \_SB.PC19.SR1A.OSHP ()
+ \_SB.PC19.SR1B.OSHP ()
+ \_SB.PC19.SR1C.OSHP ()
+ \_SB.PC19.SR1D.OSHP ()
+ }
+ if (LEqual(Arg0, 20)) { // PC20
+ \_SB.PC20.SR2A.OSHP ()
+ \_SB.PC20.SR2B.OSHP ()
+ \_SB.PC20.SR2C.OSHP ()
+ \_SB.PC20.SR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 21)) { // PC21
+ \_SB.PC21.SR3A.OSHP ()
+ \_SB.PC21.SR3B.OSHP ()
+ \_SB.PC21.SR3C.OSHP ()
+ \_SB.PC21.SR3D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 22)) { // PC22
+
+ \_SB.PC22.SR4A.OSHP ()
+ \_SB.PC22.SR4B.OSHP ()
+ \_SB.PC22.SR4C.OSHP ()
+ \_SB.PC22.SR4D.OSHP ()
+
+ }
+ if (LEqual(Arg0, 23)) { // PC23
+ \_SB.PC23.SR5A.OSHP ()
+ \_SB.PC23.SR5B.OSHP ()
+ \_SB.PC23.SR5C.OSHP ()
+ \_SB.PC23.SR5D.OSHP ()
+ }
+
+#endif
+#if MAX_SOCKET > 4
+ if (LEqual(Arg0,25)) { // PC12
+ \_SB.PC25.CR1A.OSHP ()
+ \_SB.PC25.CR1B.OSHP ()
+ \_SB.PC25.CR1C.OSHP ()
+ \_SB.PC25.CR1D.OSHP ()
+ }
+ if (LEqual(Arg0,26)) { // PC13
+ \_SB.PC26.CR2A.OSHP ()
+ \_SB.PC26.CR2B.OSHP ()
+ \_SB.PC26.CR2C.OSHP ()
+ \_SB.PC26.CR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0,27)) { // PC12
+ \_SB.PC27.CR3A.OSHP ()
+ \_SB.PC27.CR3B.OSHP ()
+ \_SB.PC27.CR3C.OSHP ()
+ \_SB.PC27.CR3D.OSHP ()
+ }
+ if (LEqual(Arg0,28)) { // PC13
+ \_SB.PC28.CR4A.OSHP ()
+ \_SB.PC28.CR4B.OSHP ()
+ \_SB.PC28.CR4C.OSHP ()
+ \_SB.PC28.CR4D.OSHP ()
+ }
+ if (LEqual(Arg0,29)) { // PC14
+ \_SB.PC29.CR5A.OSHP ()
+ \_SB.PC29.CR5B.OSHP ()
+ \_SB.PC29.CR5C.OSHP ()
+ \_SB.PC29.CR5D.OSHP ()
+ }
+#endif
+#if MAX_SOCKET > 5
+ if (LEqual(Arg0,31)) { // PC15
+ \_SB.PC31.TR1A.OSHP ()
+ \_SB.PC31.TR1B.OSHP ()
+ \_SB.PC31.TR1C.OSHP ()
+ \_SB.PC31.TR1D.OSHP ()
+ }
+ if (LEqual(Arg0,32)) { // PC16
+ \_SB.PC32.TR2A.OSHP ()
+ \_SB.PC32.TR2B.OSHP ()
+ \_SB.PC32.TR2C.OSHP ()
+ \_SB.PC32.TR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0,33)) { // PC15
+ \_SB.PC33.TR3A.OSHP ()
+ \_SB.PC33.TR3B.OSHP ()
+ \_SB.PC33.TR3C.OSHP ()
+ \_SB.PC33.TR3D.OSHP ()
+ }
+ if (LEqual(Arg0,34)) { // PC16
+ \_SB.PC34.TR4A.OSHP ()
+ \_SB.PC34.TR4B.OSHP ()
+ \_SB.PC34.TR4C.OSHP ()
+ \_SB.PC34.TR4D.OSHP ()
+ }
+ if (LEqual(Arg0,35)) { // PC17
+ \_SB.PC35.TR5A.OSHP ()
+ \_SB.PC35.TR5B.OSHP ()
+ \_SB.PC35.TR5C.OSHP ()
+ \_SB.PC35.TR5D.OSHP ()
+ }
+#endif
+#if MAX_SOCKET > 6
+ if (LEqual(Arg0,37)) { // PC37
+ \_SB.PC37.UR1A.OSHP ()
+ \_SB.PC37.UR1B.OSHP ()
+ \_SB.PC37.UR1C.OSHP ()
+ \_SB.PC37.UR1D.OSHP ()
+ }
+ if (LEqual(Arg0,38)) { // PC38
+ \_SB.PC38.UR2A.OSHP ()
+ \_SB.PC38.UR2B.OSHP ()
+ \_SB.PC38.UR2C.OSHP ()
+ \_SB.PC38.UR2D.OSHP ()
+
+ }
+ if (LEqual(Arg0,39)) { // PC39
+ \_SB.PC39.UR3A.OSHP ()
+ \_SB.PC39.UR3B.OSHP ()
+ \_SB.PC39.UR3C.OSHP ()
+ \_SB.PC39.UR3D.OSHP ()
+ }
+ if (LEqual(Arg0,40)) { // PC40
+ \_SB.PC40.UR4A.OSHP ()
+ \_SB.PC40.UR4B.OSHP ()
+ \_SB.PC40.UR4C.OSHP ()
+ \_SB.PC40.UR4D.OSHP ()
+ }
+ if (LEqual(Arg0,41)) { // PC41
+
+ \_SB.PC41.UR5A.OSHP ()
+ \_SB.PC41.UR5B.OSHP ()
+ \_SB.PC41.UR5C.OSHP ()
+ \_SB.PC41.UR5D.OSHP ()
+ }
+#endif
+#if MAX_SOCKET > 7
+ if (LEqual(Arg0,43)) { // PC43
+ \_SB.PC43.VR1A.OSHP ()
+ \_SB.PC43.VR1B.OSHP ()
+ \_SB.PC43.VR1C.OSHP ()
+ \_SB.PC43.VR1D.OSHP ()
+ }
+ if (LEqual(Arg0,44)) { // PC44
+ }
+ if (LEqual(Arg0,45)) { // PC45
+ }
+#endif
+ } // end of OSCM
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi
new file mode 100644
index 0000000000..90dbfabcbe
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi
@@ -0,0 +1,164 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Device (DMAC) {
+ Name (_HID, EISAID("PNP0200"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16, 0x0, 0x0, 0, 0x10)
+ IO(Decode16, 0x81, 0x81, 0, 0x3)
+ IO(Decode16, 0x87, 0x87, 0, 0x1)
+ IO(Decode16, 0x89, 0x89, 0, 0x3)
+ IO(Decode16, 0x8f, 0x8f, 0, 0x1)
+ IO(Decode16, 0xc0, 0xc0, 0, 0x20)
+ DMA(Compatibility,NotBusMaster,Transfer8) {4}
+ })
+}
+
+Device (RTC) {
+ Name (_HID,EISAID("PNP0B00"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x70,0x70,0x01,0x02)
+ IO(Decode16,0x72,0x72,0x01,0x02)
+ IO(Decode16,0x74,0x74,0x01,0x04)
+ IRQNoFlags(){8}
+ })
+}
+
+Device (PIC) {
+ Name (_HID,EISAID("PNP0000"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases
+ IO(Decode16,0xA0,0xA0,0x01,0x1E)
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)
+ })
+}
+
+Device (FPU) {
+ Name (_HID,EISAID("PNP0C04"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0xF0,0xF0,0x01,0x1)
+ IRQNoFlags(){13}
+ })
+}
+
+Device(TMR)
+{
+ Name(_HID,EISAID("PNP0100"))
+
+ Name(_CRS,ResourceTemplate() {
+ IO(Decode16,0x40,0x40,0x01,0x04)
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias
+ IRQNoFlags(){0}
+ })
+}
+
+Device (SPKR) {
+ Name (_HID,EISAID("PNP0800"))
+ Name (_CRS,ResourceTemplate() {
+ IO(Decode16,0x61,0x61,0x01,0x01)
+ })
+}
+
+//
+// all "PNP0C02" devices- pieces that don't fit anywhere else
+//
+Device(XTRA) {
+ Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
+ Name(_CRS,
+ ResourceTemplate() {
+ IO(Decode16,0x500,0x500,0x01,0xFF) // ACPI base
+ IO(Decode16,0x400,0x400,0x01,0x20) // PM IO, ICH5
+
+ //
+ // Resource conflict with COM Port
+ //
+ //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime registers, National SIO
+ IO(Decode16,0x10,0x10,0x01,0x10)
+ IO(Decode16,0x80,0x80,0x01,0x01)
+ IO(Decode16,0x84,0x84,0x01,0x03)
+ IO(Decode16,0x88,0x88,0x01,0x01)
+ IO(Decode16,0x8c,0x8c,0x01,0x03)
+ IO(Decode16,0x90,0x90,0x01,0x10)
+ //
+ // Pilot Mail Box decode range
+ //
+ IO(Decode16,0x600,0x600,0x01,0x20)
+ //
+ // BMC KCS decode range
+ //
+ IO(Decode16,0xCA0,0xCA0,0x01,0x2)
+ IO(Decode16,0xCA4,0xCA4,0x01,0x3)
+
+ //IO Descriptor added for range 2F8-2FF for S501706
+ //IO(Decode16,0x2F8,0x2F8,0x01,0x08)
+ //IO(Decode16,0x60,0x60,0x01,0x01)
+ //IO(Decode16,0x64,0x64,0x01,0x01)
+
+ //
+ // FLASH range
+ //
+ Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO spec
+
+ }
+ )
+}
+
+//
+// High Performance Event Timer (HPET)
+//
+Device (HPET) {
+ Name (_HID, EisaId ("PNP0103"))
+
+ Method (_STA, 0, NotSerialized) {
+ If (\HPTE) {
+ Return (0x0F)
+ } Else {
+ Return (0x00)
+ }
+ }
+
+ Name (CRS0, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+
+ Name (CRS1, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400)
+ })
+
+ Name (CRS2, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400)
+ })
+
+ Name (CRS3, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400)
+ })
+
+ //
+ // Owning control method can't be re-entrant, so _CRS must be Serialized
+ //
+ Method (_CRS, 0, Serialized) {
+ Switch (ToInteger(\HPTB)) {
+ Case (0xFED00000) {
+ Return (CRS0)
+ }
+
+ Case (0xFED01000) {
+ Return (CRS1)
+ }
+
+ Case (0xFED02000) {
+ Return (CRS2)
+ }
+
+ Case (0xFED03000) {
+ Return (CRS3)
+ }
+ }
+ Return (CRS0)
+ }
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi
new file mode 100644
index 0000000000..f0c44e67c1
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi
@@ -0,0 +1,25 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Method (NNPR, 0) // NTPR == NoTify PRe
+{
+ External (\_SB.NVDR.NTPR, MethodObj)
+ Store(Package () {}, Local0)
+ if (CondRefOf (\_SB.NVDR.NTPR)) {
+ Store (\_SB.NVDR.NTPR (), Local0) // Local0 == Opaque Package
+ }
+ Return (Local0)
+}
+
+Method (NNDO, 1) // Nvdimm Notify DO
+{
+ External (\_SB.NVDR.NTDO, MethodObj)
+ if (CondRefOf (\_SB.NVDR.NTDO)) {
+ \_SB.NVDR.NTDO (Arg0)
+ }
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi
new file mode 100644
index 0000000000..e2d5fcc78f
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi
@@ -0,0 +1,66 @@
+/** @file
+
+ @copyright
+ Copyright 2017-2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Scope (\_SB) {
+
+ Name (XCNT, 0)
+ Name (OSYS, 0) // Global variable for type of OS.
+
+ Method (_INI) {
+
+ If (CondRefOf (_OSI)) {
+ If (\_OSI ("Windows 2012")) {
+ Store (13, OSYS) // Windows Server 2012 & Windows 8
+ }
+
+ If (\_OSI ("Windows 2013")) {
+ Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1
+ }
+
+ If (\_OSI ("Windows 2015")) {
+ Store (15, OSYS) // Windows 10
+ }
+ //
+ // Check Linux also
+ //
+
+ If (\_OSI ("FreeBSD")) {
+ Store (2, OSYS)
+ }
+
+ If (\_OSI ("HP-UX")) {
+ Store (3, OSYS)
+ }
+
+ If (\_OSI ("OpenVMS")) {
+ Store (4, OSYS)
+ }
+
+ //
+ // Running WinSvr2012, Win8, or later?
+ //
+ If (LGreaterEqual (\_SB.OSYS, 13)) {
+ //
+ // It is Svr2012 or Win8
+ // Call xHCI device to switch USB ports over
+ // unless it has been done already
+ //
+ If (LEqual (XCNT, 0)) {
+ if(LEqual(DBGM, 0x01)){
+ Store (0x84, IO80)
+ }
+ Increment (XCNT)
+ }
+ } Else {
+ if(LEqual(DBGM, 0x01)){
+ Store (\_SB.OSYS, IO80)
+ }
+ }
+ }
+ } // End Method (_INI)
+} // End Scope (_SB)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi
new file mode 100644
index 0000000000..9f24076ef5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi
@@ -0,0 +1,427 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+ External (DBGM, FieldUnitObj)
+
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ //
+ // _BBN is ACPI method called by OS to read PCI base bus number for IIO stack.
+ //
+ Method(_BBN, 0, NotSerialized)
+ {
+ Return(BB00)
+ }
+
+ //
+ // _PXM is ACPI method called by OS to read Proximity Domain of IIO stack.
+ //
+ Method(_PXM, 0, NotSerialized)
+ {
+ Return(0)
+ }
+
+ //
+ // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
+ //
+ Method(_SEG, 0, NotSerialized)
+ {
+ Return(SG00)
+ }
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+
+ //
+ // Select Native PCIe AER/eDPC handling from OS or Firmware First model
+ //
+ If (CondRefOf (\_SB.OSNC))
+ {
+ //in case OS has AER capability.
+ If (LEqual ( And(CTRL, 8), 8)) {
+
+ //in case OS support multiple segment.
+ If (And (SUPP, 8)) {
+ If (CondRefof (^_SEG))
+ {
+ Store (^_SEG, Local0)
+ } Else {
+ Store (0, Local0)
+ }
+ } Else {
+ Store (0, Local0)
+ }
+
+ Store (^_BBN, Local1)
+
+ // if BIOS allows OS take. Do nothing.
+ If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) {
+
+ } Else {
+ And (CTRL, Not(0x88), CTRL)
+ }
+ } Else {
+ And (CTRL, Not(0x88), CTRL)
+ }
+ } Else {
+ //
+ //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, eDPC is bit7
+ //
+ And (CTRL, Not(0x88), CTRL)
+ }
+
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ if(LEqual(DBGM, 0x01)){
+ Store (0xE3, IO80)
+ }
+ \_SB.PC01.BR1A.OSHP ()
+ \_SB.PC01.BR1B.OSHP ()
+ \_SB.PC01.BR1C.OSHP ()
+ \_SB.PC01.BR1D.OSHP ()
+
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ if(LEqual(DBGM, 0x01)){
+ Store (0xEE, IO80)
+ }
+ Return(Arg3)
+ }
+ } // End _OSC
+
+#include "PchApic.asi"
+
+
+#define RESOURCE_CHUNK1_OFF 0
+#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
+#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
+#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
+#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
+#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
+#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
+
+#define PciResourceStart Local0
+#define PciResourceLen Local1
+
+ Name(P0RS, ResourceTemplate() {
+ //RESOURCE_CHUNK1_OFF
+ WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK2_OFF
+ IO( // Consumed resource (CF8-CFF)
+ Decode16,
+ 0x0cf8,
+ 0xcf8,
+ 1,
+ 8
+ )
+
+ //RESOURCE_CHUNK3_OFF
+ WORDIO( // Consumed-and-produced resource (all I/O below CF8)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Min
+ 0x0cf7, // Max
+ 0x0000, // Translation
+ 0x0cf8 // Range Length
+ )
+
+ //RESOURCE_CHUNK4_OFF
+ WORDIO( // Consumed-and-produced resource (all I/O above CFF)
+ ResourceProducer, // bit 0 of general flags is 0
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode,
+ EntireRange,
+ 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length (FIX2 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //RESOURCE_CHUNK5_OFF
+ DWORDMEMORY( // descriptor for video RAM on video card
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX5 // Descriptor Name
+ )
+
+ //RESOURCE_CHUNK6_OFF
+ DWORDMEMORY( // descriptor for Shadow RAM
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode,
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is Fixed
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Min (calculated dynamically)
+ 0x00000000, // Max (calculated dynamically)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically)
+ ,
+ ,
+ SRAM // DescriptorName populated so iASL doesn't flag 0 value fields and no tag as error
+ )
+/*
+ //RESOURCE_TPM
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Min (calculated dynamically)
+ 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
+ 0x00000000, // Translation
+ 0x000C0000 // Range Length (calculated dynamically)
+ )
+*/
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000)
+
+ //
+ // PCI RESOURCE_32bit
+ //
+ DWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST)
+ 0x00000000, // Translation
+ 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+
+ //
+ // PCI RESOURCE_64bit
+ //
+ QWORDMemory( // Consumed-and-produced resource(all of memory space)
+ ResourceProducer, // bit 0 of general flags is 0
+ PosDecode, // positive Decode
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ NonCacheable,
+ ReadWrite,
+ 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST)
+ 0x00000000000, // Translation
+ 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ }) // end of P0RS Buffer
+
+ OperationRegion(TMEM, PCI_Config, 0x00, 0x100)
+ Field(TMEM, ByteAcc, NoLock, Preserve) {
+ Offset(0x40),
+ , 4,
+ BSEG, 4,
+ PAMS, 48,
+ Offset(0x52),
+ DIM0, 4,
+ DIM1, 4,
+ , 8,
+ DIM2, 4,
+ }
+
+ Name(MTBL, Package(0x10) {
+ 0x0,
+ 0x20,
+ 0x20,
+ 0x30,
+ 0x40,
+ 0x40,
+ 0x60,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xc0,
+ 0x100,
+ 0x100,
+ 0x100,
+ 0x200
+ })
+
+ Name(ERNG, Package(0xd) {
+ 0xc0000,
+ 0xc4000,
+ 0xc8000,
+ 0xcc000,
+ 0xd0000,
+ 0xd4000,
+ 0xd8000,
+ 0xdc000,
+ 0xe0000,
+ 0xe4000,
+ 0xe8000,
+ 0xec000,
+ 0xf0000
+ })
+
+ Name(PAMB, Buffer(0x7) {
+ })
+
+ Method(EROM, 0x0, NotSerialized) {
+ CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard-coded address
+ CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference hard-coded address
+ CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard-coded address
+ CreateByteField(PAMB, 0x6, BREG)
+ Store(PAMS, PAMB)
+ Store(BSEG, BREG)
+ Store(0x0, RMIN)
+ Store(0x0, RMAX)
+ Store(0x0, RLEN)
+ Store(0x0, Local0)
+ While(LLess(Local0, 0xd))
+ {
+ ShiftRight(Local0, 0x1, Local1)
+ Store(DerefOf(Index(PAMB, Local1, )), Local2)
+ If(And(Local0, 0x1, ))
+ {
+ ShiftRight(Local2, 0x4, Local2)
+ }
+ And(Local2, 0x3, Local2)
+ If(RMIN)
+ {
+ If(Local2)
+ {
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff))
+ {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ }
+ Else
+ {
+ Store(0xc, Local0)
+ }
+ }
+ Else
+ {
+ If(Local2)
+ {
+ Store(DerefOf(Index(ERNG, Local0, )), RMIN)
+ Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
+ If(LEqual(RMAX, 0xf3fff))
+ {
+ Store(0xfffff, RMAX)
+ }
+ Subtract(RMAX, RMIN, RLEN)
+ Increment(RLEN)
+ }
+ Else
+ {
+ }
+ }
+ Increment(Local0)
+ }
+ }
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized) {
+ EROM()
+ Return(P0RS)
+ }
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi
new file mode 100644
index 0000000000..966cd82640
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 0610 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if PC06 is removed.
+ Name(_EJD,"\\_SB.PC06") // Dependent on PC18
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi
new file mode 100644
index 0000000000..6c210da62d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if PC12 is removed.
+ Name(_EJD,"\\_SB.PC12") // Dependent on PC18
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi
new file mode 100644
index 0000000000..7b6aa91cd5
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if PC18 is removed.
+ Name(_EJD,"\\_SB.PC18") // Dependent on PC18
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi
new file mode 100644
index 0000000000..e76063647e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi
@@ -0,0 +1,18 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2012 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Device(APIC) {
+ Name (_HID,EISAID("PNP0003")) // APIC resources
+ Name (_CRS, ResourceTemplate() {
+ //
+ // APIC range(0xFEC0_0000 to 0xFECF_FFFF)
+ //
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC
+ }
+ )
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi
new file mode 100644
index 0000000000..64484e5402
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi
@@ -0,0 +1,669 @@
+/** @file
+
+ @copyright
+ Copyright 2007 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ External (DBGM, FieldUnitObj)
+
+ Method (_INI, 0, NotSerialized)
+ {
+ }
+
+ Name(_HPP, Package(){0x08, 0x40, SERR, PERR})
+
+ //
+ // begin hotplug code
+ //
+ Name(SHPC, 0x40) // Slot Hot-plug Capable
+
+ Name(SPDS, 0x040) // Slot Presence Detect State
+
+ Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
+ Name(CCOM, 0x010) // Command Complete
+ Name(SPDC, 0x08) // Slot Presence Detect Changes
+ Name(MRLC, 0x04) // Slot MRL Changed
+ Name(SPFD, 0x02) // Slot Power Fault Detected
+ Name(SABP, 0x01) // Slot Attention Button Pressed
+
+ Name(SPOF, 0x10) // Slot Power Off
+ Name(SPON, 0x0F) // Slot Power On Mask
+
+ Name(ALMK, 0x1C) // Slot Atten. LED Mask
+ Name(ALON, 0x01) // Slot Atten. LED On
+ Name(ALBL, 0x02) // Slot Atten LED Blink
+ Name(ALOF, 0x03) // Slot Atten LED Off
+
+ Name(PLMK, 0x13) // Slot Pwr. LED Mask
+ Name(PLON, 0x04) // Slot Pwr. LED On
+ Name(PLBL, 0x08) // Slot Pwr. LED Blink
+ Name(PLOF, 0x0C) // Slot Pwr. LED Off
+
+ //;*************************************
+ //; Bit 3 = Presence Detect Event
+ //; Bit 2 = MRL Sensor Event
+ //; Bit 1 = PWR Fault Event
+ //; Bit 0 = Attention Button Event
+ //;*************************************
+ Name(HPEV, 0xF) // Possible interrupt events (all)
+
+ //;************************************************************************;
+ //; PCIe Slot Capabilities Register
+ //; Bit - 31-5 - Not used
+ //; Bit - 4 - Power Indicator Present.
+ //; Bit - 3 - Attention Indicator Present.
+ //; Bit - 2 - MRL Sensor Present.
+ //; Bit - 1 - Power Controller Present.
+ //; Bit - 0 - Attention Button Present.
+ //;
+ //; PCIe Slot control Register
+ //; Bit - 10 - PWR Control Disable
+ //; Bit - 9:8 - Attn Indicator
+ //; Bit - 7:6 - PWR Indicator
+ //; Bit - 5 - Hot-Plug Interrupt Event Enable
+ //; Bit - 4 - Command Complete Interrupt enable
+ //; Bit - 3 - Presence Detect Changed Interrupt enable
+ //; Bit - 2 - MRL Sensor Changed Interrupt enable
+ //; Bit - 1 - PwrFault Detect Interrupt enable
+ //; Bit - 0 - Attention Button Pressed Interrupt Enable
+ //;
+ //; PCIe Slot Status Registers
+ //; Bit - 6 - Presence Detect State.
+ //; Bit - 5 - MRL Sensor State.
+ //; Bit - 4 - Command Completed.
+ //;
+ //; RWC Status Bits
+ //;
+ //; Bit - 3 - Presence Detect Changed.
+ //; Bit - 2 - MRL Sensor Changed.
+ //; Bit - 1 - Power Fault Detected.
+ //; Bit - 0 - Attention Button Pressed.
+ //;************************************************************************;
+ OperationRegion (PXCP, PCI_Config, IRPC, 0x40)
+ Field (PXCP, ByteAcc, NoLock, Preserve) {
+ Offset (0x10), // Link Control Register
+ , 4,
+ LDIS, 1, // Link Disable bit4.
+ , 11,
+ Offset (0x14), // PCI Slot Capabilities Register
+ ATBP, 1, // Attention Button Present
+ , 1,
+ MRSP, 1, // MRL Sensor Present
+ ATIP, 1, // Attention Indicator Present
+ PWIP, 1, // Power Indicator Present
+ , 14,
+ PSNM, 13, // Physical Slot Number
+ Offset (0x18), // Slot Control Register
+ ABIE, 1, // Attention Button Pressed Interrupt Enable
+ PFIE, 1, // Power Fault Detected Interrupt Enable
+ MSIE, 1, // MRL Sensor Changed Interrupt Enable
+ PDIE, 1, // Presence Detect Changed Interrupt Enable.
+ CCIE, 1, // Command Complete Interrupt Enable.
+ HPIE, 1, // Hot-plug Interrupt Enable.
+ SCTL, 5, // Attn/Power indicator and Power controller.
+ , 5,
+ Offset (0x1A), // Slot Status Register
+ SSTS, 7, // The status bits in Slot Status Reg
+ , 1,
+ Offset (0x20), // Root Status Register
+ , 16,
+ PMES, 1, // PME Status bit 16
+ PMEP, 1, // PME Pending bit 17
+ , 14
+ }
+
+ //
+ // These Methods replace the bit field definitions in PPA8
+ // that were bit fields within SCTL
+ //
+ Method (ATID, 0) {
+ Return (And (SCTL, 0x03))
+ }
+
+ Method (PWID, 0) {
+ Return (ShiftRight (And (SCTL, 0x0C), 2))
+ }
+
+ Method (PWCC, 0) {
+ Return (ShiftRight (And (SCTL, 0x10), 4))
+ }
+
+ //
+ // These methods replace the bit fields definitions in PPA8
+ // that were bit fields within SSTS
+ //
+ Method (ABPS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x01, SSTS)
+ }
+ Return (And (SSTS, 0x01))
+ }
+
+ Method (PFDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x02, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x02), 1))
+ }
+
+ Method (MSCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x04, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x04), 2))
+ }
+
+ Method (PDCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x08, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x08), 3))
+ }
+
+ Method (CMCS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x10, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x10), 4))
+ }
+
+ Method (MSSC, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x20, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x20), 5))
+ }
+
+ Method (PRDS, 1) {
+ If (LEqual (Arg0, 1)) {
+ Or (SSTS, 0x40, SSTS)
+ }
+ Return (ShiftRight (And (SSTS, 0x40), 6))
+ }
+
+
+ //;************************************************************************;
+ //; This OSHP (Operating System Hot Plug) method is provided for each HPC
+ //; which is controlled by ACPI. This method disables ACPI access to the
+ //; HPC and restores the normal System Interrupt and Wakeup Signal
+ //; connection.
+ //;************************************************************************;
+ Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
+ Store(SSTS, Local0) // Clear any status (RW1C)
+ Store(Local0, SSTS) // (use write thru Local to avoid iasl warning 'Duplicate value in list ^ (Source is the same as Target)')
+ }
+
+ //;************************************************************************;
+ //; Hot Plug Controller Command Method
+ //;
+ //; Input: Arg0 - Command to issue
+ //;
+ //;************************************************************************;
+ Method(HPCC,1) {
+ Store(SCTL, Local0) // get current command state
+ Store(0, Local1) // reset the timeout value
+ If(LNotEqual(Arg0, Local0)) { // see if state is different
+ Store(Arg0, SCTL) // Update the Slot Control
+ While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
+ // check for timeout to avoid dead loop
+ if(LEqual(DBGM, 0x01)){
+ Store(0xFB, IO80)
+ }
+ Sleep(2) // allow processor time slice
+ Add(Local1, 2, Local1)
+ }
+ CMCS(1) // Clear the command complete status
+ }
+ }
+
+ //;************************************************************************;
+ //; Attention Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(ATCM,1) {
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
+ Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
+ Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Indicator Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = ON
+ //; 2 = Blink
+ //; 3 = OFF
+ //;************************************************************************;
+ Method(PWCM,1){
+ Store(SCTL, Local0) // Get Slot Control
+ And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
+ If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
+ Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
+ }
+ If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
+ Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
+ }
+ If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; Power Slot Command
+ //;
+ //; Input: Arg0 - Command to issue
+ //; 1 = Slot Power ON
+ //; 2 = Slot Power Off
+ //;************************************************************************;
+ Method(PWSL,1){
+ Store(SCTL, Local0) // Get Slot Control
+ If(Arg0){ // Power Slot "ON" Arg0 = 1
+ And(Local0, SPON, Local0) // Turns the Power "ON"
+ } Else { // Power Slot "OFF"
+ Or(Local0, SPOF, Local0) // Turns the Power "OFF"
+ }
+ HPCC(Local0)
+ }
+
+ //;************************************************************************;
+ //; _OST Methods to indicate that the device Eject/insert request is
+ //; pending, OS could not complete it
+ //;
+ //; Input: Arg0 - Value used in Notify to OS
+ //; 0x00 - card insert
+ //; 0x03 - card eject
+ //; Arg1 - status of Notify
+ //; 0 - success
+ //; 0x80 - Ejection not supported by OSPM
+ //; 0x81 - Device in use
+ //; 0x82 - Device Busy
+ //; 0x84 - Ejection in progress-pending
+ //;************************************************************************;
+ Method(_OST,3,Serialized) {
+ Switch(And(Arg0,0xFF)) { // Mask to retain low byte
+ Case(0x03) { // Ejection Request
+ Switch(ToInteger(Arg1)) {
+ Case(Package() {0x80, 0x81, 0x82, 0x83}) {
+ //
+ // Ejection Failure for some reason
+ //
+ If (Lnot(PWCC())) { // if slot is powered
+ PWCM(0x1) // Set PowerIndicator to ON
+ Store(0x1,ABIE) // Set AttnBtn Interrupt ON
+ }
+ }
+ }
+ }
+ }
+ #include "IioPcieEdpcOst.asi"
+ } // End _OST
+
+ //
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index (0 = Return Supported Functions)
+ // Arg3: Package Parameters
+ Method(_DSM, 4, Serialized) {
+ //
+ // Switch based on which unique function identifier was passed in
+ //
+ If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
+ //
+ // _DSM Definitions for Latency Tolerance Reporting
+ //
+ // Arguments:
+ // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
+ // Arg1: Revision ID: 3
+ // Arg2: Function Index: 0, c, d
+ // Arg3: Empty Package
+ //
+ // Switch by function index
+ //
+ Switch(ToInteger(Arg2)) {
+ //
+ // Function Index:0
+ // Standard query - A bitmask of functions supported
+ //
+ Case (0) {
+ Name(OPTS, Buffer(2) {0, 0})
+ CreateBitField(OPTS, 0, FUN0)
+ CreateBitField(OPTS, 12, FUNC)
+ CreateBitField(OPTS, 13, FUND)
+
+ Store(1, FUN0)
+ Store(1, FUNC)
+ Store(1, FUND)
+ Return(OPTS)
+ }
+ //
+ // Function Index: C
+ // Downstream Port Containment Hint
+ //
+ Case(12) {
+ Return(1)
+ }
+
+ //
+ // Function Index: D
+ // Downstream Port Containment Device Location
+ //
+ Case(13) {
+ Name(DLOC, Buffer(2){0, 0})
+ CreateField(DLOC, 0, 3, DFUN)
+ CreateField(DLOC, 3, 5, DDEV)
+ CreateField(DLOC, 8, 8, DBUS)
+ Store(_BBN, DBUS)
+ store(_ADR, Local2)
+ And(Local2, 0xffff, Local3)
+ ShiftRight (Local2, 16, Local4)
+ Store(Local4, DDEV)
+ Store(Local3, DFUN)
+ Return(ToInteger(DLOC))
+ }
+
+ } // End of switch(Arg2)
+ } // End of if
+ return (Buffer() {0x00})
+ } // End of _DSM
+
+ //;************************************************************************;
+ //; Eject Control Methods to indicate that the device is hot-ejectable and
+ //; should "eject" the device.
+ //;
+ //;
+ //;************************************************************************;
+ Method(EJ0L){
+ if(LEqual(DBGM, 0x01)){
+ Store(0xFF, IO80)
+ }
+ Store(SCTL, Local0) // Get IIO Port Control state
+ if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid "ON"
+ And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
+ Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
+ }
+ HPCC(Local0) // issue command
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
+ HPCC(Local0)
+
+ Store(SCTL, Local0) // Get IIO Port Control state
+ Or(Local0, ALOF, Local0) // Set the Attntion LED to Off.
+ HPCC(Local0)
+
+ } // End of EJ0L
+
+ //;************************************************************************;
+ //; PM_PME Wake Handler for All Slots
+ //;
+ //; Input: Arg0 - Slot Numnber
+ //;
+ //;************************************************************************;
+ Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interupt (GPI xxh)
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ If(ABPS(0)) {
+ if(LEqual(DBGM, 0x01)){
+ if(LEqual(DBGM, 0x01)){
+ Store (Arg0, IO80) // Send slot number to Port 80
+ }
+ }
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ }
+ }
+ Return (0xff) // Indicate that this controller did not interrupt
+ } // End of Method PMEH
+
+ //;************************************************************************;
+ //; Hot-Plug Handler for All Slots.
+ //;
+ //; Input: Arg0 - Slot Number
+ //;
+ //;************************************************************************;
+ Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt (GPI xxh)
+ if(LEqual(DBGM, 0x01)){
+ Store(0xFE, IO80)
+ }
+ Sleep(100)
+ Store(0,CCIE) // Disable command interrupt
+ If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
+ if(LEqual(DBGM, 0x01)){
+ Store(0xFD, IO80)
+ }
+ Sleep(10)
+ if(LEqual(DBGM, 0x01)){
+ Store (Arg0, IO80) // Send slot number to Port 80
+ }
+ Sleep(10)
+ Store(PPXH(), Local0) // Call Hot plug Interrupt Handler
+ Return(Local0) // Return PPXH information
+ }
+ Else{
+ Return (0xff) // Indicate that this controller did not interrupt
+ }
+ if(LEqual(DBGM, 0x01)){
+ Store(0xFC, IO80)
+ }
+ Sleep(10)
+ } // End of Method HPEH
+
+ //;************************************************************************;
+ //; Interrut Event Handler
+ //;
+ //;
+ //;************************************************************************;
+ Method(PPXH){ // Hot plug Interrupt Handler
+ //
+ // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
+ //
+ Sleep(200) // HW Workaround for AttentionButton Status to stabilise
+ If(ABPS(0)) { // Check if Attention Button Pressed
+ If(LNot(PRDS(0))) { // See if nothing installed (no card in slot)
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ PWSL(0x0) // make sure Power is Off
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ //
+ // Check for MRL here and set attn indicator accordingly
+ //
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ } else { // Standby power is off - MRL open
+ ATCM(0x3) // set attention indicator "OFF"
+ }
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return(0xff) // Attn Button pressed without card in slot. Do nothing
+ }
+ //
+ // Card is present in slot so....
+ //
+ Store(0x0, ABIE) // set Attention Button Interrupt to disable
+ // Attn Btn Interrupt has to be enabled only after an insert oprn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ //
+ // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
+ //
+ //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off
+ // PWSL(0x0) // make sure Power is Off
+ // PWCM(0x3) // Set Power Indicator to "OFF"
+ // ATCM(0x2) // Set Attention Indicator to "BLINK"
+ // Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
+ //}
+ //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
+ If(PWCC()) { // Slot not Powered
+ PWCM(0x3) // Set Power Indicator to "OFF"
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
+ } Else { // See if Slot is already Powered
+ PWCM(0x2) // Set power Indicator to BLINK
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
+ ABPS(1) // Clear the interrupt status
+ Sleep(200) // delay 200ms
+ Return (0x3) // continue with Eject request
+ }
+ }
+ PWCM(0x1) // Set power Indicator baCK "ON"
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Store(0x1, ABIE) // set Attention Button Interrupt to enable
+ Return (0xff) // do nothing and abort
+ }
+ } // End if for the Attention Button Hot Plug Interrupt.
+
+ If(PFDS(0)) { // Check if Power Fault Detected
+ PFDS(1) // Clear the Power Fault Status
+ PWSL(0x0) // set Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } // End if for the Power Fault Interrupt.
+
+ If(MSCS(0)) { // Check interrupt caused by the MRL Sensor
+ MSCS(1) // Clear the MRL Status
+ If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
+ If(PRDS(0)) { // Card is Present
+
+ ATCM(0x3) // Set Attention Indicator to off
+ PWCM(0x2) // Set Power Indicator to Blink
+ Sleep(600) // Wait 100ms
+ Store(600, Local0) // set 5 second accumulator to 0
+ ABPS(1) // Clear the interrupt status
+ While(LNot(ABPS(0))) { // check for someone pressing Attention
+ Sleep(200) // Wait 200ms
+ Add(Local0, 200, Local0)
+ If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // set attention indicator "OFF"
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Power the Slot
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ // Check for the Power Fault Detection
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
+ // Notify the OS to load the Driver for the card
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ }
+ //
+ // someone pressed Attention Button
+ //
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ // End of Insert sequence
+ }
+ //MRL is closed, Card is not present
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ ATCM(02) // Set Attention Indicator to "BLINK"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xff) // leave it off
+ } Else { // MRL is open i.e Stdby power is turned off
+ If(PRDS(0)) { //card present MRL switched off
+ ATCM(0x2) // Set Attention Indicator to "BLINK"
+ If(Lnot(PWCC())) { // If slot is powered
+ // This event is not supported and someone has opened the MRL and dumped the power
+ // on the slot with possible pending transactions. This could hose the OS.
+ // Try to Notify the OS to unload the drivers.
+ PWSL(0x0) // Set Slot Power off
+ PWCM(0x3) // Set Power Indicator back to "OFF"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0x03) // Eject request.
+ } Else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
+ Return(0xFF)
+ }
+ }
+ //no card present and Stdby power switched off, turn AI off
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ Return(0xff) // leave it off
+ } // End of MRL switch open/close state
+ } // End of MRL Sensor State Change
+
+ If(PDCS(0)) { // Check if Presence Detect Changed Status
+ PDCS(1) // Clear the Presence Detect Changed Status
+ If(LNot(PRDS(0))) { // Slot is Empty
+ PWSL(0x0) // Set Slot Power "OFF"
+ PWCM(0x3) // set power indicator to "OFF"
+ If(LEqual(MSSC(0),MRLS)) { // If Standby power is on
+ ATCM(0x2) // Set Attention Indicator to "Blink"
+ } else {
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ }
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Return(0xFF) // Do nothing
+ } Else { // Slot Card is inserted
+ // Irrespective of MRL state, do the following
+ Store(0x0, LDIS) // Enable the Link associated with PCI-E port
+ PWSL(0x1) // Set Slot Power ON
+ Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
+ If(LNot(PFDS(0))) { // No Power Fault
+ PWCM(0x1) // Set Power Indicator to "ON"
+ Store(0x00, Local1)
+ Store(0x1, ABIE) // Enable Attention button interrupt
+ ATCM(0x3) // Set Attention Indicator to "OFF"
+ } Else { // Power Fault present
+ PWSL(0x0) // set Slot Power Off
+ PWCM(0x3) // set power indicator to OFF
+ ATCM(0x1) // set attention indicator "ON"
+ Store(0x1, LDIS) // Disable the Link associated with PCI-E port
+ Store(0x03, Local1) // Eject request.
+ } // End if for the Slot Power Fault
+ ABPS(1) // Clear the Attention status
+ Sleep(200) // delay 200ms
+ Return(Local1)
+ }
+ } // End if for the Presence Detect Changed Hot Plug Interrupt.
+ Return(0xff) // should not get here, but do device check if it does.
+ } // End of method PP5H
+ //
+ // End of hotplug code
+ //
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi
new file mode 100644
index 0000000000..ce48d3800a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi
@@ -0,0 +1,53 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Device(H000) {
+ Name(_ADR, 0x00000000)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H001) {
+ Name(_ADR, 0x00000001)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H002) {
+ Name(_ADR, 0x00000002)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H003) {
+ Name(_ADR, 0x00000003)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H004) {
+ Name(_ADR, 0x00000004)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H005) {
+ Name(_ADR, 0x00000005)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H006) {
+ Name(_ADR, 0x00000006)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
+ Device(H007) {
+ Name(_ADR, 0x00000007)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi
new file mode 100644
index 0000000000..44872cefd4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi
@@ -0,0 +1,45 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ Method(SNUM, 0, Serialized) {
+ Store(PSNM, Local0)
+ Return(Local0)
+ }
+
+ Device(H000) {
+ Name(_ADR, 0x00000000)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H001) {
+ Name(_ADR, 0x00000001)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H002) {
+ Name(_ADR, 0x00000002)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H003) {
+ Name(_ADR, 0x00000003)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H004) {
+ Name(_ADR, 0x00000004)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H005) {
+ Name(_ADR, 0x00000005)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H006) {
+ Name(_ADR, 0x00000006)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
+ Device(H007) {
+ Name(_ADR, 0x00000007)
+ Method(_SUN, 0) { Return(SNUM) } // Slot User Number
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl
new file mode 100644
index 0000000000..bd33a63efc
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl
@@ -0,0 +1,91 @@
+/** @file
+ ACPI DSDT table
+
+ @copyright
+ Copyright 2011 - 2019 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+//
+// Port from client
+//
+
+//
+// Original file line: 91
+//
+
+
+ External (\_SB.OSNC, MethodObj)
+
+
+
+//
+// Original file line: 163
+//
+
+Method(ADBG,1,Serialized)
+{
+ Return(0)
+}
+
+//
+// Original file line: 1460
+//
+Scope (\)
+{
+ //
+ // Global Name, returns current Interrupt controller mode;
+ // updated from _PIC control method
+ //
+
+ //
+ // Procedure: GPRW
+ //
+ // Description: Generic Wake up Control Method ("Big brother")
+ // to detect the Max Sleep State available in ASL Name scope
+ // and Return the Package compatible with _PRW format.
+ // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
+ // Arg1 = Max Sleep state, device can resume the System from.
+ // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
+ // Output: _PRW package
+ //
+ Name(PRWP, Package(){Zero, Zero}) // _PRW Package
+
+ Method(GPRW, 2)
+ {
+ Store(Arg0, Index(PRWP, 0)) // copy GPE#
+ //
+ // SS1-SS4 - enabled in BIOS Setup Sleep states
+ //
+ Store(ShiftLeft(SS1,1),Local0) // S1 ?
+ Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
+ Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
+ Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
+ //
+ // Local0 has a bit mask of enabled Sx(1 based)
+ // bit mask of enabled in BIOS Setup Sleep states(1 based)
+ //
+ If(And(ShiftLeft(1, Arg1), Local0))
+ {
+ //
+ // Requested wake up value (Arg1) is present in Sx list of available Sleep states
+ //
+ Store(Arg1, Index(PRWP, 1)) // copy Sx#
+ }
+ Else
+ {
+ //
+ // Not available -> match Wake up value to the higher Sx state
+ //
+ ShiftRight(Local0, 1, Local0)
+ // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
+ // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
+ // } Else { // ??? Win2k / XP
+ FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
+ // }
+ }
+
+ Return(PRWP)
+ }
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi
new file mode 100644
index 0000000000..4faa4cbaea
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi
@@ -0,0 +1,191 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "MaxSocket.h"
+External(\_SB.WERR, DeviceObj)
+
+// General Purpose Event
+
+Scope (\_GPE) {
+
+ // Based on Socket ID to be notified, evaluate appropriate devices.
+ Method(NTFC, 2){
+ If(And(Arg0, 0x01)){
+ Notify(\_SB.SCK0, Arg1)
+ }
+
+#if MAX_SOCKET > 1
+ If(And(Arg0, 0x02)){
+ Notify(\_SB.SCK1, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 2
+ If(And(Arg0, 0x04)){
+ Notify(\_SB.SCK2, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 3
+ If(And(Arg0, 0x08)){
+ Notify(\_SB.SCK3, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 4
+ If(And(Arg0, 0x10)){
+ Notify(\_SB.SCK4, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 5
+ If(And(Arg0, 0x20)){
+ Notify(\_SB.SCK5, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 6
+ If(And(Arg0, 0x40)){
+ Notify(\_SB.SCK6, Arg1)
+ }
+#endif
+
+#if MAX_SOCKET > 7
+ If(And(Arg0, 0x80)){
+ Notify(\_SB.SCK7, Arg1)
+ }
+#endif
+ } //End Method NTFC
+#if 0
+ Method(NTFM, 2){
+
+ // Based on Memory Board ID to be notified, evaluate appropriate devices.
+ If(And(Arg0, 0x01)){
+ Notify(\_SB.SCK0.M000, Arg1)
+ }
+ If(And(Arg0, 0x02)){
+ Notify(\_SB.SCK0.M001, Arg1)
+ }
+#if MAX_SOCKET > 1
+ If(And(Arg0, 0x04)){
+ Notify(\_SB.SCK1.M000, Arg1)
+ }
+ If(And(Arg0, 0x08)){
+ Notify(\_SB.SCK1.M001, Arg1)
+ }
+#endif
+#if MAX_SOCKET > 2
+ If(And(Arg0, 0x10)){
+ Notify(\_SB.SCK2.M000, Arg1)
+ }
+ If(And(Arg0, 0x20)){
+ Notify(\_SB.SCK2.M001, Arg1)
+ }
+#endif
+#if MAX_SOCKET > 3
+ If(And(Arg0, 0x40)){
+ Notify(\_SB.SCK3.M000, Arg1)
+ }
+ If(And(Arg0, 0x80)){
+ Notify(\_SB.SCK3.M001, Arg1)
+ }
+#endif
+
+ } // End Method NTFM
+#endif
+
+ Method(NTFI, 2){
+#if MAX_SOCKET > 1
+ If(And(Arg0, 0x01)){
+ Notify(\_SB.PC06, Arg1)
+ Notify(\_SB.PC07, Arg1)
+ Notify(\_SB.PC08, Arg1)
+ Notify(\_SB.PC09, Arg1)
+ Notify(\_SB.PC10, Arg1)
+ Notify(\_SB.PC11, Arg1)
+
+ }
+#endif
+#if MAX_SOCKET > 2
+ If(And(Arg0, 0x02)){
+ Notify(\_SB.PC12, Arg1)
+ Notify(\_SB.PC13, Arg1)
+ Notify(\_SB.PC14, Arg1)
+ Notify(\_SB.PC15, Arg1)
+ Notify(\_SB.PC16, Arg1)
+ Notify(\_SB.PC17, Arg1)
+ }
+#endif
+#if MAX_SOCKET > 3
+ If(And(Arg0, 0x04)){
+ Notify(\_SB.PC18, Arg1)
+ Notify(\_SB.PC19, Arg1)
+ Notify(\_SB.PC20, Arg1)
+ Notify(\_SB.PC21, Arg1)
+ Notify(\_SB.PC22, Arg1)
+ Notify(\_SB.PC23, Arg1)
+ }
+#endif
+ } //End Method NTFI
+
+ // Tell OS to run thru the new status of this device (Software SCI generated from SMM for all Hot plug events)
+ Method (_L62, 0x0, NotSerialized) {
+ if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
+ //NTFM (SCI1, 3)
+ NTFC (SCI2, 3)
+ Store (0, SCI0)
+ } ElseIf (LEqual(SCI0, 1)) { // Device check (OS can still reject online request based on resources and capability)
+ NTFC (CPHP, 0)
+ NTFI (IIOP, 0)
+ Store (0, CPHP)
+ Store (0, IIOP)
+ Store (0, SCI0)
+ }
+
+ #include "NvdimmGpe.asi"
+
+ // Retrieve leaf and root notification data pre SWGPE clear
+ Store (NNPR (), Local0)
+
+ Store (0, GPEC)
+
+ if(LEqual(WSCI, 0x1)) {
+ Store(0, WSCI)
+ if(LEqual(DBGM, 0x01)){
+ Store (0x4A, IO80)
+ }
+ If (CondRefOf (\_SB.WERR)) {
+ Notify (\_SB.WERR, 0x80)
+ }
+ }
+
+ // Perform NVDIMM leaf and root notifications with notification data updated post SWGPE clear
+ NNDO (Local0)
+
+ ///
+ /// Handle HWP SCI event
+ ///
+ //#include "HwpLvt.asi"
+
+ //
+ // Handle eDPC SWGPE event
+ //
+ #include "IioPcieEdpcGpe.asi"
+ }
+
+ // PME supported for Slots, use GPE 9 for PME
+ // Hot plug on all slots for now, change later.
+ // Slot numbers on silk screen might be different than the port number, currently use port numbers.
+ //
+ // IIO PCI_E Slot Hotplug GPE Event
+ //
+ Method (_L61, 0, NotSerialized) {
+ #include "IioPcieHotPlugGpeHandler10nm.asl"
+ }// end of _L61 GPE Method
+
+}// end of _GPE scope
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi
new file mode 100644
index 0000000000..2ad0a32d25
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi
@@ -0,0 +1,5388 @@
+/** @file
+ @copyright
+ Copyright 2005 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <MaxSocket.h>
+
+#ifndef CONCATENATE2
+#define CONCATENATE2_(a, b) a ## b
+#define CONCATENATE2(a, b) CONCATENATE2_(a, b)
+#endif
+#ifndef CONCATENATE3
+#define CONCATENATE3_(a, b, c) a ## b ## c
+#define CONCATENATE3(a, b, c) CONCATENATE3_(a, b, c)
+#endif
+
+Scope (\_SB) {
+
+ Name (AR00, Package() {
+ // [IIM0]: IIOMISC on PC00
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [CB0A]: CB3DMA on PC00
+ // [CB0E]: CB3DMA on PC00
+ Package() { 0x0001FFFF, 0, 0, 17 },
+ // [CB0B]: CB3DMA on PC00
+ // [CB0F]: CB3DMA on PC00
+ Package() { 0x0001FFFF, 1, 0, 18 },
+ // [CB0C]: CB3DMA on PC00
+ // [CB0G]: CB3DMA on PC00
+ Package() { 0x0001FFFF, 2, 0, 19 },
+ // [CB0D]: CB3DMA on PC00
+ // [CB0H]: CB3DMA on PC00
+ Package() { 0x0001FFFF, 3, 0, 16 },
+ // [MSM1] MSM
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ // [PMON] PMON MSM
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ // [NRPK]: NorthPeak
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [DMI0]: Legacy PCI Express Port 0 on PC00
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ // [IHC1]: IE HECI #1
+ // [IHC3]: IE HECI #3
+ Package() { 0x0010FFFF, 0, 0, 16 },
+ // [IHC2]: IE HECI #2
+ Package() { 0x0010FFFF, 1, 0, 17 },
+ // [IIDR]: IE IDE-Redirection (IDE-R)
+ Package() { 0x0010FFFF, 2, 0, 18 },
+ // [IMKT]: IE Keyboard and Text (KT) Redirection
+ Package() { 0x0010FFFF, 3, 0, 19 },
+ // [SAT2]: sSATA Host controller on PCH
+ // [MRO0]: MROM 0 function
+ // [MRO1]: MROM 1 function
+ Package() { 0x0011FFFF, 0, 0, 17 },
+ Package() { 0x0011FFFF, 1, 0, 18 },
+ Package() { 0x0011FFFF, 2, 0, 19 },
+ Package() { 0x0011FFFF, 3, 0, 16 },
+ // [XHCI]: xHCI controller 1 on PCH
+ Package() { 0x0014FFFF, 0, 0, 16 },
+ Package() { 0x0014FFFF, 1, 0, 17 },
+ // [TERM]: Thermal Subsystem on PCH
+ Package() { 0x0014FFFF, 2, 0, 18 },
+ Package() { 0x0014FFFF, 3, 0, 19 },
+ // [HEC1]: ME HECI #1 on PCH
+ // [HEC3]: ME HECI #3 on PCH
+ Package() { 0x0016FFFF, 0, 0, 18 },
+ // [HEC2]: ME HECI #2 on PCH
+ Package() { 0x0016FFFF, 1, 0, 19 },
+ // [IDER]: ME IDE redirect on PCH
+ Package() { 0x0016FFFF, 2, 0, 16 },
+ // [MEKT]: MEKT on PCH
+ Package() { 0x0016FFFF, 3, 0, 17 },
+ // [SAT1]: SATA controller 1 on PCH
+ Package() { 0x0017FFFF, 0, 0, 19 },
+ // [RP17]: PCIE PCH Root Port #17
+ Package() { 0x001BFFFF, 0, 0, 19 },
+ // [RP18]: PCIE PCH Root Port #18
+ Package() { 0x001BFFFF, 1, 0, 16 },
+ // [RP19]: PCIE PCH Root Port #19
+ Package() { 0x001BFFFF, 2, 0, 17 },
+ // [RP20]: PCIE PCH Root Port #20
+ Package() { 0x001BFFFF, 3, 0, 18 },
+ // [RP01]: PCIE PCH Root Port #1
+ // [RP05]: PCIE PCH Root Port #5
+ Package() { 0x001CFFFF, 0, 0, 16 },
+ // [RP02]: PCIE PCH Root Port #2
+ // [RP06]: PCIE PCH Root Port #6
+ Package() { 0x001CFFFF, 1, 0, 17 },
+ // [RP03]: PCIE PCH Root Port #3
+ // [RP07]: PCIE PCH Root Port #7
+ Package() { 0x001CFFFF, 2, 0, 18 },
+ // [RP04]: PCIE PCH Root Port #4
+ // [RP08]: PCIE PCH Root Port #8
+ Package() { 0x001CFFFF, 3, 0, 19 },
+ // [RP09]: PCIE PCH Root Port #9
+ // [RP13]: PCIE PCH Root Port #13
+ Package() { 0x001DFFFF, 0, 0, 17 },
+ // [RP10]: PCIE PCH Root Port #10
+ // [RP14]: PCIE PCH Root Port #14
+ Package() { 0x001DFFFF, 1, 0, 18 },
+ // [RP11]: PCIE PCH Root Port #11
+ // [RP15]: PCIE PCH Root Port #15
+ Package() { 0x001DFFFF, 2, 0, 19 },
+ // [RP12]: PCIE PCH Root Port #12
+ // [RP16]: PCIE PCH Root Port #16
+ Package() { 0x001DFFFF, 3, 0, 16 },
+ // [P2SB]: P2SB
+ // [PMC1]: Power Management Controller on PCH
+ // [CAVS]: HD Audio Subsystem Controller on PCH
+ // [SMBS]: SMBus controller on PCH
+ // [GBE1]: GbE Controller on PCH
+ // [TRHB]: Intel Trace Hub on PCH
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ })
+
+ Name (AR01, Package() {
+ // [SLTH]: PCIE PCH Slot #17
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR02, Package() {
+ // [SLTI]: PCIE PCH Slot #18
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR03, Package() {
+ // [SLTJ]: PCIE PCH Slot #19
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR04, Package() {
+ // [SLTK]: PCIE PCH Slot #20
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR05, Package() {
+ // [SLT1]: PCIE PCH Slot #1
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR06, Package() {
+ // [SLT2]: PCIE PCH Slot #2
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR07, Package() {
+ // [SLT3]: PCIE PCH Slot #3
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR08, Package() {
+ // [SLT4]: PCIE PCH Slot #4
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR09, Package() {
+ // [SLT5]: PCIE PCH Slot #5
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR0A, Package() {
+ // [SLT6]: PCIE PCH Slot #6
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR0B, Package() {
+ // [SLT7]: PCIE PCH Slot #7
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR0C, Package() {
+ // [SLT8]: PCIE PCH Slot #8
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR0D, Package() {
+ // [SLT9]: PCIE PCH Slot #9
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR0E, Package() {
+ // [SLTA]: PCIE PCH Slot #10
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR0F, Package() {
+ // [SLTB]: PCIE PCH Slot #11
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR10, Package() {
+ // [SLTC]: PCIE PCH Slot #12
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR11, Package() {
+ // [SLTD]: PCIE PCH Slot #13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR12, Package() {
+ // [SLTE]: PCIE PCH Slot #14
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR13, Package() {
+ // [SLTF]: PCIE PCH Slot #15
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR14, Package() {
+ // [SLTG]: PCIE PCH Slot #16
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR15, Package() {
+ // [BR1A]: PCI Express Port 1A on PC01
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [BR1B]: PCI Express Port 1B on PC01
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [BR1C]: PCI Express Port 1C on PC01
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [BR1D]: PCI Express Port 1D on PC01
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR16, Package() {
+ // [SL01]: PCI Express Slot 1 on 1A on PC01
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR17, Package() {
+ // [SL02]: PCI Express Slot 2 on 1B on PC01
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR18, Package() {
+ // [SL03]: PCI Express Slot 3 on 1C on PC01
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR19, Package() {
+ // [SL04]: PCI Express Slot 4 on 1D on PC01
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR1A, Package() {
+ // [BR2A]: PCI Express Port 2A on PC02
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [BR2B]: PCI Express Port 2B on PC02
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [BR2C]: PCI Express Port 2C on PC02
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [BR2D]: PCI Express Port 2D on PC02
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR1B, Package() {
+ // [SL05]: PCI Express Slot 5 on 2A on PC02
+ // [EPCU]: EVA PCIe Uplink
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR1C, Package() {
+ // [VSP0]: EVA Virtual Switch Port 0
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ // [VSP1]: EVA Virtual Switch Port 1
+ Package() { 0x0001FFFF, 0, 0, 19 },
+ // [VSP2]: EVA Virtual Switch Port 2
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ // [VSP3]: EVA Virtual Switch Port 3
+ Package() { 0x0003FFFF, 0, 0, 17 },
+ })
+
+ Name (AR1D, Package() {
+ // [CPM0]: EVA CPM0
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AR1E, Package() {
+ // [CPM1]: EVA CPM1
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AR1F, Package() {
+ // [CPM2]: EVA CPM2
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+ Name (AR20, Package() {
+ // [SL06]: PCI Express Slot 6 on 2B on PC02
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR21, Package() {
+ // [SL07]: PCI Express Slot 7 on 2C on PC02
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR22, Package() {
+ // [SL08]: PCI Express Slot 8 on 2D on PC02
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR23, Package() {
+ // [BR3A]: PCI Express Port 3A on PC03
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [BR3B]: PCI Express Port 3B on PC03
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [BR3C]: PCI Express Port 3C on PC03
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [BR3D]: PCI Express Port 3D on PC03
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR24, Package() {
+ // [SL09]: PCI Express Slot 9 on 3A on PC03
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR25, Package() {
+ // [SL0A]: PCI Express Slot 10 on 3B on PC03
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR26, Package() {
+ // [SL0B]: PCI Express Slot 11 on 3C on PC03
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR27, Package() {
+ // [SL0C]: PCI Express Slot 12 on 3D on PC03
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR28, Package() {
+ // [BR4A]: PCI Express Port 4A on PC04
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [BR4B]: PCI Express Port 4B on PC04
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [BR4C]: PCI Express Port 4C on PC04
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [BR4D]: PCI Express Port 4D on PC04
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR29, Package() {
+ // [SL0D]: PCI Express Slot 13 on 4A on PC04
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR2A, Package() {
+ // [SL0E]: PCI Express Slot 14 on 4B on PC04
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR2B, Package() {
+ // [SL0F]: PCI Express Slot 15 on 4C on PC04
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR2C, Package() {
+ // [SL10]: PCI Express Slot 16 on 4D on PC04
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR2D, Package() {
+ // [BR5A]: PCI Express Port 5A on PC05
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [BR5B]: PCI Express Port 5B on PC05
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [BR5C]: PCI Express Port 5C on PC05
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [BR5D]: PCI Express Port 5D on PC05
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR2E, Package() {
+ // [SL11]: PCI Express Slot 17 on 5A on PC05
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR2F, Package() {
+ // [SL12]: PCI Express Slot 18 on 5B on PC05
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR30, Package() {
+ // [SL13]: PCI Express Slot 19 on 5C on PC05
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR31, Package() {
+ // [SL14]: PCI Express Slot 20 on 5D on PC05
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR32, Package() {
+ // [UBX0]: Uncore 0 UBOX Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [UP00]: Uncore 0 Misc 2 UPI 0-7 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [UP01]: Unocre 0 Misc 1 UPI 0-7 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [M2U0]: Uncore 0 M2UPI0 Device
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [M2U1]: Uncore 0 M2UPI1 Device
+ Package() { 0x0006FFFF, 0, 0, 16 },
+ Package() { 0x0006FFFF, 1, 0, 17 },
+ Package() { 0x0006FFFF, 2, 0, 18 },
+ Package() { 0x0006FFFF, 3, 0, 19 },
+ // [M2U2]: Uncore 0 M2UPI2 Device
+ Package() { 0x0007FFFF, 0, 0, 16 },
+ Package() { 0x0007FFFF, 1, 0, 17 },
+ Package() { 0x0007FFFF, 2, 0, 18 },
+ Package() { 0x0007FFFF, 3, 0, 19 },
+ // [CSM0]: Uncore 0 CHASIS_SMBUS Devices
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [M2M0]: Uncore 0 MS2MEM_SCF_MS2MEM0 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [M2M1]: Uncore 0 MS2MEM_SCF_MS2MEM1 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [MCD0]: Uncore 0 MCDDR0 Device
+ Package() { 0x001AFFFF, 0, 0, 16 },
+ Package() { 0x001AFFFF, 1, 0, 17 },
+ Package() { 0x001AFFFF, 2, 0, 18 },
+ Package() { 0x001AFFFF, 3, 0, 19 },
+ // [MCD1]: Uncore 0 MCDDR1 Device
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ })
+
+ Name (AR33, Package() {
+ // [CHA0]: Uncore 1 GRP1_CHA0-7 Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [CHA1]: Uncore 1 GRP1_CHA8-15 Device
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // [CHA2]: Uncore 1 GRP1_CHA16-23 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [CHA3]: Uncore 1 GRP1_CHAU24-31 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [CHA4]: Uncore 1 GRP1_CHA32-33 Device
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [CHA5]: Uncore 1 GRP0_CHA0-7 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [CHA8]: Uncore 1 GRP0_CHA24-31 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [CHA9]: Uncore 1 GRP0_CHA32-33 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [CHA6]: Uncore 1 GRP0_CHA8-15 Device
+ Package() { 0x00B0FFFF, 0, 0, 16 },
+ Package() { 0x00B0FFFF, 1, 0, 17 },
+ Package() { 0x00B0FFFF, 2, 0, 18 },
+ Package() { 0x00B0FFFF, 3, 0, 19 },
+ // [CHA7]: Uncore 1 GRP0_CHA16-23 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [CA00]: Uncore 1 CHAALL0-1 Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PUC0]: Uncore 1 CHASIS_PUINT0-7 Device
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [GN30]: Uncore 1 Gen3Phy Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+#if MAX_SOCKET > 1
+ Name (AR34, Package() {
+ // [IIM1]: IIOMISC on PC06
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [CB1A]: CB3DMA on PC06
+ // [CB1E]: CB3DMA on PC06
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [CB1B]: CB3DMA on PC06
+ // [CB1F]: CB3DMA on PC06
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ // [CB1C]: CB3DMA on PC06
+ // [CB1G]: CB3DMA on PC06
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ // [CB1D]: CB3DMA on PC06
+ // [CB1H]: CB3DMA on PC06
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // NorthPeak
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ })
+
+ Name (AR35, Package() {
+ // [QR1A]: PCI Express Port 1A on PC07
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [QR1B]: PCI Express Port 1B on PC07
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [QR1C]: PCI Express Port 1C on PC07
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [QR1D]: PCI Express Port 1D on PC07
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR36, Package() {
+ // [SL16]: PCI Express Slot 22 on 1A on PC07
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR37, Package() {
+ // [SL17]: PCI Express Slot 23 on 1B on PC07
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR38, Package() {
+ // [SL18]: PCI Express Slot 24 on 1C on PC07
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR39, Package() {
+ // [SL19]: PCI Express Slot 25 on 1D on PC07
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR3A, Package() {
+ // [QR2A]: PCI Express Port 2A on PC08
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [QR2B]: PCI Express Port 2B on PC08
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [QR2C]: PCI Express Port 2C on PC08
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [QR2D]: PCI Express Port 2D on PC08
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR3B, Package() {
+ // [SL1A]: PCI Express Slot 26 on 2A on PC08
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR3C, Package() {
+ // [SL1B]: PCI Express Slot 27 on 2B on PC08
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR3D, Package() {
+ // [SL1C]: PCI Express Slot 28 on 2C on PC08
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR3E, Package() {
+ // [SL1D]: PCI Express Slot 29 on 2D on PC08
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR3F, Package() {
+ // [QR3A]: PCI Express Port 3A on PC09
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [QR3B]: PCI Express Port 3B on PC09
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [QR3C]: PCI Express Port 3C on PC09
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [QR3D]: PCI Express Port 3D on PC09
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR40, Package() {
+ // [SL1E]: PCI Express Slot 30 on 3A on PC09
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR41, Package() {
+ // [SL1F]: PCI Express Slot 31 on 3B on PC09
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR42, Package() {
+ // [SL20]: PCI Express Slot 32 on 3C on PC09
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR43, Package() {
+ // [SL21]: PCI Express Slot 33 on 3D on PC09
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR44, Package() {
+ // [QR4A]: PCI Express Port 4A on PC10
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [QR4B]: PCI Express Port 4B on PC10
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [QR4C]: PCI Express Port 4C on PC10
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [QR4D]: PCI Express Port 4D on PC10
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR45, Package() {
+ // [SL22]: PCI Express Slot 34 on 4A on PC10
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR46, Package() {
+ // [SL23]: PCI Express Slot 35 on 4B on PC10
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR47, Package() {
+ // [SL24]: PCI Express Slot 36 on 4C on PC10
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR48, Package() {
+ // [SL25]: PCI Express Slot 37 on 4D on PC10
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR49, Package() {
+ // [QR5A]: PCI Express Port 5A on PC11
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [QR5B]: PCI Express Port 5B on PC11
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [QR5C]: PCI Express Port 5C on PC11
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [QR5D]: PCI Express Port 5D on PC11
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR4A, Package() {
+ // [SL26]: PCI Express Slot 38 on 5A on PC11
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR4B, Package() {
+ // [SL27]: PCI Express Slot 39 on 5B on PC11
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR4C, Package() {
+ // [SL28]: PCI Express Slot 40 on 5C on PC11
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR4D, Package() {
+ // [SL29]: PCI Express Slot 41 on 5D on PC11
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR4E, Package() {
+ // [UBX1]: Uncore 2 UBOX Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [UP02]: Uncore 2 Misc 2 UPI 0-7 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [UP03]: Uncore 2 Misc 1 UPI 0-7 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [M2U3]: Uncore 2 M2UPI0 Device
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [M2U4]: Uncore 2 M2UPI1 Device
+ Package() { 0x0006FFFF, 0, 0, 16 },
+ Package() { 0x0006FFFF, 1, 0, 17 },
+ Package() { 0x0006FFFF, 2, 0, 18 },
+ Package() { 0x0006FFFF, 3, 0, 19 },
+ // [M2U5]: Uncore 2 M2UPI2 Device
+ Package() { 0x0007FFFF, 0, 0, 16 },
+ Package() { 0x0007FFFF, 1, 0, 17 },
+ Package() { 0x0007FFFF, 2, 0, 18 },
+ Package() { 0x0007FFFF, 3, 0, 19 },
+ // [CSM1]: Uncore 2 CHASIS_SMBUS Devices
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [M2M2]: Uncore 2 MS2MEM_SCF_MS2MEM0 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [M2M3]: Uncore 2 MS2MEM_SCF_MS2MEM1 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [MCD2]: Uncore 2 MCDDR0 Device
+ Package() { 0x001AFFFF, 0, 0, 16 },
+ Package() { 0x001AFFFF, 1, 0, 17 },
+ Package() { 0x001AFFFF, 2, 0, 18 },
+ Package() { 0x001AFFFF, 3, 0, 19 },
+ // [MCD3]: Uncore 2 MCDDR1 Device
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ })
+
+ Name (AR4F, Package() {
+ // [DHA0]: Uncore 3 GRP1_CHA0-7 Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [DHA1]: Uncore 3 GRP1_CHA8-15 Device
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // [DHA2]: Uncore 3 GRP1_CHA16-23 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [DHA3]: Uncore 3 GRP1_CHAU24-31 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [DHA4]: Uncore 3 GRP1_CHA32-33 Device
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [DHA5]: Uncore 3 GRP0_CHA0-7 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [DHA8]: Uncore 3 GRP0_CHA24-31 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [DHA9]: Uncore 3 GRP0_CHA32-33 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [DHA6]: Uncore 3 GRP0_CHA8-15 Device
+ Package() { 0x00B0FFFF, 0, 0, 16 },
+ Package() { 0x00B0FFFF, 1, 0, 17 },
+ Package() { 0x00B0FFFF, 2, 0, 18 },
+ Package() { 0x00B0FFFF, 3, 0, 19 },
+ // [DHA7]: Uncore 3 GRP0_CHA16-23 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [CA01]: Uncore 3 CHAALL0-1 Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PUC1]: Uncore 3 CHASIS_PUINT0-7 Device
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [GN31]: Uncore 3 Gen3Phy Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+#endif
+
+#if MAX_SOCKET > 2
+ Name (AR50, Package() {
+ // [IIM2]: IIOMISC on PC12
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [CB2A]: CB3DMA on PC12
+ // [CB2E]: CB3DMA on PC12
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [CB2B]: CB3DMA on PC12
+ // [CB2F]: CB3DMA on PC12
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ // [CB2C]: CB3DMA on PC12
+ // [CB2G]: CB3DMA on PC12
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ // [CB2D]: CB3DMA on PC12
+ // [CB2H]: CB3DMA on PC12
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // NorthPeak
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ })
+
+ Name (AR51, Package() {
+ // [RR1A]: PCI Express Port 1A on PC13
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [RR1B]: PCI Express Port 1B on PC13
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [RR1C]: PCI Express Port 1C on PC13
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [RR1D]: PCI Express Port 1D on PC13
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR52, Package() {
+ // [SL2B]: PCI Express Slot 43 on 1A on PC13
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR53, Package() {
+ // [SL2C]: PCI Express Slot 44 on 1B on PC13
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR54, Package() {
+ // [SL2D]: PCI Express Slot 45 on 1C on PC13
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR55, Package() {
+ // [SL2E]: PCI Express Slot 46 on 1D on PC13
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR56, Package() {
+ // [RR2A]: PCI Express Port 2A on PC14
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [RR2B]: PCI Express Port 2B on PC14
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [RR2C]: PCI Express Port 2C on PC14
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [RR2D]: PCI Express Port 2D on PC14
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR57, Package() {
+ // [SL2F]: PCI Express Slot 47 on 2A on PC14
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR58, Package() {
+ // [SL30]: PCI Express Slot 48 on 2B on PC14
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR59, Package() {
+ // [SL31]: PCI Express Slot 49 on 2C on PC14
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR5A, Package() {
+ // [SL32]: PCI Express Slot 50 on 2D on PC14
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR5B, Package() {
+ // [RR3A]: PCI Express Port 3A on PC15
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [RR3B]: PCI Express Port 3B on PC15
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [RR3C]: PCI Express Port 3C on PC15
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [RR3D]: PCI Express Port 3D on PC15
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR5C, Package() {
+ // [SL33]: PCI Express Slot 51 on 3A on PC15
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR5D, Package() {
+ // [SL34]: PCI Express Slot 52 on 3B on PC15
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR5E, Package() {
+ // [SL35]: PCI Express Slot 53 on 3C on PC15
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR5F, Package() {
+ // [SL36]: PCI Express Slot 54 on 3D on PC15
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR60, Package() {
+ // [RR4A]: PCI Express Port 4A on PC16
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [RR4B]: PCI Express Port 4B on PC16
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [RR4C]: PCI Express Port 4C on PC16
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [RR4D]: PCI Express Port 4D on PC16
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR61, Package() {
+ // [SL37]: PCI Express Slot 55 on 4A on PC16
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR62, Package() {
+ // [SL38]: PCI Express Slot 56 on 4B on PC16
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR63, Package() {
+ // [SL39]: PCI Express Slot 57 on 4C on PC16
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR64, Package() {
+ // [SL3A]: PCI Express Slot 58 on 4D on PC16
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR65, Package() {
+ // [RR5A]: PCI Express Port 5A on PC17
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [RR5B]: PCI Express Port 5B on PC17
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [RR5C]: PCI Express Port 5C on PC17
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [RR5D]: PCI Express Port 5D on PC17
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR66, Package() {
+ // [SL3B]: PCI Express Slot 59 on 5A on PC17
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR67, Package() {
+ // [SL3C]: PCI Express Slot 60 on 5B on PC17
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR68, Package() {
+ // [SL3D]: PCI Express Slot 61 on 5C on PC17
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR69, Package() {
+ // [SL3E]: PCI Express Slot 62 on 5D on PC17
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR6A, Package() {
+ // [UBX2]: Uncore 4 UBOX Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [UP04]: Uncore 4 Misc 2 UPI 0-7 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [UP05]: Uncore 4 Misc 1 UPI 0-7 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [M2U6]: Uncore 4 M2UPI Device
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [M2U7]: Uncore 4 M2UPI Device
+ Package() { 0x0006FFFF, 0, 0, 16 },
+ Package() { 0x0006FFFF, 1, 0, 17 },
+ Package() { 0x0006FFFF, 2, 0, 18 },
+ Package() { 0x0006FFFF, 3, 0, 19 },
+ // [M2U8]: Uncore 4 M2UPI Device
+ Package() { 0x0007FFFF, 0, 0, 16 },
+ Package() { 0x0007FFFF, 1, 0, 17 },
+ Package() { 0x0007FFFF, 2, 0, 18 },
+ Package() { 0x0007FFFF, 3, 0, 19 },
+ // [CSM2]: Uncore 4 CHASIS_SMBUS Devices
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [M2M4]: Uncore 4 MS2MEM_SCF_MS2MEM0 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [M2M5]: Uncore 4 MS2MEM_SCF_MS2MEM1 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [MCD4]: Uncore 4 MCDDR0 Device
+ Package() { 0x001AFFFF, 0, 0, 16 },
+ Package() { 0x001AFFFF, 1, 0, 17 },
+ Package() { 0x001AFFFF, 2, 0, 18 },
+ Package() { 0x001AFFFF, 3, 0, 19 },
+ // [MCD5]: Uncore 4 MCDDR1 Device
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ })
+
+ Name (AR6B, Package() {
+ // [EHA0]: Uncore 5 GRP1_CHA0-7 Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [EHA1]: Uncore 5 GRP1_CHA8-15 Device
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // [EHA2]: Uncore 5 GRP1_CHA16-23 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [EHA3]: Uncore 5 GRP1_CHAU24-31 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [EHA4]: Uncore 5 GRP1_CHA32-33 Device
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [EHA5]: Uncore 5 GRP0_CHA0-7 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [EHA8]: Uncore 5 GRP0_CHA24-31 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [EHA9]: Uncore 5 GRP0_CHA32-33 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [EHA6]: Uncore 5 GRP0_CHA8-15 Device
+ Package() { 0x00B0FFFF, 0, 0, 16 },
+ Package() { 0x00B0FFFF, 1, 0, 17 },
+ Package() { 0x00B0FFFF, 2, 0, 18 },
+ Package() { 0x00B0FFFF, 3, 0, 19 },
+ // [EHA7]: Uncore 5 GRP0_CHA16-23 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [CA02]: Uncore 5 CHAALL0-1 Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PUC2]: Uncore 5 CHASIS_PUINT0-7 Device
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [GN32]: Uncore 5 Gen3Phy Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+#endif
+
+#if MAX_SOCKET > 3
+ Name (AR6C, Package() {
+ // [IIM3]: IIOMISC on PC18
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [CB3A]: CB3DMA on PC18
+ // [CB3E]: CB3DMA on PC18
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ // [CB3B]: CB3DMA on PC18
+ // [CB3F]: CB3DMA on PC18
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ // [CB3C]: CB3DMA on PC18
+ // [CB3G]: CB3DMA on PC18
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ // [CB3D]: CB3DMA on PC18
+ // [CB3H]: CB3DMA on PC18
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // NorthPeak
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ })
+
+ Name (AR6D, Package() {
+ // [SR1A]: PCI Express Port 1A on PC19
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [SR1B]: PCI Express Port 1B on PC19
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [SR1C]: PCI Express Port 1C on PC19
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [SR1D]: PCI Express Port 1D on PC19
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR6E, Package() {
+ // [SL40]: PCI Express Slot 64 on 1A on PC19
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR6F, Package() {
+ // [SL41]: PCI Express Slot 65 on 1B on PC19
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR70, Package() {
+ // [SL42]: PCI Express Slot 66 on 1C on PC19
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR71, Package() {
+ // [SL43]: PCI Express Slot 67 on 1D on PC19
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR72, Package() {
+ // [SR2A]: PCI Express Port 2A on PC20
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [SR2B]: PCI Express Port 2B on PC20
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [SR2C]: PCI Express Port 2C on PC20
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [SR2D]: PCI Express Port 2D on PC20
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR73, Package() {
+ // [SL44]: PCI Express Slot 68 on 2A on PC20
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR74, Package() {
+ // [SL45]: PCI Express Slot 69 on 2B on PC20
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR75, Package() {
+ // [SL46]: PCI Express Slot 70 on 2C on PC20
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR76, Package() {
+ // [SL47]: PCI Express Slot 71 on 2D on PC20
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR77, Package() {
+ // [SR3A]: PCI Express Port 3A on PC21
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [SR3B]: PCI Express Port 3B on PC21
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [SR3C]: PCI Express Port 3C on PC21
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [SR3D]: PCI Express Port 3D on PC21
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR78, Package() {
+ // [SL48]: PCI Express Slot 72 on 3A on PC21
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR79, Package() {
+ // [SL49]: PCI Express Slot 73 on 3B on PC21
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR7A, Package() {
+ // [SL4A]: PCI Express Slot 74 on 3C on PC21
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR7B, Package() {
+ // [SL4B]: PCI Express Slot 75 on 3D on PC21
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR7C, Package() {
+ // [SR4A]: PCI Express Port 4A on PC22
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [SR4B]: PCI Express Port 4B on PC22
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [SR4C]: PCI Express Port 4C on PC22
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [SR4D]: PCI Express Port 4D on PC22
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR7D, Package() {
+ // [SL4C]: PCI Express Slot 76 on 4A on PC22
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR7E, Package() {
+ // [SL4D]: PCI Express Slot 77 on 4B on PC22
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR7F, Package() {
+ // [SL4D]: PCI Express Slot 78 on 4C on PC22
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR80, Package() {
+ // [SL4E]: PCI Express Slot 79 on 4D on PC22
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR81, Package() {
+ // [SR5A]: PCI Express Port 5A on PC23
+ Package() { 0x0002FFFF, 0, 0, 18 },
+ Package() { 0x0002FFFF, 1, 0, 19 },
+ Package() { 0x0002FFFF, 2, 0, 16 },
+ Package() { 0x0002FFFF, 3, 0, 17 },
+ // [SR5B]: PCI Express Port 5B on PC23
+ Package() { 0x0003FFFF, 0, 0, 19 },
+ Package() { 0x0003FFFF, 1, 0, 16 },
+ Package() { 0x0003FFFF, 2, 0, 17 },
+ Package() { 0x0003FFFF, 3, 0, 18 },
+ // [SR5C]: PCI Express Port 5C on PC23
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [SR5D]: PCI Express Port 5D on PC23
+ Package() { 0x0005FFFF, 0, 0, 17 },
+ Package() { 0x0005FFFF, 1, 0, 18 },
+ Package() { 0x0005FFFF, 2, 0, 19 },
+ Package() { 0x0005FFFF, 3, 0, 16 },
+ })
+
+ Name (AR82, Package() {
+ // [SL4F]: PCI Express Slot 80 on 5A on PC23
+ Package() { 0x0000FFFF, 0, 0, 18 },
+ Package() { 0x0000FFFF, 1, 0, 19 },
+ Package() { 0x0000FFFF, 2, 0, 16 },
+ Package() { 0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name (AR83, Package() {
+ // [SL50]: PCI Express Slot 81 on 5B on PC23
+ Package() { 0x0000FFFF, 0, 0, 19 },
+ Package() { 0x0000FFFF, 1, 0, 16 },
+ Package() { 0x0000FFFF, 2, 0, 17 },
+ Package() { 0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name (AR84, Package() {
+ // [SL51]: PCI Express Slot 82 on 5C on PC23
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name (AR85, Package() {
+ // [SL52]: PCI Express Slot 83 on 5D on PC23
+ Package() { 0x0000FFFF, 0, 0, 17 },
+ Package() { 0x0000FFFF, 1, 0, 18 },
+ Package() { 0x0000FFFF, 2, 0, 19 },
+ Package() { 0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name (AR86, Package() {
+ // [UBX3]: Uncore 6 UBOX Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [UP06]: Uncore 6 Misc 2 UPI 0-7 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [UP07]: Uncore 6 Misc 1 UPI 0-7 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [M2U9]: Uncore 6 M2UPI0 Device
+ Package() { 0x0005FFFF, 0, 0, 16 },
+ Package() { 0x0005FFFF, 1, 0, 17 },
+ Package() { 0x0005FFFF, 2, 0, 18 },
+ Package() { 0x0005FFFF, 3, 0, 19 },
+ // [M2UA]: Uncore 6 M2UPI1 Device
+ Package() { 0x0006FFFF, 0, 0, 16 },
+ Package() { 0x0006FFFF, 1, 0, 17 },
+ Package() { 0x0006FFFF, 2, 0, 18 },
+ Package() { 0x0006FFFF, 3, 0, 19 },
+ // [M2UB]: Uncore 6 M2UPI2 Device
+ Package() { 0x0007FFFF, 0, 0, 16 },
+ Package() { 0x0007FFFF, 1, 0, 17 },
+ Package() { 0x0007FFFF, 2, 0, 18 },
+ Package() { 0x0007FFFF, 3, 0, 19 },
+ // [CSM3]: Uncore 6 CHASIS_SMBUS Devices
+ Package() { 0x000BFFFF, 0, 0, 16 },
+ Package() { 0x000BFFFF, 1, 0, 17 },
+ Package() { 0x000BFFFF, 2, 0, 18 },
+ Package() { 0x000BFFFF, 3, 0, 19 },
+ // [M2M6]: Uncore 6 MS2MEM_SCF_MS2MEM0 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [M2M7]: Uncore 6 MS2MEM_SCF_MS2MEM1 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [MCD6]: Uncore 6 MCDDR0 Device
+ Package() { 0x001AFFFF, 0, 0, 16 },
+ Package() { 0x001AFFFF, 1, 0, 17 },
+ Package() { 0x001AFFFF, 2, 0, 18 },
+ Package() { 0x001AFFFF, 3, 0, 19 },
+ // [MCD7]: Uncore 6 MCDDR1 Device
+ Package() { 0x001BFFFF, 0, 0, 16 },
+ Package() { 0x001BFFFF, 1, 0, 17 },
+ Package() { 0x001BFFFF, 2, 0, 18 },
+ Package() { 0x001BFFFF, 3, 0, 19 },
+ })
+
+ Name (AR87, Package() {
+ // [FHA0]: Uncore 7 GRP1_CHA0-7 Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ // [FHA1]: Uncore 7 GRP1_CHA8-15 Device
+ Package() { 0x0001FFFF, 0, 0, 16 },
+ Package() { 0x0001FFFF, 1, 0, 17 },
+ Package() { 0x0001FFFF, 2, 0, 18 },
+ Package() { 0x0001FFFF, 3, 0, 19 },
+ // [FHA2]: Uncore 7 GRP1_CHA16-23 Device
+ Package() { 0x0002FFFF, 0, 0, 16 },
+ Package() { 0x0002FFFF, 1, 0, 17 },
+ Package() { 0x0002FFFF, 2, 0, 18 },
+ Package() { 0x0002FFFF, 3, 0, 19 },
+ // [FHA3]: Uncore 7 GRP1_CHAU24-31 Device
+ Package() { 0x0003FFFF, 0, 0, 16 },
+ Package() { 0x0003FFFF, 1, 0, 17 },
+ Package() { 0x0003FFFF, 2, 0, 18 },
+ Package() { 0x0003FFFF, 3, 0, 19 },
+ // [FHA4]: Uncore 7 GRP1_CHA32-33 Device
+ Package() { 0x0004FFFF, 0, 0, 16 },
+ Package() { 0x0004FFFF, 1, 0, 17 },
+ Package() { 0x0004FFFF, 2, 0, 18 },
+ Package() { 0x0004FFFF, 3, 0, 19 },
+ // [FHA5]: Uncore 7 GRP0_CHA0-7 Device
+ Package() { 0x000AFFFF, 0, 0, 16 },
+ Package() { 0x000AFFFF, 1, 0, 17 },
+ Package() { 0x000AFFFF, 2, 0, 18 },
+ Package() { 0x000AFFFF, 3, 0, 19 },
+ // [FHA8]: Uncore 7 GRP0_CHA24-31 Device
+ Package() { 0x000DFFFF, 0, 0, 16 },
+ Package() { 0x000DFFFF, 1, 0, 17 },
+ Package() { 0x000DFFFF, 2, 0, 18 },
+ Package() { 0x000DFFFF, 3, 0, 19 },
+ // [FHA9]: Uncore 7 GRP0_CHA32-33 Device
+ Package() { 0x000EFFFF, 0, 0, 16 },
+ Package() { 0x000EFFFF, 1, 0, 17 },
+ Package() { 0x000EFFFF, 2, 0, 18 },
+ Package() { 0x000EFFFF, 3, 0, 19 },
+ // [FHA6]: Uncore 7 GRP0_CHA8-15 Device
+ Package() { 0x00B0FFFF, 0, 0, 16 },
+ Package() { 0x00B0FFFF, 1, 0, 17 },
+ Package() { 0x00B0FFFF, 2, 0, 18 },
+ Package() { 0x00B0FFFF, 3, 0, 19 },
+ // [FHA7]: Uncore 7 GRP0_CHA16-23 Device
+ Package() { 0x000CFFFF, 0, 0, 16 },
+ Package() { 0x000CFFFF, 1, 0, 17 },
+ Package() { 0x000CFFFF, 2, 0, 18 },
+ Package() { 0x000CFFFF, 3, 0, 19 },
+ // [CA03]: Uncore 7 CHAALL0-1 Device
+ Package() { 0x001DFFFF, 0, 0, 16 },
+ Package() { 0x001DFFFF, 1, 0, 17 },
+ Package() { 0x001DFFFF, 2, 0, 18 },
+ Package() { 0x001DFFFF, 3, 0, 19 },
+ // [PUC3]: Uncore 7 CHASIS_PUINT0-7 Device
+ Package() { 0x001EFFFF, 0, 0, 16 },
+ Package() { 0x001EFFFF, 1, 0, 17 },
+ Package() { 0x001EFFFF, 2, 0, 18 },
+ Package() { 0x001EFFFF, 3, 0, 19 },
+ // [GN33]: Uncore 7 Gen3Phy Device
+ Package() { 0x001FFFFF, 0, 0, 16 },
+ Package() { 0x001FFFFF, 1, 0, 17 },
+ Package() { 0x001FFFFF, 2, 0, 18 },
+ Package() { 0x001FFFFF, 3, 0, 19 },
+ })
+#endif
+ Name (AR88, Package() {
+ // [FPG0]: FPGA Device
+ Package() { 0x0000FFFF, 0, 0, 16 },
+ })
+
+#if MAX_SOCKET > 1
+ Name (AR89, Package() {
+ // [FPG1]: FPGA Device
+ Package() { 0x0000FFFF, 1, 0, 17 },
+ })
+#endif
+
+#if MAX_SOCKET > 2
+ Name (AR8A, Package() {
+ // [FPG2]: FPGA Device
+ Package() { 0x0000FFFF, 2, 0, 18 },
+ })
+#endif
+
+#if MAX_SOCKET > 3
+ Name (AR8B, Package() {
+ // [FPG3]: FPGA Device
+ Package() { 0x0000FFFF, 3, 0, 19 },
+ })
+#endif
+ //
+ // Socket 0 Root bridge (Stack 0)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 0
+ Device (PC00) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x00)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR00)
+ }
+
+ #include "PC0010nm.asi"
+
+ // IIOMISC on PC00
+ Device (IIM0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0A) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0B) {
+ Name (_ADR, 0x00010001)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0C) {
+ Name (_ADR, 0x00010002)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0D) {
+ Name (_ADR, 0x00010003)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0E) {
+ Name (_ADR, 0x00010004)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0F) {
+ Name (_ADR, 0x00010005)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0G) {
+ Name (_ADR, 0x00010006)
+ }
+
+ // CB3DMA on PC00
+ Device (CB0H) {
+ Name (_ADR, 0x00010007)
+ }
+
+ // MSM on PC00
+ Device (MSM1) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // PMON MSM on PC00
+ Device (PMON) {
+ Name (_ADR, 0x00020001)
+ }
+
+ // NorthPeak on PC00
+ Device (NRPK) {
+ Name (_ADR, 0x00020004)
+ }
+
+ // Legacy PCI Express Port 0 on PC00
+ Device (DMI0) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // IE HECI #1
+ Device (IHC1) {
+ Name (_ADR, 0x00100000)
+ }
+
+ // IE HECI #2
+ Device (IHC2) {
+ Name (_ADR, 0x00100001)
+ }
+
+ // IE IDE-Redirection (IDE-R)
+ Device (IIDR) {
+ Name (_ADR, 0x00100002)
+ }
+
+ // IE Keyboard and Text (KT) Redirection
+ Device (IMKT) {
+ Name (_ADR, 0x00100003)
+ }
+
+ // IE HECI #3
+ Device (IHC3) {
+ Name (_ADR, 0x00100004)
+ }
+
+ // MROM 0 function function
+ Device (MRO0) {
+ Name (_ADR, 0x00110000)
+ }
+
+ // MROM 1 function function
+ Device (MRO1) {
+ Name (_ADR, 0x00110001)
+ }
+
+ // sSATA Host controller on PCH
+ Device (SAT2) {
+ Name (_ADR, 0x00110005)
+ }
+
+ // xHCI controller 1 on PCH
+ Device (XHCI) {
+ Name (_ADR, 0x00140000)
+ }
+
+ // Thermal Subsystem on PCH
+ Device (TERM) {
+ Name (_ADR, 0x00140002)
+ }
+
+ // ME HECI #1 on PCH
+ Device (HEC1) {
+ Name (_ADR, 0x00160000)
+ }
+
+ // ME HECI #2 on PCH
+ Device (HEC2) {
+ Name (_ADR, 0x00160001)
+ }
+
+ // ME IDE redirect on PCH
+ Device (IDER) {
+ Name (_ADR, 0x00160002)
+ }
+
+ // MEKT on PCH
+ Device (MEKT) {
+ Name (_ADR, 0x00160003)
+ }
+
+ // ME HECI #3 on PCH
+ Device (HEC3) {
+ Name (_ADR, 0x00160004)
+ }
+
+ // SATA controller 1 on PCH
+ Device (SAT1) {
+ Name (_ADR, 0x00170000)
+ }
+
+ // PCIE PCH Root Port #17
+ Device (RP17) {
+ #include "RP17_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR01)
+ }
+
+ // PCIE PCH Slot #17
+ Device (SLTH) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #18
+ Device (RP18) {
+ #include "RP18_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR02)
+ }
+
+ // PCIE PCH Slot #18
+ Device (SLTI) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #19
+ Device (RP19) {
+ #include "RP19_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR03)
+ }
+
+ // PCIE PCH Slot #19
+ Device (SLTJ) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #20
+ Device (RP20) {
+ #include "RP20_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR04)
+ }
+
+ // PCIE PCH Slot #20
+ Device (SLTK) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #1
+ Device (RP01) {
+ #include "RP01_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR05)
+ }
+ }
+
+ // PCIE PCH Root Port #2
+ Device (RP02) {
+ #include "RP02_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR06)
+ }
+ }
+
+ // PCIE PCH Root Port #3
+ Device (RP03) {
+ #include "RP03_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR07)
+ }
+ }
+
+ // PCIE PCH Root Port #4
+ Device (RP04) {
+ #include "RP04_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR08)
+ }
+ }
+
+ // PCIE PCH Root Port #5
+ Device (RP05) {
+ #include "RP05_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR09)
+ }
+ }
+
+ // PCIE PCH Root Port #6
+ Device (RP06) {
+ #include "RP06_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0A)
+ }
+ }
+
+ // PCIE PCH Root Port #7
+ Device (RP07) {
+ #include "RP07_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0B)
+ }
+ }
+
+ // PCIE PCH Root Port #8
+ Device (RP08) {
+ #include "RP08_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0C)
+ }
+ }
+
+ // PCIE PCH Root Port #9
+ Device (RP09) {
+ #include "RP09_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0D)
+ }
+
+ // PCIE PCH Slot #9
+ Device (SLT9) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #10
+ Device (RP10) {
+ #include "RP10_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0E)
+ }
+
+ // PCIE PCH Slot #10
+ Device (SLTA) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #11
+ Device (RP11) {
+ #include "RP11_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR0F)
+ }
+
+ // PCIE PCH Slot #11
+ Device (SLTB) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #12
+ Device (RP12) {
+ #include "RP12_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR10)
+ }
+
+ // PCIE PCH Slot #12
+ Device (SLTC) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #13
+ Device (RP13) {
+ #include "RP13_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR11)
+ }
+
+ // PCIE PCH Slot #13
+ Device (SLTD) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #14
+ Device (RP14) {
+ #include "RP14_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR12)
+ }
+
+ // PCIE PCH Slot #14
+ Device (SLTE) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #15
+ Device (RP15) {
+ #include "RP15_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR13)
+ }
+
+ // PCIE PCH Slot #15
+ Device (SLTF) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // PCIE PCH Root Port #16
+ Device (RP16) {
+ #include "RP16_ADR.asl"
+ Method (_PRT, 0) {
+
+ Return (AR14)
+ }
+
+ // PCIE PCH Slot #16
+ Device (SLTG) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // ISA Bridge on PCH
+ Device (LPC0) {
+ Name (_ADR, 0x001F0000)
+
+ #include "Mother.asi"
+ }
+
+ // P2SB
+ Device (P2SB) {
+ Name (_ADR, 0x001F0001)
+ }
+
+ // Power Management Controller on PCH
+ Device (PMC1) {
+ Name (_ADR, 0x001F0002)
+ }
+
+ // HD Audio Subsystem Controller on PCH
+ Device (CAVS) {
+ Name (_ADR, 0x001F0003)
+ }
+
+ // SMBus controller on PCH
+ Device (SMBS) {
+ Name (_ADR, 0x001F0004)
+ }
+
+ // SPI controller on PCH
+ Device (SPIC) {
+ Name (_ADR, 0x001F0005)
+ }
+
+ // GbE Controller on PCH
+ Device (GBE1) {
+ Name (_ADR, 0x001F0006)
+ }
+
+ // Intel Trace Hub on PCH
+ Device (TRHB) {
+ Name (_ADR, 0x001F0007)
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 1)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 1
+ Device (PC01) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x01)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR15)
+ }
+
+ #include "IioRootBridge.asi"
+
+ // PCI Express Port 1A on PC01
+ Device (BR1A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR16)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1B on PC01
+ Device (BR1B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR17)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1C on PC01
+ Device (BR1C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR18)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 1D on PC01
+ Device (BR1D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR19)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 2)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 2
+ Device (PC02) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x02)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR1A)
+ }
+
+ #include "IioRootBridge.asi"
+
+ // PCI Express Port 2A on PC02
+ Device (BR2A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR1B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+
+ // EVA PCIe Uplink
+ Device (EPCU) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR1C)
+ }
+
+ // EVA Virtual Switch Port 0
+ Device (VSP0) {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR1D)
+ }
+
+ // EVA CPM0
+ Device (CPM0) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 1
+ Device (VSP1) {
+ Name (_ADR, 0x00010000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR1E)
+ }
+
+ // EVA CPM1
+ Device (CPM1) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 2
+ Device (VSP2) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR1F)
+ }
+
+ // EVA CPM2
+ Device (CPM2) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+
+ // EVA Virtual Switch Port 3
+ Device (VSP3) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x0B, 0x00})
+ }
+ }
+ }
+ }
+
+ // PCI Express Port 2B on PC02
+ Device (BR2B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR20)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 2C on PC02
+ Device (BR2C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR21)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 2D on PC02
+ Device (BR2D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR22)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 3)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 3
+ Device (PC03) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x03)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR23)
+ }
+
+ #include "IioRootBridge.asi"
+
+ // PCI Express Port 3A on PC03
+ Device (BR3A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR24)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3B on PC03
+ Device (BR3B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR25)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3C on PC03
+ Device (BR3C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR26)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 3D on PC03
+ Device (BR3D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR27)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 4)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 4
+ Device (PC04) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x04)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR28)
+ }
+
+ #include "IioRootBridge.asi"
+
+ // PCI Express Port 4A on PC04
+ Device (BR4A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR29)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ }
+
+ // PCI Express Port 4B on PC04
+ Device (BR4B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR2A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 4C on PC04
+ Device (BR4C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR2B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 4D on PC04
+ Device (BR4D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR2C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+ }
+
+ // Socket 0 Root bridge (Stack 5)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 5
+ Device (PC05) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x05)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR2D)
+ }
+
+ #include "IioRootBridge.asi"
+
+ // PCI Express Port 5A on PC05
+ Device (BR5A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR2E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 5B on PC05
+ Device (BR5B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR2F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 5C on PC05
+ Device (BR5C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR30)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+
+ // PCI Express Port 5D on PC05
+ Device (BR5D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR31)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieNonHpDev.asi"
+ }
+ }
+
+ // Socket 0 Uncore 0
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 6
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x32)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR32)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 0 UBOX Device
+ Device (UBX0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 0 Misc 2 UPI 0-7 Device
+ Device (UP00) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Unocre 0 Misc 1 UPI 0-7 Device
+ Device (UP01) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 0 M2UPI0 Device
+ Device (M2U0) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 0 M2UPI1 Device
+ Device (M2U1) {
+ Name (_ADR, 0x00060000)
+ }
+
+ // Uncore 0 M2UPI2 Device
+ Device (M2U2) {
+ Name (_ADR, 0x00070000)
+ }
+
+ // Uncore 0 CHASIS_SMBUS Devices
+ Device (CSM0) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 0 MS2MEM_SCF_MS2MEM0 Device
+ Device (M2M0) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 0 MS2MEM_SCF_MS2MEM1 Device
+ Device (M2M1) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 0 MCDDR0 Device
+ Device (MCD0) {
+ Name (_ADR, 0x001A0000)
+ }
+
+ // Uncore 0 MCDDR1 Device
+ Device (MCD1) {
+ Name (_ADR, 0x001B0000)
+ }
+ }
+
+ // Socket 0 Uncore 1
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 0
+#define STACK 7
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x33)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR33)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 1 GRP1_CHA0-7 Device
+ Device (CHA0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 1 GRP1_CHA8-15 Device
+ Device (CHA1) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // Uncore 1 GRP1_CHA16-23 Device
+ Device (CHA2) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 1 GRP1_CHAU24-31 Device
+ Device (CHA3) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 1 GRP1_CHA32-33 Device
+ Device (CHA4) {
+ Name (_ADR, 0x00040000)
+ }
+
+ // Uncore 1 GRP0_CHA0-7 Device
+ Device (CHA5) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 1 GRP0_CHA24-31 Device
+ Device (CHA8) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 1 GRP0_CHA32-33 Device
+ Device (CHA9) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 1 GRP0_CHA8-15 Device
+ Device (CHA6) {
+ Name (_ADR, 0x00B00000)
+ }
+
+ // Uncore 1 GRP0_CHA16-23 Device
+ Device (CHA7) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 1 CHAALL0-1 Device
+ Device (CA00) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 1 CHASIS_PUINT0-7 Device
+ Device (PUC0) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 1 Gen3Phy Device
+ Device (GN30) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+
+#if MAX_SOCKET > 1
+ //
+ // Socket 1 Root bridge (Stack 0)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 0
+ Device (PC06) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x06)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR34)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // IIOMISC on PC06
+ Device (IIM1) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1A) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1B) {
+ Name (_ADR, 0x00010001)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1C) {
+ Name (_ADR, 0x00010002)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1D) {
+ Name (_ADR, 0x00010003)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1E) {
+ Name (_ADR, 0x00010004)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1F) {
+ Name (_ADR, 0x00010005)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1G) {
+ Name (_ADR, 0x00010006)
+ }
+
+ // CB3DMA on PC06
+ Device (CB1H) {
+ Name (_ADR, 0x00010007)
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 1)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 1
+ Device (PC07) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x07)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR35)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 1A on PC07
+ Device (QR1A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR36)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 1B on PC07
+ Device (QR1B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR37)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 1C on PC07
+ Device (QR1C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR38)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 1D on PC07
+ Device (QR1D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR39)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 2)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 2
+ Device (PC08) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x08)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR3A)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 2A on PC08
+ Device (QR2A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR3B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 2B on PC08
+ Device (QR2B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR3C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 2C on PC08
+ Device (QR2C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR3D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 2D on PC08
+ Device (QR2D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR3E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 3)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 3
+ Device (PC09) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x09)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR3F)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 3A on PC09
+ Device (QR3A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR40)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 3B on PC09
+ Device (QR3B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR41)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 3C on PC09
+ Device (QR3C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR42)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 3D on PC09
+ Device (QR3D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR43)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 4)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 4
+ Device (PC10) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0A)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR44)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 4A on PC10
+ Device (QR4A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR45)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 4B on PC10
+ Device (QR4B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR46)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 4C on PC10
+ Device (QR4C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR47)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 4D on PC10
+ Device (QR4D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR48)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+ }
+
+ // Socket 1 Root bridge (Stack 5)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 5
+ Device (PC11) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0B)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR49)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck1Ejd.asi"
+
+ // PCI Express Port 5A on PC11
+ Device (QR5A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR4A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 5B on PC11
+ Device (QR5B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR4B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 5C on PC11
+ Device (QR5C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR4C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+
+ // PCI Express Port 5D on PC11
+ Device (QR5D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR4D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC0610nmEjd.asi"
+ }
+ }
+
+ // Socket 1 Uncore 0
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 6
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x34)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR4E)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 2 UBOX Device
+ Device (UBX1) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 2 Misc 2 UPI 0-7 Device
+ Device (UP02) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 2 Misc 1 UPI 0-7 Device
+ Device (UP03) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 2 M2UPI0 Device
+ Device (M2U3) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 2 M2UPI1 Device
+ Device (M2U4) {
+ Name (_ADR, 0x00060000)
+ }
+
+ // Uncore 2 M2UPI2 Device
+ Device (M2U5) {
+ Name (_ADR, 0x00070000)
+ }
+
+ // Uncore 2 CHASIS_SMBUS Devices
+ Device (CSM1) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 2 MS2MEM_SCF_MS2MEM0 Device
+ Device (M2M2) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 2 MS2MEM_SCF_MS2MEM1 Device
+ Device (M2M3) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 2 MCDDR0 Device
+ Device (MCD2) {
+ Name (_ADR, 0x001A0000)
+ }
+
+ // Uncore 2 MCDDR1 Device
+ Device (MCD3) {
+ Name (_ADR, 0x001B0000)
+ }
+ }
+
+ // Socket 1 Uncore 1
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 1
+#define STACK 7
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x35)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR4F)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 3 GRP1_CHA0-7 Device
+ Device (DHA0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 3 GRP1_CHA8-15 Device
+ Device (DHA1) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // Uncore 3 GRP1_CHA16-23 Device
+ Device (DHA2) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 3 GRP1_CHAU24-31 Device
+ Device (DHA3) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 3 GRP1_CHA32-33 Device
+ Device (DHA4) {
+ Name (_ADR, 0x00040000)
+ }
+
+ // Uncore 3 GRP0_CHA0-7 Device
+ Device (DHA5) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 3 GRP0_CHA24-31 Device
+ Device (DHA8) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 3 GRP0_CHA32-33 Device
+ Device (DHA9) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 3 GRP0_CHA8-15 Device
+ Device (DHA6) {
+ Name (_ADR, 0x00B00000)
+ }
+
+ // Uncore 3 GRP0_CHA16-23 Device
+ Device (DHA7) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 3 CHAALL0-1 Device
+ Device (CA01) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 3 CHASIS_PUINT0-7 Device
+ Device (PUC1) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 3 Gen3Phy Device
+ Device (GN31) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+#endif
+
+#if MAX_SOCKET > 2
+ // Socket 2 Root bridge (Stack 0)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 0
+ Device (PC12) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0C)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR50)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // IIOMISC on PC12
+ Device (IIM2) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2A) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2B) {
+ Name (_ADR, 0x00010001)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2C) {
+ Name (_ADR, 0x00010002)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2D) {
+ Name (_ADR, 0x00010003)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2E) {
+ Name (_ADR, 0x00010004)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2F) {
+ Name (_ADR, 0x00010005)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2G) {
+ Name (_ADR, 0x00010006)
+ }
+
+ // CB3DMA on PC12
+ Device (CB2H) {
+ Name (_ADR, 0x00010007)
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 1)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 1
+ Device (PC13) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0D)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR51)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 1A on PC13
+ Device (RR1A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR52)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 1B on PC13
+ Device (RR1B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR53)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 1C on PC13
+ Device (RR1C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR54)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 1D on PC13
+ Device (RR1D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR55)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 2)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 2
+ Device (PC14) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0E)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR56)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 2A on PC14
+ Device (RR2A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR57)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 2B on PC14
+ Device (RR2B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR58)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 2C on PC14
+ Device (RR2C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR59)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 2D on PC14
+ Device (RR2D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR5A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 3)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 3
+ Device (PC15) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x0F)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR5B)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 3A on PC15
+ Device (RR3A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR5C)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 3B on PC15
+ Device (RR3B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR5D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 3C on PC15
+ Device (RR3C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR5E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 3D on PC15
+ Device (RR3D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR5F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 4)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 4
+ Device (PC16) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x10)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR60)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 4A on PC16
+ Device (RR4A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR61)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 4B on PC16
+ Device (RR4B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR62)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 4C on PC16
+ Device (RR4C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR63)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 4D on PC16
+ Device (RR4D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR64)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+ }
+
+ // Socket 2 Root bridge (Stack 5)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 5
+ Device (PC17) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x11)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR65)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck2Ejd.asi"
+
+ // PCI Express Port 5A on PC17
+ Device (RR5A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR66)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 5B on PC17
+ Device (RR5B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR67)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 5C on PC17
+ Device (RR5C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR68)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+
+ // PCI Express Port 5D on PC17
+ Device (RR5D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR69)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1210nmEjd.asi"
+ }
+ }
+
+ // Socket 2 Uncore 0
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 6
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x36)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR6A)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 4 UBOX Device
+ Device (UBX2) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 4 Misc 2 UPI 0-7 Device
+ Device (UP04) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 4 Misc 1 UPI 0-7 Device
+ Device (UP05) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 4 M2UPI Device
+ Device (M2U6) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 4 M2UPI Device
+ Device (M2U7) {
+ Name (_ADR, 0x00060000)
+ }
+
+ // Uncore 4 M2UPI Device
+ Device (M2U8) {
+ Name (_ADR, 0x00070000)
+ }
+
+ // Uncore 4 CHASIS_SMBUS Devices
+ Device (CSM2) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 4 MS2MEM_SCF_MS2MEM0 Device
+ Device (M2M4) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 4 MS2MEM_SCF_MS2MEM1 Device
+ Device (M2M5) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 4 MCDDR0 Device
+ Device (MCD4) {
+ Name (_ADR, 0x001A0000)
+ }
+
+ // Uncore 4 MCDDR1 Device
+ Device (MCD5) {
+ Name (_ADR, 0x001B0000)
+ }
+ }
+
+ // Socket 2 Uncore 1
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 2
+#define STACK 7
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x37)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR6B)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 5 GRP1_CHA0-7 Device
+ Device (EHA0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 5 GRP1_CHA8-15 Device
+ Device (EHA1) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // Uncore 5 GRP1_CHA16-23 Device
+ Device (EHA2) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 5 GRP1_CHAU24-31 Device
+ Device (EHA3) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 5 GRP1_CHA32-33 Device
+ Device (EHA4) {
+ Name (_ADR, 0x00040000)
+ }
+
+ // Uncore 5 GRP0_CHA0-7 Device
+ Device (EHA5) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 5 GRP0_CHA24-31 Device
+ Device (EHA8) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 5 GRP0_CHA32-33 Device
+ Device (EHA9) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 5 GRP0_CHA8-15 Device
+ Device (EHA6) {
+ Name (_ADR, 0x00B00000)
+ }
+
+ // Uncore 5 GRP0_CHA16-23 Device
+ Device (EHA7) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 5 CHAALL0-1 Device
+ Device (CA02) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 5 CHASIS_PUINT0-7 Device
+ Device (PUC2) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 5 Gen3Phy Device
+ Device (GN32) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+#endif
+
+#if MAX_SOCKET > 3
+ // Socket 3 Root bridge (Stack 0)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 0
+ Device (PC18) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x12)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR6C)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // IIOMISC on PC18
+ Device (IIM3) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3A) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3B) {
+ Name (_ADR, 0x00010001)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3C) {
+ Name (_ADR, 0x00010002)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3D) {
+ Name (_ADR, 0x00010003)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3E) {
+ Name (_ADR, 0x00010004)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3F) {
+ Name (_ADR, 0x00010005)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3G) {
+ Name (_ADR, 0x00010006)
+ }
+
+ // CB3DMA on PC18
+ Device (CB3H) {
+ Name (_ADR, 0x00010007)
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 1)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 1
+ Device (PC19) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x13)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR6D)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 1A on PC19
+ Device (SR1A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR6E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 1B on PC19
+ Device (SR1B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR6F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 1C on PC19
+ Device (SR1C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR70)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 1D on PC19
+ Device (SR1D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR71)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 2)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 2
+ Device (PC20) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x14)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR72)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 2A on PC20
+ Device (SR2A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR73)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 2B on PC20
+ Device (SR2B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR74)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 2C on PC20
+ Device (SR2C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR75)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 2D on PC20
+ Device (SR2D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR76)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 3)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 3
+ Device (PC21) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x15)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR77)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 3A on PC21
+ Device (SR3A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR78)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 3B on PC21
+ Device (SR3B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR79)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 3C on PC21
+ Device (SR3C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR7A)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 3D on PC21
+ Device (SR3D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR7B)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 4)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 4
+ Device (PC22) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x16)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR7C)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 4A on PC22
+ Device (SR4A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR7D)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 4B on PC22
+ Device (SR4B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR7E)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 4C on PC22
+ Device (SR4C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR7F)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 4D on PC22
+ Device (SR4D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR80)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+ }
+
+ // Socket 3 Root bridge (Stack 5)
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 5
+ Device (PC23) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x17)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR81)
+ }
+
+ #include "IioRootBridge.asi"
+ #include "Sck3Ejd.asi"
+
+ // PCI Express Port 5A on PC23
+ Device (SR5A) {
+ Name (_ADR, 0x00020000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR82)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 5B on PC23
+ Device (SR5B) {
+ Name (_ADR, 0x00030000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR83)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 5C on PC23
+ Device (SR5C) {
+ Name (_ADR, 0x00040000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR84)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+
+ // PCI Express Port 5D on PC23
+ Device (SR5D) {
+ Name (_ADR, 0x00050000)
+ Method (_PRW, 0) {
+ Return (Package (0x02) {0x09, 0x04})
+ }
+ Method (_PRT, 0) {
+
+ Return (AR85)
+ }
+
+ #include "PcieHp.asi"
+ #include "PcieHpDev.asi"
+ #include "PC1810nmEjd.asi"
+ }
+ }
+
+ // Socket 3 Uncore 0
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 6
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x38)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR86)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 6 UBOX Device
+ Device (UBX3) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 6 Misc 2 UPI 0-7 Device
+ Device (UP06) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 6 Misc 1 UPI 0-7 Device
+ Device (UP07) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 6 M2UPI0 Device
+ Device (M2U9) {
+ Name (_ADR, 0x00050000)
+ }
+
+ // Uncore 6 M2UPI1 Device
+ Device (M2UA) {
+ Name (_ADR, 0x00060000)
+ }
+
+ // Uncore 6 M2UPI2 Device
+ Device (M2UB) {
+ Name (_ADR, 0x00070000)
+ }
+
+ // Uncore 6 CHASIS_SMBUS Devices
+ Device (CSM3) {
+ Name (_ADR, 0x000B0000)
+ }
+
+ // Uncore 6 MS2MEM_SCF_MS2MEM0 Device
+ Device (M2M6) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 6 MS2MEM_SCF_MS2MEM1 Device
+ Device (M2M7) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 6 MCDDR0 Device
+ Device (MCD6) {
+ Name (_ADR, 0x001A0000)
+ }
+
+ // Uncore 6 MCDDR1 Device
+ Device (MCD7) {
+ Name (_ADR, 0x001B0000)
+ }
+ }
+
+ // Socket 3 Uncore 1
+ //
+#undef SOCKET
+#undef STACK
+#define SOCKET 3
+#define STACK 7
+ Device (CONCATENATE3(UC, SOCKET, STACK)) {
+ Name (_HID, EISAID("PNP0A03"))
+ Name (_UID, 0x39)
+
+ //
+ // _PRT is ACPI method called by OS to read PCI Routing Table.
+ //
+ Method (_PRT, 0)
+ {
+ Return (AR87)
+ }
+
+ #include "Uncore.asi"
+
+ // Uncore 7 GRP1_CHA0-7 Device
+ Device (FHA0) {
+ Name (_ADR, 0x00000000)
+ }
+
+ // Uncore 7 GRP1_CHA8-15 Device
+ Device (FHA1) {
+ Name (_ADR, 0x00010000)
+ }
+
+ // Uncore 7 GRP1_CHA16-23 Device
+ Device (FHA2) {
+ Name (_ADR, 0x00020000)
+ }
+
+ // Uncore 7 GRP1_CHAU24-31 Device
+ Device (FHA3) {
+ Name (_ADR, 0x00030000)
+ }
+
+ // Uncore 7 GRP1_CHA32-33 Device
+ Device (FHA4) {
+ Name (_ADR, 0x00040000)
+ }
+
+ // Uncore 7 GRP0_CHA0-7 Device
+ Device (FHA5) {
+ Name (_ADR, 0x000A0000)
+ }
+
+ // Uncore 7 GRP0_CHA24-31 Device
+ Device (FHA8) {
+ Name (_ADR, 0x000D0000)
+ }
+
+ // Uncore 7 GRP0_CHA32-33 Device
+ Device (FHA9) {
+ Name (_ADR, 0x000E0000)
+ }
+
+ // Uncore 7 GRP0_CHA8-15 Device
+ Device (FHA6) {
+ Name (_ADR, 0x00B00000)
+ }
+
+ // Uncore 7 GRP0_CHA16-23 Device
+ Device (FHA7) {
+ Name (_ADR, 0x000C0000)
+ }
+
+ // Uncore 7 CHAALL0-1 Device
+ Device (CA03) {
+ Name (_ADR, 0x001D0000)
+ }
+
+ // Uncore 7 CHASIS_PUINT0-7 Device
+ Device (PUC3) {
+ Name (_ADR, 0x001E0000)
+ }
+
+ // Uncore 7 Gen3Phy Device
+ Device (GN33) {
+ Name (_ADR, 0x001F0000)
+ }
+ }
+#endif
+
+ // Virtual FPGA Bridge on Socket 0
+ Device (VFP0) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x18)
+ Method (_BBN, 0, NotSerialized) {
+ return (FBB0)
+ }
+
+ Method (_PRT, 0) {
+
+ Return (AR88)
+ }
+
+ #include "FpgaBus00.asi"
+
+ // FPGA Device
+ Device (FPG0) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+#if MAX_SOCKET > 1
+
+ // Virtual FPGA Bridge on Socket 1
+ Device (VFP1) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x19)
+ Method (_BBN, 0, NotSerialized) {
+ return (FBB1)
+ }
+
+ Method (_PRT, 0) {
+
+ Return (AR89)
+ }
+
+ #include "FpgaBus01.asi"
+
+ // FPGA Device
+ Device (FPG1) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+#endif
+
+#if MAX_SOCKET > 2
+ // Virtual FPGA Bridge on Socket 2
+ Device (VFP2) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x1A)
+ Method (_BBN, 0, NotSerialized) {
+ return (FBB2)
+ }
+
+ Method (_PRT, 0) {
+
+ Return (AR8A)
+ }
+
+ #include "FpgaBus02.asi"
+
+ // FPGA Device
+ Device (FPG2) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+#endif
+
+#if MAX_SOCKET > 3
+ // Virtual FPGA Bridge on Socket 3
+ Device (VFP3) {
+ Name (_HID, EISAID("PNP0A08"))
+ Name (_CID, EISAID("PNP0A03"))
+ Name (_UID, 0x1B)
+ Method (_BBN, 0, NotSerialized) {
+ return (FBB3)
+ }
+
+ Method (_PRT, 0) {
+
+ Return (AR8B)
+ }
+
+ #include "FpgaBus03.asi"
+
+ // FPGA Device
+ Device (FPG3) {
+ Name (_ADR, 0x00000000)
+ }
+ }
+#endif
+}
+
+Scope (\_GPE) {
+ // [BR1A]: PCI Express Port 1A on PC01
+ // [BR1B]: PCI Express Port 1B on PC01
+ // [BR1C]: PCI Express Port 1C on PC01
+ // [BR1D]: PCI Express Port 1D on PC01
+ // [BR2A]: PCI Express Port 2A on PC02
+ // [BR2B]: PCI Express Port 2B on PC02
+ // [BR2C]: PCI Express Port 2C on PC02
+ // [BR2D]: PCI Express Port 2D on PC02
+ // [BR3A]: PCI Express Port 3A on PC03
+ // [BR3B]: PCI Express Port 3B on PC03
+ // [BR3C]: PCI Express Port 3C on PC03
+ // [BR3D]: PCI Express Port 3D on PC03
+ // [BR4A]: PCI Express Port 4A on PC04
+ // [BR4B]: PCI Express Port 4B on PC04
+ // [BR4C]: PCI Express Port 4C on PC04
+ // [BR4D]: PCI Express Port 4D on PC04
+ // [BR5A]: PCI Express Port 5A on PC05
+ // [BR5B]: PCI Express Port 5B on PC05
+ // [BR5C]: PCI Express Port 5C on PC05
+ // [BR5D]: PCI Express Port 5D on PC05
+ // [QR1A]: PCI Express Port 1A on PC07
+ // [QR1B]: PCI Express Port 1B on PC07
+ // [QR1C]: PCI Express Port 1C on PC07
+ // [QR1D]: PCI Express Port 1D on PC07
+ // [QR2A]: PCI Express Port 2A on PC08
+ // [QR2B]: PCI Express Port 2B on PC08
+ // [QR2C]: PCI Express Port 2C on PC08
+ // [QR2D]: PCI Express Port 2D on PC08
+ // [QR3A]: PCI Express Port 3A on PC09
+ // [QR3B]: PCI Express Port 3B on PC09
+ // [QR3C]: PCI Express Port 3C on PC09
+ // [QR3D]: PCI Express Port 3D on PC09
+ // [QR4A]: PCI Express Port 4A on PC10
+ // [QR4B]: PCI Express Port 4B on PC10
+ // [QR4C]: PCI Express Port 4C on PC10
+ // [QR4D]: PCI Express Port 4D on PC10
+ // [QR5A]: PCI Express Port 5A on PC11
+ // [QR5B]: PCI Express Port 5B on PC11
+ // [QR5C]: PCI Express Port 5C on PC11
+ // [QR5D]: PCI Express Port 5D on PC11
+ // [RR1A]: PCI Express Port 1A on PC13
+ // [RR1B]: PCI Express Port 1B on PC13
+ // [RR1C]: PCI Express Port 1C on PC13
+ // [RR1D]: PCI Express Port 1D on PC13
+ // [RR2A]: PCI Express Port 2A on PC14
+ // [RR2B]: PCI Express Port 2B on PC14
+ // [RR2C]: PCI Express Port 2C on PC14
+ // [RR2D]: PCI Express Port 2D on PC14
+ // [RR3A]: PCI Express Port 3A on PC15
+ // [RR3B]: PCI Express Port 3B on PC15
+ // [RR3C]: PCI Express Port 3C on PC15
+ // [RR3D]: PCI Express Port 3D on PC15
+ // [RR4A]: PCI Express Port 4A on PC16
+ // [RR4B]: PCI Express Port 4B on PC16
+ // [RR4C]: PCI Express Port 4C on PC16
+ // [RR4D]: PCI Express Port 4D on PC16
+ // [RR5A]: PCI Express Port 5A on PC17
+ // [RR5B]: PCI Express Port 5B on PC17
+ // [RR5C]: PCI Express Port 5C on PC17
+ // [RR5D]: PCI Express Port 5D on PC17
+ // [SR1A]: PCI Express Port 1A on PC19
+ // [SR1B]: PCI Express Port 1B on PC19
+ // [SR1C]: PCI Express Port 1C on PC19
+ // [SR1D]: PCI Express Port 1D on PC19
+ // [SR2A]: PCI Express Port 2A on PC20
+ // [SR2B]: PCI Express Port 2B on PC20
+ // [SR2C]: PCI Express Port 2C on PC20
+ // [SR2D]: PCI Express Port 2D on PC20
+ // [SR3A]: PCI Express Port 3A on PC21
+ // [SR3B]: PCI Express Port 3B on PC21
+ // [SR3C]: PCI Express Port 3C on PC21
+ // [SR3D]: PCI Express Port 3D on PC21
+ // [SR4A]: PCI Express Port 4A on PC22
+ // [SR4B]: PCI Express Port 4B on PC22
+ // [SR4C]: PCI Express Port 4C on PC22
+ // [SR4D]: PCI Express Port 4D on PC22
+ // [SR5A]: PCI Express Port 5A on PC23
+ // [SR5B]: PCI Express Port 5B on PC23
+ // [SR5C]: PCI Express Port 5C on PC23
+ // [SR5D]: PCI Express Port 5D on PC23
+ Method (_L09, 0x0, NotSerialized) {
+ #include "Gpe.asi"
+ Notify (\_SB.PC01.BR1A, 0x02)
+ Notify (\_SB.PC01.BR1B, 0x02)
+ Notify (\_SB.PC01.BR1C, 0x02)
+ Notify (\_SB.PC01.BR1D, 0x02)
+ Notify (\_SB.PC02.BR2A, 0x02)
+ Notify (\_SB.PC02.BR2B, 0x02)
+ Notify (\_SB.PC02.BR2C, 0x02)
+ Notify (\_SB.PC02.BR2D, 0x02)
+ Notify (\_SB.PC03.BR3A, 0x02)
+ Notify (\_SB.PC03.BR3B, 0x02)
+ Notify (\_SB.PC03.BR3C, 0x02)
+ Notify (\_SB.PC03.BR3D, 0x02)
+ Notify (\_SB.PC04.BR4A, 0x02)
+ Notify (\_SB.PC04.BR4B, 0x02)
+ Notify (\_SB.PC04.BR4C, 0x02)
+ Notify (\_SB.PC04.BR4D, 0x02)
+ Notify (\_SB.PC05.BR5A, 0x02)
+ Notify (\_SB.PC05.BR5B, 0x02)
+ Notify (\_SB.PC05.BR5C, 0x02)
+ Notify (\_SB.PC05.BR5D, 0x02)
+#if MAX_SOCKET > 1
+ Notify (\_SB.PC07.QR1A, 0x02)
+ Notify (\_SB.PC07.QR1B, 0x02)
+ Notify (\_SB.PC07.QR1C, 0x02)
+ Notify (\_SB.PC07.QR1D, 0x02)
+ Notify (\_SB.PC08.QR2A, 0x02)
+ Notify (\_SB.PC08.QR2B, 0x02)
+ Notify (\_SB.PC08.QR2C, 0x02)
+ Notify (\_SB.PC08.QR2D, 0x02)
+ Notify (\_SB.PC09.QR3A, 0x02)
+ Notify (\_SB.PC09.QR3B, 0x02)
+ Notify (\_SB.PC09.QR3C, 0x02)
+ Notify (\_SB.PC09.QR3D, 0x02)
+ Notify (\_SB.PC10.QR4A, 0x02)
+ Notify (\_SB.PC10.QR4B, 0x02)
+ Notify (\_SB.PC10.QR4C, 0x02)
+ Notify (\_SB.PC10.QR4D, 0x02)
+ Notify (\_SB.PC11.QR5A, 0x02)
+ Notify (\_SB.PC11.QR5B, 0x02)
+ Notify (\_SB.PC11.QR5C, 0x02)
+ Notify (\_SB.PC11.QR5D, 0x02)
+#endif
+#if MAX_SOCKET > 2
+ Notify (\_SB.PC13.RR1A, 0x02)
+ Notify (\_SB.PC13.RR1B, 0x02)
+ Notify (\_SB.PC13.RR1C, 0x02)
+ Notify (\_SB.PC13.RR1D, 0x02)
+ Notify (\_SB.PC14.RR2A, 0x02)
+ Notify (\_SB.PC14.RR2B, 0x02)
+ Notify (\_SB.PC14.RR2C, 0x02)
+ Notify (\_SB.PC14.RR2D, 0x02)
+ Notify (\_SB.PC15.RR3A, 0x02)
+ Notify (\_SB.PC15.RR3B, 0x02)
+ Notify (\_SB.PC15.RR3C, 0x02)
+ Notify (\_SB.PC15.RR3D, 0x02)
+ Notify (\_SB.PC16.RR4A, 0x02)
+ Notify (\_SB.PC16.RR4B, 0x02)
+ Notify (\_SB.PC16.RR4C, 0x02)
+ Notify (\_SB.PC16.RR4D, 0x02)
+ Notify (\_SB.PC17.RR5A, 0x02)
+ Notify (\_SB.PC17.RR5B, 0x02)
+ Notify (\_SB.PC17.RR5C, 0x02)
+ Notify (\_SB.PC17.RR5D, 0x02)
+#endif
+#if MAX_SOCKET > 3
+ Notify (\_SB.PC19.SR1A, 0x02)
+ Notify (\_SB.PC19.SR1B, 0x02)
+ Notify (\_SB.PC19.SR1C, 0x02)
+ Notify (\_SB.PC19.SR1D, 0x02)
+ Notify (\_SB.PC20.SR2A, 0x02)
+ Notify (\_SB.PC20.SR2B, 0x02)
+ Notify (\_SB.PC20.SR2C, 0x02)
+ Notify (\_SB.PC20.SR2D, 0x02)
+ Notify (\_SB.PC21.SR3A, 0x02)
+ Notify (\_SB.PC21.SR3B, 0x02)
+ Notify (\_SB.PC21.SR3C, 0x02)
+ Notify (\_SB.PC21.SR3D, 0x02)
+ Notify (\_SB.PC22.SR4A, 0x02)
+ Notify (\_SB.PC22.SR4B, 0x02)
+ Notify (\_SB.PC22.SR4C, 0x02)
+ Notify (\_SB.PC22.SR4D, 0x02)
+ Notify (\_SB.PC23.SR5A, 0x02)
+ Notify (\_SB.PC23.SR5B, 0x02)
+ Notify (\_SB.PC23.SR5C, 0x02)
+ Notify (\_SB.PC23.SR5D, 0x02)
+#endif
+ }
+
+ // [EPCU]: EVA PCIe Uplink
+ // [VSP0]: EVA Virtual Switch Port 0
+ // [VSP1]: EVA Virtual Switch Port 1
+ // [VSP2]: EVA Virtual Switch Port 2
+ // [VSP3]: EVA Virtual Switch Port 3
+ Method (_L0B, 0x0, NotSerialized) {
+ Notify (\_SB.PC02.BR2A.EPCU, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02)
+ Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02)
+ }
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi
new file mode 100644
index 0000000000..5c5c5fbade
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2012 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if SCK1 is removed.
+ Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi
new file mode 100644
index 0000000000..f8b0cd107d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2012 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if SCK2 is removed.
+ Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi
new file mode 100644
index 0000000000..175d5d871b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi
@@ -0,0 +1,10 @@
+/** @file
+
+ @copyright
+ Copyright 2001 - 2012 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ // Eject device if SCK3 is removed.
+ Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi
new file mode 100644
index 0000000000..d6a1e5da71
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi
@@ -0,0 +1,219 @@
+/** @file
+
+ @copyright
+ Copyright 2007 - 2017 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+Device (EPC) {
+ Name (_HID, EISAID ("INT0E0C"))
+ Name (_STR, Unicode ("Enclave Page Cache 1.0"))
+ Name (_MLS, Package () {Package (2) { "en", Unicode ("Enclave Page Cache 1.0")}})
+
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC0 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC1 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC2 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC3 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC4 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC5 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC6 // DescriptorName
+ )
+ QWordMemory (
+ ResourceConsumer, // ResourceUsage
+ PosDecode, // Decode _DEC
+ MinNotFixed, // IsMinFixed _MIF
+ MaxNotFixed, // IsMaxFixed _MAF
+ NonCacheable, // Cacheable _MEM
+ ReadWrite, // ReadAndWrite _RW
+ 0, // AddressGranularity _GRA
+ 0, // AddressMinimum _MIN <= To be patched in Runtime
+ 0, // AddressMaximum _MAX <= To be patched in Runtime
+ 0, // AddressTranslation _TRA
+ 0, // RangeLength _LEN <= To be patched in Runtime
+ , // ResourceSourceIndex
+ , // ResourceSource
+ EPC7 // DescriptorName
+ )
+ })
+
+ Method (_CRS, 0x0, NotSerialized) {
+ If (LNotEqual (EBA0, 0)) {
+ CreateQwordField (RBUF, ^EPC0._MIN, MIN0)
+ CreateQwordField (RBUF, ^EPC0._MAX, MAX0)
+ CreateQwordField (RBUF, ^EPC0._LEN, LEN0)
+ Store (EBA0, MIN0)
+ Store (ELN0, LEN0)
+ Subtract (Add (EBA0, ELN0), 1, MAX0)
+ }
+ If (LNotEqual (EBA1, 0)) {
+ CreateQwordField (RBUF, ^EPC1._MIN, MIN1)
+ CreateQwordField (RBUF, ^EPC1._MAX, MAX1)
+ CreateQwordField (RBUF, ^EPC1._LEN, LEN1)
+ Store (EBA1, MIN1)
+ Store (ELN1, LEN1)
+ Subtract (Add (EBA1, ELN1), 1, MAX1)
+ }
+ If (LNotEqual (EBA2, 0)) {
+ CreateQwordField (RBUF, ^EPC2._MIN, MIN2)
+ CreateQwordField (RBUF, ^EPC2._MAX, MAX2)
+ CreateQwordField (RBUF, ^EPC2._LEN, LEN2)
+ Store (EBA2, MIN2)
+ Store (ELN2, LEN2)
+ Subtract (Add (EBA2, ELN2), 1, MAX2)
+ }
+ If (LNotEqual (EBA3, 0)) {
+ CreateQwordField (RBUF, ^EPC3._MIN, MIN3)
+ CreateQwordField (RBUF, ^EPC3._MAX, MAX3)
+ CreateQwordField (RBUF, ^EPC3._LEN, LEN3)
+ Store (EBA3, MIN3)
+ Store (ELN3, LEN3)
+ Subtract (Add (EBA3, ELN3), 1, MAX3)
+ }
+ If (LNotEqual (EBA4, 0)) {
+ CreateQwordField (RBUF, ^EPC4._MIN, MIN4)
+ CreateQwordField (RBUF, ^EPC4._MAX, MAX4)
+ CreateQwordField (RBUF, ^EPC4._LEN, LEN4)
+ Store (EBA4, MIN4)
+ Store (ELN4, LEN4)
+ Subtract (Add (EBA4, ELN4), 1, MAX4)
+ }
+ If (LNotEqual (EBA5, 0)) {
+ CreateQwordField (RBUF, ^EPC5._MIN, MIN5)
+ CreateQwordField (RBUF, ^EPC5._MAX, MAX5)
+ CreateQwordField (RBUF, ^EPC5._LEN, LEN5)
+ Store (EBA5, MIN5)
+ Store (ELN5, LEN5)
+ Subtract (Add (EBA5, ELN5), 1, MAX5)
+ }
+ If (LNotEqual (EBA6, 0)) {
+ CreateQwordField (RBUF, ^EPC6._MIN, MIN6)
+ CreateQwordField (RBUF, ^EPC6._MAX, MAX6)
+ CreateQwordField (RBUF, ^EPC6._LEN, LEN6)
+ Store (EBA6, MIN6)
+ Store (ELN6, LEN6)
+ Subtract (Add (EBA6, ELN6), 1, MAX6)
+ }
+ If (LNotEqual (EBA7, 0)) {
+ CreateQwordField (RBUF, ^EPC7._MIN, MIN7)
+ CreateQwordField (RBUF, ^EPC7._MAX, MAX7)
+ CreateQwordField (RBUF, ^EPC7._LEN, LEN7)
+ Store (EBA7, MIN7)
+ Store (ELN7, LEN7)
+ Subtract (Add (EBA7, ELN7), 1, MAX7)
+ }
+ Return (RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized) {
+ If (LNotEqual (EPCS, 0)) {
+ Return (0xF)
+ }
+ Return (0x0)
+ }
+} // end EPC Device
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi
new file mode 100644
index 0000000000..bfda78432c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi
@@ -0,0 +1,163 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2020 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+ //
+ // _BBN is ACPI method called by OS to read PCI base bus number for IIO stack.
+ //
+ Method(_BBN, 0, NotSerialized)
+ {
+ Return(CONCATENATE3(BB, SOCKET, STACK))
+ }
+
+ //
+ // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA Node) where IIO stack belongs to.
+ //
+ Method(_PXM, 0, NotSerialized)
+ {
+ Store(SOCKET, Local0)
+ If (CLOD) {
+ //
+ // If Sub-NUMA Cluster (SNC) enabled report PCI in the first of SNC domains of a socket,
+ // so multiplicate socket number by the number of SNC domains.
+ //
+ Multiply(Local0, CLOD, Local0)
+ }
+ Return(Local0)
+ }
+
+ //
+ // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
+ //
+ Method(_SEG, 0, NotSerialized)
+ {
+ Return(CONCATENATE2(SG0, SOCKET))
+ }
+
+ //
+ // _STA is a ACPI method called by OS to read status of ACPI device, IIO stack in this case.
+ //
+ Method(_STA, 0, NotSerialized)
+ { //
+ // Check in processor present bitmap (PRBM) if processor is present, then
+ // in stack present bitmap of given processor (SPBx) if stack is present.
+ //
+ ShiftLeft(1, SOCKET, Local0)
+ If (And(PRBM, Local0)) {
+
+ ShiftLeft(1, CONCATENATE2(0x,STACK), Local1)
+ if (And(CONCATENATE2(SPB, SOCKET), Local1)) {
+ Return(0x0F)
+ }
+ }
+ Return(0x00)
+ }
+
+ External (DBGM, FieldUnitObj)
+ Name (SUPP, 0)
+ Name (CTRL, 0)
+
+ Method(_OSC,4) {
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,0,CDW1)
+ If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+
+ //
+ // Create DWord-addressable fields from the capabilities Buffer
+ //
+ CreateDWordField(Arg3,4,CDW2)
+
+ //
+ // Fill 3rd capability DWORD only if the count is greater than 2.
+ //
+ If(LGreater(Arg2,2)) {
+ CreateDWordField(Arg3,8,CDW3)
+ }
+
+ //
+ // Save Capabilities DWord2 & 3
+ //
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // Only allow native hot plug control if OS supports
+ // * ASPM
+ // * MSI/MSI-X
+ //
+ If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met?
+ And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
+ Sleep(1000)
+ }
+
+ //
+ // Never allow SHPC (no SHPC controller in system)
+ //
+ And(CTRL, 0x1D, CTRL)
+ //
+ // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA
+ //
+ And (CTRL, 0x17, CTRL)
+ If (Not(And(CDW1,1))) { // Query Flag Clear?
+ //
+ // Disable GPEs for Features granted native control
+ //
+ If (And(CTRL, 0x01)) { // Native Hot plug control granted?
+ Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
+ }
+ }
+
+ If (LNotEqual(Arg1,one)) { // unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Return(Arg3)
+
+ } Else {
+ //
+ // Just indicate unrecognized UUID
+ // Leave it at that
+ //
+ Or (CDW1,4,CDW1)
+ if(LEqual(DBGM, 0x01)){
+ Store (0xEE, IO80)
+ }
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Name (UNRS, ResourceTemplate() {
+ WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses
+ ResourceProducer, // bit 0 of general flags is 1
+ MinFixed, // Range is fixed
+ MaxFixed, // Range is fixed
+ PosDecode, // PosDecode
+ 0x0000, // Granularity (FIX9 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Min (FIX9 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Max (FIX9 - Patched by ACPI Platform Driver during POST)
+ 0x0000, // Translation
+ 0x0001, // Range Length = Max-Min+1 (FIX9 - Patched by ACPI Platform Driver during POST)
+ ,
+ ,
+ FIX9 // DescriptorName populated so iASL outputs offset for it in a .h file
+ )
+ })
+
+ // Current resource template return
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(UNRS)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index 42680254d1..9c2b8a1048 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -805,6 +805,7 @@
$(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ $(RP_PKG)/Features/Acpi/AcpiTables/AcpiTables10nm.inf
$(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
$(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
index 45460570d9..ca3514b8ba 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
@@ -671,6 +671,7 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF RuleOverride = ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
` (4 preceding siblings ...)
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver Oram, Isaac W
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
Separate the [BuildOptions] sections of the DSC to facilitate
multiple DSC builds for prebuilding.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc | 151 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 147 +------------------
2 files changed, 152 insertions(+), 146 deletions(-)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
new file mode 100644
index 0000000000..d806521abf
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
@@ -0,0 +1,151 @@
+## @file
+# Includable build options
+#
+# @copyright
+# Copyright (C) 2008 Intel Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
index 9c2b8a1048..e78a104004 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
@@ -867,149 +867,4 @@
# module style (EDK or EDKII) specified in [Components] section.
#
###################################################################################################
-[BuildOptions.Common.EDKII]
-# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
-!if $(CRB_FLAG_ENABLE) == TRUE
- DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
-!else
- DEFINE CRB_EDKII_BUILD_OPTIONS =
-!endif
-
-!if $(DEBUG_FLAGS_ENABLE) == TRUE
- DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
-!else
- DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
-!endif
-
-!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
- DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
-!else
- DEFINE SPARING_SCRATCHPAD_OPTIONS =
-!endif
-
-!if $(SCRATCHPAD_DEBUG) == TRUE
- DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
-!else
- DEFINE SCRATCHPAD_DEBUG_OPTION =
-!endif
-
-!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
- DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
-!else
- DEFINE PCH_BUILD_OPTION =
-!endif
-
-!if $(SERVER_BIOS_ENABLE) == TRUE
- DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
-!else
- DEFINE SERVER_BUILD_OPTION =
-!endif
-
-DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
-
-DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
-
-DEFINE IE_PATH = -D IE_PATH="Ie/v1"
-
-DEFINE NVDIMM_OPTIONS =
-
-!if $(CPUTARGET) == "ICX"
- DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
-!elseif $(CPUTARGET) == "CPX"
- DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
-!endif
-
-DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
-
-DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
-
-!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
- DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
-!else
- DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
-!endif
-
-DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
-
-DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
-
-DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
-
-#
-# MAX_KTI_PORTS needs to be updated based on the silicon type
-#
-!if $(CPUTARGET) == "CPX"
- DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
-!else
- DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
-!endif
-
-DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
-
-DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
-
-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
-
-DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
-
-!if $(LINUX_GCC_BUILD) == TRUE
- DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
-!else
- DEFINE EDK2_LINUX_BUILD_OPTIONS =
-!endif
-
-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
-
-DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
-
-DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
-
-DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
-
- MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
- GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
- *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
- *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
- *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
- *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
- *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
-
-
-#
-# Enable source level debugging for RELEASE build
-#
-!if $(TARGET) == "RELEASE"
- DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
- DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
- DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
-
- MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
- MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
- MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
- GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
- GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
- GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
-!endif
-
-#
-# Override ASL Compiler parameters in tools_def.template.
-#
- *_*_*_ASL_FLAGS == -vr -we -oi
-#
-# Override the VFR compile flags to speed the build time
-#
-
-*_*_*_VFR_FLAGS == -n
-
-#
-# add to the build options for DXE/SMM drivers to remove the log message:
-# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
-#
-[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
- MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
-
-[BuildOptions]
- GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
- GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
- GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
- MSFT:*_*_*_CC_FLAGS = /FAsc
+!include $(RP_PKG)/Include/Dsc/BuildOptions.dsc
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
` (5 preceding siblings ...)
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver Oram, Isaac W
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
Add PreBuild step to generate the AML offset table for the
ACPI tables.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/.gitignore | 2 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc | 41 +++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf | 26 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py | 63 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg | 15 +++++
5 files changed, 147 insertions(+)
diff --git a/Platform/Intel/.gitignore b/Platform/Intel/.gitignore
new file mode 100644
index 0000000000..548fee5bea
--- /dev/null
+++ b/Platform/Intel/.gitignore
@@ -0,0 +1,2 @@
+WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
+__init__.py
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
new file mode 100644
index 0000000000..2e5ebf432a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
@@ -0,0 +1,41 @@
+## @file
+# Build file for generating AML offset table
+#
+# @copyright
+# Copyright (C) 2021 Intel Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ PLATFORM_NAME = $(RP_PKG)
+ PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+[Components.X64]
+ $(RP_PKG)/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
+
+!include $(RP_PKG)/Include/Dsc/BuildOptions.dsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
new file mode 100644
index 0000000000..8945f372e3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
@@ -0,0 +1,26 @@
+## @file
+# Generate AML offset table EPRPPlatform10nm.offset.h via edk2 build
+#
+# @copyright
+# Copyright (C) 2022 Intel Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AmlOffsets
+ FILE_GUID = d7641589-753a-44c5-91c2-bd09686205c6
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+
+[BuildOptions]
+ # add -vr and -so to generate offset.h
+ *_*_*_ASL_FLAGS = -oi -vr -so
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
index a0c31e4558..5f625f5f92 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
@@ -23,6 +23,7 @@ def pre_build_ex(config, functions):
:returns: nothing
"""
print("pre_build_ex")
+
config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
'Build',
config["PLATFORM_BOARD_PACKAGE"],
@@ -53,6 +54,68 @@ def pre_build_ex(config, functions):
if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable")
+
+ # Build the ACPI AML offset table *.offset.h
+ print("Info: re-generating PlatformOffset header files")
+
+ execute_script = functions.get("execute_script")
+
+ command = ["build", "-D", "MAX_SOCKET=" + config["MAX_SOCKET"]]
+
+ if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
+ ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ")
+ ext_build_flags = [x.strip() for x in ext_build_flags]
+ ext_build_flags = [x for x in ext_build_flags if x != ""]
+ command.extend(ext_build_flags)
+
+ aml_offsets_split = os.path.split(os.path.normpath(config["AML_OFFSETS_PATH"]))
+ command.append("-p")
+ command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) + '.dsc')
+ command.append("-m")
+ command.append(os.path.join(aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1] + '.inf'))
+ command.append("-y")
+ command.append(os.path.join(config["WORKSPACE"], "PreBuildReport.txt"))
+ command.append("--log=" + os.path.join(config["WORKSPACE"], "PreBuild.log"))
+
+ _, _, _, code = execute_script(command, config)
+ if code != 0:
+ print(" ".join(command))
+ print("Error re-generating PlatformOffset header files")
+ sys.exit(1)
+
+ # Build AmlGenOffset command to consume the *.offset.h and produce AmlOffsetTable.c for StaticSkuDataDxe use.
+
+ # Get destination path and filename from config
+ relative_file_path = os.path.normpath(config["STRIPPED_AML_OFFSETS_FILE_PATH"]) # get path relative to Platform/Intel
+ out_file_path = os.path.join(config["WORKSPACE_PLATFORM"], relative_file_path) # full path to output file
+ out_file_dir = os.path.dirname(out_file_path) # remove filename
+
+ out_file_root_ext = os.path.splitext(os.path.basename(out_file_path)) # root and extension of output file
+
+ # Get relative path for the generated offset.h file
+ relative_dsdt_file_path = os.path.normpath(config["DSDT_TABLE_FILE_PATH"]) # path relative to Platform/Intel
+ dsdt_file_root_ext = os.path.splitext(os.path.basename(relative_dsdt_file_path)) # root and extension of generated offset.h file
+
+ # Generate output directory if it doesn't exist
+ if not os.path.exists(out_file_dir):
+ os.mkdir(out_file_dir)
+
+ command = ["python",
+ os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset", "AmlGenOffset.py"),
+ "-d", "--aml_filter", config["AML_FILTER"],
+ "-o", out_file_path,
+ os.path.join(config["BUILD_X64"], aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1], "OUTPUT", os.path.dirname(relative_dsdt_file_path), dsdt_file_root_ext[0] + ".offset.h")]
+
+ # execute the command
+ _, _, _, code = execute_script(command, config)
+ if code != 0:
+ print(" ".join(command))
+ print("Error re-generating PlatformOffset header files")
+ sys.exit(1)
+
+ print("GenOffset done")
+
+
return None
def _merge_files(files, ofile):
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
index 1676c08813..4cc9496153 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
+++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
@@ -34,3 +34,18 @@ FSP_BINARY_BUILD = FALSE
FSP_TEST_RELEASE = FALSE
SECURE_BOOT_ENABLE = FALSE
BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+
+#
+# AML offset table generation configuration options
+# All paths should use / and be relative to edk2-platforms/Platform/Intel
+#
+# AML_FILTER - AML filter is used to strip out unused AML offset data
+# AML_OFFSETS_PATH - Path to INF file that builds AML offsets C source file
+# The directory name, DSC file name, INF file name, and BASE_NAME must match identically
+# DSDT_TABLE_FILE_PATH - Path to DSDT ASL file for the board
+# STRIPPED_AML_OFFSETS_FILE_PATH - Target AML offset data file consumed by UBA driver
+#
+AML_FILTER = \"PSYS\" .\.DRVT\" .\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 .\.CCT[0-9A-Z]\" .\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .\.FXBS\" .\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL };
+AML_OFFSETS_PATH = WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets
+DSDT_TABLE_FILE_PATH = WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
+STRIPPED_AML_OFFSETS_FILE_PATH = WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
` (6 preceding siblings ...)
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table Oram, Isaac W
@ 2022-02-07 19:02 ` Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
7 siblings, 1 reply; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-07 19:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Chasel Chiu
This driver provides data for boards patching AML, PIRQ, and MP tables.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h | 41 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h | 42 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 5 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c | 54 ++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c | 100 ++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c | 110 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md | 19 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c | 60 +++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h | 41 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf | 59 +++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 5 +
11 files changed, 536 insertions(+)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
new file mode 100644
index 0000000000..5aedaf62be
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
@@ -0,0 +1,41 @@
+/** @file
+ UBA Mp table Update Library Header File.
+
+ @copyright
+ Copyright 2008 - 2015 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UBA_MP_TABLE_UPDATE_LIB_H
+#define _UBA_MP_TABLE_UPDATE_LIB_H
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <PlatDevData.h>
+
+#define PLATFORM_MP_TABLE_UPDATE_SIGNATURE SIGNATURE_32 ('U', 'M', 'P', 'T')
+#define PLATFORM_MP_TABLE_UPDATE_VERSION 0x01
+
+// {0FF8A1CF-A0AB-4ac0-BFC9-34A78F68DD8A}
+#define PLATFORM_MP_TABLE_CONFIG_DATA_GUID \
+{ 0xff8a1cf, 0xa0ab, 0x4ac0, { 0xbf, 0xc9, 0x34, 0xa7, 0x8f, 0x68, 0xdd, 0x8a } };
+
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ DEVICE_DATA *DeviceDataPtr;
+
+} PLATFORM_MP_UPDATE_TABLE;
+
+EFI_STATUS
+PlatformGetMpTableDataPointer (
+ IN DEVICE_DATA **DeviceData
+);
+
+STATIC EFI_GUID gPlatformMpTableConfigDataGuid =PLATFORM_MP_TABLE_CONFIG_DATA_GUID;
+
+#endif //_UBA_MP_TABLE_UPDATE_LIB_H
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
new file mode 100644
index 0000000000..4261b7b74f
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
@@ -0,0 +1,42 @@
+/** @file
+ UBA PirqData Update Library Header File.
+
+ @copyright
+ Copyright 2008 - 2014 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UBA_PIRQ_UPDATE_LIB_H
+#define _UBA_PIRQ_UPDATE_LIB_H
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <PlatPirqData.h>
+
+#define PLATFORM_PIRQ_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'R', 'Q')
+#define PLATFORM_PIRQ_UPDATE_VERSION 0x01
+
+
+// {4C1F48A5-C976-4d90-9F03-8E9B1C327FCF}
+#define PLATFORM_PIRQ_CONFIG_DATA_GUID \
+{ 0x4c1f48a5, 0xc976, 0x4d90, { 0x9f, 0x3, 0x8e, 0x9b, 0x1c, 0x32, 0x7f, 0xcf } }
+
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Version;
+
+ PLATFORM_PIRQ_DATA *PirqDataPtr;
+
+} PLATFORM_PIRQ_UPDATE_TABLE;
+
+EFI_STATUS
+PlatformGetPirqDataPointer (
+ IN PLATFORM_PIRQ_DATA **PirqData
+);
+
+STATIC EFI_GUID gPlatformPirqConfigDataGuid = PLATFORM_PIRQ_CONFIG_DATA_GUID;
+
+#endif //_UBA_PIRQ_UPDATE_LIB_H
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
index fcf147885f..7c182db5df 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
@@ -7,6 +7,11 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
+#
+# Currently shared by all platforms
+#
+INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
+
#
# Platform TypeWilsonCityRP
#
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
new file mode 100644
index 0000000000..c658b9fd28
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
@@ -0,0 +1,54 @@
+/** @file
+ ACPI static data update.
+
+ @copyright
+ Copyright 2013 - 2022 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "StaticSkuDataDxe.h"
+#include <Library/UbaAcpiUpdateLib.h>
+
+#include "AmlOffsetTable.c" // Generated in PreBuild step
+
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+
+ACPI_FIX_UPDATE_TABLE FixupTableUpdate10nm =
+{
+ PLATFORM_ACPI_FIX_UPDATE_SIGNATURE,
+ PLATFORM_ACPI_FIX_UPDATE_VERSION,
+ &DSDT_EPRP10NM_OffsetTable
+};
+
+EFI_STATUS
+InstallAcpiFixupTableData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ ACPI_FIX_UPDATE_TABLE *PtrTable;
+ UINT32 TableSize;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ PtrTable = &FixupTableUpdate10nm;
+ TableSize = sizeof(FixupTableUpdate10nm);
+ DEBUG ((DEBUG_INFO, "UBA: Loading Acpi table for ICX\n"));
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformAcpiFixTableGuid,
+ PtrTable,
+ TableSize
+ );
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
new file mode 100644
index 0000000000..dc49390cb2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
@@ -0,0 +1,100 @@
+/** @file
+ Device data installation.
+
+ @copyright
+ Copyright 2014 - 2022 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "StaticSkuDataDxe.h"
+
+#include <Library/UbaPirqUpdateLib.h>
+#include <Library/UbaMpTableUpdateLib.h>
+
+#include <PlatPirqData.h>
+#include <PlatDevData.h>
+
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+
+extern PLATFORM_PIRQ_DATA mPlatformPirqDataPlatformSRP10nm;
+
+PLATFORM_PIRQ_UPDATE_TABLE PirqUpdate10nm =
+{
+ PLATFORM_PIRQ_UPDATE_SIGNATURE,
+ PLATFORM_PIRQ_UPDATE_VERSION,
+ &mPlatformPirqDataPlatformSRP10nm
+};
+
+EFI_STATUS
+InstallPirqData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ PLATFORM_PIRQ_UPDATE_TABLE *PtrTable;
+ UINT32 TableSize;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ PtrTable = &PirqUpdate10nm;
+ TableSize = sizeof(PirqUpdate10nm);
+ DEBUG ((DEBUG_ERROR, "UBA: Loading Pirqupdate table for ICX\n"));
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformPirqConfigDataGuid,
+ PtrTable,
+ TableSize
+ );
+ return Status;
+}
+
+extern DEVICE_DATA mDeviceDataPlatformSRP10nm;
+
+PLATFORM_MP_UPDATE_TABLE MpTableUpdate10nm =
+{
+ PLATFORM_MP_TABLE_UPDATE_SIGNATURE,
+ PLATFORM_MP_TABLE_UPDATE_VERSION,
+ &mDeviceDataPlatformSRP10nm
+};
+
+EFI_STATUS
+InstallMpTableData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ PLATFORM_MP_UPDATE_TABLE *PtrTable;
+ UINT32 TableSize;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ PtrTable = &MpTableUpdate10nm;
+ TableSize = sizeof(MpTableUpdate10nm);
+ DEBUG ((DEBUG_ERROR, "UBA: Loading MpTableupdate table for ICX\n"));
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformMpTableConfigDataGuid,
+ PtrTable,
+ TableSize
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
new file mode 100644
index 0000000000..ed9f80734c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
@@ -0,0 +1,110 @@
+/** @file
+
+ @copyright
+ Copyright 2017 - 2018 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PlatPirqData.h>
+#include <PlatDevData.h>
+#include <IndustryStandard/LegacyBiosMpTable.h>
+
+#ifndef V_INTEL_VID
+#define V_INTEL_VID 0x8086
+#endif // #ifndef V_INTEL_VID
+
+//
+// Describes Local APICs' connections.
+//
+STATIC DEVICE_DATA_HW_LOCAL_INT DeviceDataHwLocalInt1[] = {
+ {
+ {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}},
+ 0x00,
+ 0xff,
+ 0x00,
+ EfiLegacyMpTableEntryLocalIntTypeExtInt,
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
+ },
+ {
+ {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}},
+ 0x00,
+ 0xff,
+ 0x01,
+ EfiLegacyMpTableEntryLocalIntTypeInt,
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec,
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
+ },
+};
+
+//
+// Describes system's address space mapping, specific to the system.
+//
+STATIC DEVICE_DATA_HW_ADDR_SPACE_MAPPING DeviceDataHwAddrSpace1[] = {
+ //
+ // Legacy IO addresses.
+ //
+ { {0}, EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo, 0x0000, 0x1000 },
+};
+
+//
+// IRQ priority
+//
+STATIC EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY IrqPriorityTable1[] = {
+ {11, 0},
+ {10, 0},
+ {9, 0},
+ {5, 0},
+ {0, 0},
+ {0, 0},
+ {0, 0}
+};
+
+//
+// Note : UpdateBusNumbers updates the bus numeber
+//
+STATIC EFI_LEGACY_PIRQ_TABLE PirqTableHead1 [] = {
+ {
+ {
+ EFI_PIRQ_TABLE_SIGNATURE,
+ 00,
+ 01,
+ 0000,
+ 00,
+ 00,
+ 0000,
+ V_INTEL_VID,
+ 30,
+ 00000000,
+ {00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00,
+ 00},
+ 00
+ }
+ }
+};
+
+//
+// Instantiation of the system device data.
+//
+DEVICE_DATA mDeviceDataPlatformSRP10nm = {
+ DeviceDataHwLocalInt1, sizeof (DeviceDataHwLocalInt1) / sizeof (DeviceDataHwLocalInt1[0]),
+ DeviceDataHwAddrSpace1, sizeof (DeviceDataHwAddrSpace1)/ sizeof (DeviceDataHwAddrSpace1[0])
+};
+
+//
+// Instantiation of platform PIRQ data.
+//
+PLATFORM_PIRQ_DATA mPlatformPirqDataPlatformSRP10nm = {
+ IrqPriorityTable1, sizeof(IrqPriorityTable1) / sizeof(IrqPriorityTable1[0]),
+ PirqTableHead1, sizeof(PirqTableHead1) / sizeof(PirqTableHead1[0])
+};
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
new file mode 100644
index 0000000000..2138810db4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
@@ -0,0 +1,19 @@
+# **Generating ACPI AML Offset table**
+
+The StaticSkuDataDxe driver includes AmlOffsetTable.c which contains the AML offset table. This Readme captures the build process for this file.
+
+edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py drives the build since ACPI tables are expected to be board specific.
+
+The AmlOffsetTable.c file is generated in two key steps:
+1. Generate the *Dsdt*.offsets.h where *Dsdt* is the DSDT ASL file name specific for this build. For WilsonCityRvp:
+ * The DSDT is WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
+ * The generated file is Build/WhitleyOpenBoardPkg/DEBUG_VS2015x86/X64/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets/OUTPUT/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.offset.h
+ * These are customized in the build_config.cfg file
+2. Generat the AmlOffsetTable.c using the AmlGenOffset.py script from the MinPlatformPkg. For WilsonCityRvp:
+ * Script is at edk2-platforms/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
+ * Input is Build/WhitleyOpenBoardPkg/DEBUG_VS2015x86/X64/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets/OUTPUT/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.offset.h
+ * Output is edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
+
+Common Issues:
+* The same iasl compiler version must be used to build the AML offset table and to build the DSDT.
+* The Board/*AmlOffsets*.dsc file name, Board/*AmlOffsets* directory name, Board/AmlOffsets/*AmlOffsets*.inf file name, and the BASE_NAME in *AmlOffsets*.inf must all match exactly.
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
new file mode 100644
index 0000000000..c4f0102f59
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
@@ -0,0 +1,60 @@
+/** @file
+ UBA static sku data update dxe driver.
+
+ @copyright
+ Copyright 2013 - 2014 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "StaticSkuDataDxe.h"
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+StaticSkuConfigDataDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = InstallMpTableData (UbaConfigProtocol);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = InstallPirqData (UbaConfigProtocol);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = InstallAcpiFixupTableData (UbaConfigProtocol);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
new file mode 100644
index 0000000000..e54191d4f7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
@@ -0,0 +1,41 @@
+/** @file
+ UBA static sku data update dxe driver.
+
+ @copyright
+ Copyright 2013 - 2022 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _STATIC_SKU_DATA_DXE_H_
+#define _STATIC_SKU_DATA_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Protocol/UbaCfgDb.h>
+
+EFI_STATUS
+InstallMpTableData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+);
+
+EFI_STATUS
+InstallPirqData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+);
+
+EFI_STATUS
+InstallAcpiFixupTableData (
+ IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
+);
+
+#endif // _STATIC_SKU_DATA_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
new file mode 100644
index 0000000000..97a1931c84
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
@@ -0,0 +1,59 @@
+## @file
+# Static Board Data DXE Driver.
+#
+# @copyright
+# Copyright 2018 - 2022 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = StaticSkuDataDxeBaseline
+ FILE_GUID = 2C03C058-4305-7829-7E84-C7B3D6232F42
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = StaticSkuConfigDataDxeEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = x64
+#
+
+[Sources]
+ StaticSkuDataDxe.c
+ StaticSkuDataDxe.h
+ DeviceDataInstall.c
+ PlatformDeviceDataSRP10nm.c
+ AcpiStaticData.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ DebugLib
+ IoLib
+ HobLib
+
+[Guids]
+ gEfiPlatformInfoGuid
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid OR
+ gEfiPlatformTypeWilsonCityRPProtocolGuid OR
+ gEfiPlatformTypeJunctionCityProtocolGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
index f37093bccd..48b26de427 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
@@ -30,6 +30,11 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
}
[Components.X64]
+#
+# Currently shared by all platforms
+#
+$(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
+
#
# Platform TypeWilsonCityRP
#
--
2.27.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver Oram, Isaac W
@ 2022-02-09 3:20 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:20 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Hi Isaac,
Please see feedback inline.
There is a minor typo in Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md. "Generat" should be "Generate". This can be fixed during the commit process, no need to send a V2 patch series.
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Thanks,
Nate
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 8/8]
> WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver
>
> This driver provides data for boards patching AML, PIRQ, and MP tables.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
> Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h | 41 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h | 42 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 5 +
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c | 54 ++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c | 100 ++++++++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c | 110 ++++++++++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md | 19 ++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c | 60 +++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h | 41 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf | 59 +++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 5 +
> 11 files changed, 536 insertions(+)
>
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
> new file mode 100644
> index 0000000000..5aedaf62be
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
> @@ -0,0 +1,41 @@
> +/** @file
> + UBA Mp table Update Library Header File.
> +
> + @copyright
> + Copyright 2008 - 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _UBA_MP_TABLE_UPDATE_LIB_H
> +#define _UBA_MP_TABLE_UPDATE_LIB_H
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +#include <PlatDevData.h>
> +
> +#define PLATFORM_MP_TABLE_UPDATE_SIGNATURE SIGNATURE_32 ('U', 'M', 'P', 'T')
> +#define PLATFORM_MP_TABLE_UPDATE_VERSION 0x01
> +
> +// {0FF8A1CF-A0AB-4ac0-BFC9-34A78F68DD8A}
> +#define PLATFORM_MP_TABLE_CONFIG_DATA_GUID \
> +{ 0xff8a1cf, 0xa0ab, 0x4ac0, { 0xbf, 0xc9, 0x34, 0xa7, 0x8f, 0x68, 0xdd, 0x8a } };
> +
> +
> +typedef struct {
> + UINT32 Signature;
> + UINT32 Version;
> +
> + DEVICE_DATA *DeviceDataPtr;
> +
> +} PLATFORM_MP_UPDATE_TABLE;
> +
> +EFI_STATUS
> +PlatformGetMpTableDataPointer (
> + IN DEVICE_DATA **DeviceData
> +);
> +
> +STATIC EFI_GUID gPlatformMpTableConfigDataGuid =PLATFORM_MP_TABLE_CONFIG_DATA_GUID;
> +
> +#endif //_UBA_MP_TABLE_UPDATE_LIB_H
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
> new file mode 100644
> index 0000000000..4261b7b74f
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
> @@ -0,0 +1,42 @@
> +/** @file
> + UBA PirqData Update Library Header File.
> +
> + @copyright
> + Copyright 2008 - 2014 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _UBA_PIRQ_UPDATE_LIB_H
> +#define _UBA_PIRQ_UPDATE_LIB_H
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +#include <PlatPirqData.h>
> +
> +#define PLATFORM_PIRQ_UPDATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'R', 'Q')
> +#define PLATFORM_PIRQ_UPDATE_VERSION 0x01
> +
> +
> +// {4C1F48A5-C976-4d90-9F03-8E9B1C327FCF}
> +#define PLATFORM_PIRQ_CONFIG_DATA_GUID \
> +{ 0x4c1f48a5, 0xc976, 0x4d90, { 0x9f, 0x3, 0x8e, 0x9b, 0x1c, 0x32, 0x7f, 0xcf } }
> +
> +
> +typedef struct {
> + UINT32 Signature;
> + UINT32 Version;
> +
> + PLATFORM_PIRQ_DATA *PirqDataPtr;
> +
> +} PLATFORM_PIRQ_UPDATE_TABLE;
> +
> +EFI_STATUS
> +PlatformGetPirqDataPointer (
> + IN PLATFORM_PIRQ_DATA **PirqData
> +);
> +
> +STATIC EFI_GUID gPlatformPirqConfigDataGuid = PLATFORM_PIRQ_CONFIG_DATA_GUID;
> +
> +#endif //_UBA_PIRQ_UPDATE_LIB_H
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> index fcf147885f..7c182db5df 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
> @@ -7,6 +7,11 @@
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> ##
>
> +#
> +# Currently shared by all platforms
> +#
> +INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
> +
> #
> # Platform TypeWilsonCityRP
> #
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
> new file mode 100644
> index 0000000000..c658b9fd28
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
> @@ -0,0 +1,54 @@
> +/** @file
> + ACPI static data update.
> +
> + @copyright
> + Copyright 2013 - 2022 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "StaticSkuDataDxe.h"
> +#include <Library/UbaAcpiUpdateLib.h>
> +
> +#include "AmlOffsetTable.c" // Generated in PreBuild step
> +
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +
> +ACPI_FIX_UPDATE_TABLE FixupTableUpdate10nm =
> +{
> + PLATFORM_ACPI_FIX_UPDATE_SIGNATURE,
> + PLATFORM_ACPI_FIX_UPDATE_VERSION,
> + &DSDT_EPRP10NM_OffsetTable
> +};
> +
> +EFI_STATUS
> +InstallAcpiFixupTableData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + EFI_HOB_GUID_TYPE *GuidHob;
> + EFI_PLATFORM_INFO *PlatformInfo;
> + ACPI_FIX_UPDATE_TABLE *PtrTable;
> + UINT32 TableSize;
> +
> + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (GuidHob != NULL);
> + if (GuidHob == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
> +
> + PtrTable = &FixupTableUpdate10nm;
> + TableSize = sizeof(FixupTableUpdate10nm);
> + DEBUG ((DEBUG_INFO, "UBA: Loading Acpi table for ICX\n"));
> +
> + Status = UbaConfigProtocol->AddData (
> + UbaConfigProtocol,
> + &gPlatformAcpiFixTableGuid,
> + PtrTable,
> + TableSize
> + );
> + return Status;
> +}
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
> new file mode 100644
> index 0000000000..dc49390cb2
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
> @@ -0,0 +1,100 @@
> +/** @file
> + Device data installation.
> +
> + @copyright
> + Copyright 2014 - 2022 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "StaticSkuDataDxe.h"
> +
> +#include <Library/UbaPirqUpdateLib.h>
> +#include <Library/UbaMpTableUpdateLib.h>
> +
> +#include <PlatPirqData.h>
> +#include <PlatDevData.h>
> +
> +#include <Library/HobLib.h>
> +#include <Guid/PlatformInfo.h>
> +
> +extern PLATFORM_PIRQ_DATA mPlatformPirqDataPlatformSRP10nm;
> +
> +PLATFORM_PIRQ_UPDATE_TABLE PirqUpdate10nm =
> +{
> + PLATFORM_PIRQ_UPDATE_SIGNATURE,
> + PLATFORM_PIRQ_UPDATE_VERSION,
> + &mPlatformPirqDataPlatformSRP10nm
> +};
> +
> +EFI_STATUS
> +InstallPirqData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + PLATFORM_PIRQ_UPDATE_TABLE *PtrTable;
> + UINT32 TableSize;
> + EFI_HOB_GUID_TYPE *GuidHob;
> + EFI_PLATFORM_INFO *PlatformInfo;
> +
> + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (GuidHob != NULL);
> + if (GuidHob == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
> +
> + PtrTable = &PirqUpdate10nm;
> + TableSize = sizeof(PirqUpdate10nm);
> + DEBUG ((DEBUG_ERROR, "UBA: Loading Pirqupdate table for ICX\n"));
> +
> + Status = UbaConfigProtocol->AddData (
> + UbaConfigProtocol,
> + &gPlatformPirqConfigDataGuid,
> + PtrTable,
> + TableSize
> + );
> + return Status;
> +}
> +
> +extern DEVICE_DATA mDeviceDataPlatformSRP10nm;
> +
> +PLATFORM_MP_UPDATE_TABLE MpTableUpdate10nm =
> +{
> + PLATFORM_MP_TABLE_UPDATE_SIGNATURE,
> + PLATFORM_MP_TABLE_UPDATE_VERSION,
> + &mDeviceDataPlatformSRP10nm
> +};
> +
> +EFI_STATUS
> +InstallMpTableData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> + PLATFORM_MP_UPDATE_TABLE *PtrTable;
> + UINT32 TableSize;
> + EFI_HOB_GUID_TYPE *GuidHob;
> + EFI_PLATFORM_INFO *PlatformInfo;
> +
> + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
> + ASSERT (GuidHob != NULL);
> + if (GuidHob == NULL) {
> + return EFI_NOT_FOUND;
> + }
> + PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
> +
> + PtrTable = &MpTableUpdate10nm;
> + TableSize = sizeof(MpTableUpdate10nm);
> + DEBUG ((DEBUG_ERROR, "UBA: Loading MpTableupdate table for ICX\n"));
> +
> + Status = UbaConfigProtocol->AddData (
> + UbaConfigProtocol,
> + &gPlatformMpTableConfigDataGuid,
> + PtrTable,
> + TableSize
> + );
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
> new file mode 100644
> index 0000000000..ed9f80734c
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
> @@ -0,0 +1,110 @@
> +/** @file
> +
> + @copyright
> + Copyright 2017 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PlatPirqData.h>
> +#include <PlatDevData.h>
> +#include <IndustryStandard/LegacyBiosMpTable.h>
> +
> +#ifndef V_INTEL_VID
> +#define V_INTEL_VID 0x8086
> +#endif // #ifndef V_INTEL_VID
> +
> +//
> +// Describes Local APICs' connections.
> +//
> +STATIC DEVICE_DATA_HW_LOCAL_INT DeviceDataHwLocalInt1[] = {
> + {
> + {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}},
> + 0x00,
> + 0xff,
> + 0x00,
> + EfiLegacyMpTableEntryLocalIntTypeExtInt,
> + EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec,
> + EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
> + },
> + {
> + {{0},{{0xFF,0},{0xFF,0},{0xFF,0}}},
> + 0x00,
> + 0xff,
> + 0x01,
> + EfiLegacyMpTableEntryLocalIntTypeInt,
> + EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec,
> + EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
> + },
> +};
> +
> +//
> +// Describes system's address space mapping, specific to the system.
> +//
> +STATIC DEVICE_DATA_HW_ADDR_SPACE_MAPPING DeviceDataHwAddrSpace1[] = {
> + //
> + // Legacy IO addresses.
> + //
> + { {0}, EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo, 0x0000, 0x1000 },
> +};
> +
> +//
> +// IRQ priority
> +//
> +STATIC EFI_LEGACY_IRQ_PRIORITY_TABLE_ENTRY IrqPriorityTable1[] = {
> + {11, 0},
> + {10, 0},
> + {9, 0},
> + {5, 0},
> + {0, 0},
> + {0, 0},
> + {0, 0}
> +};
> +
> +//
> +// Note : UpdateBusNumbers updates the bus numeber
> +//
> +STATIC EFI_LEGACY_PIRQ_TABLE PirqTableHead1 [] = {
> + {
> + {
> + EFI_PIRQ_TABLE_SIGNATURE,
> + 00,
> + 01,
> + 0000,
> + 00,
> + 00,
> + 0000,
> + V_INTEL_VID,
> + 30,
> + 00000000,
> + {00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00,
> + 00},
> + 00
> + }
> + }
> +};
> +
> +//
> +// Instantiation of the system device data.
> +//
> +DEVICE_DATA mDeviceDataPlatformSRP10nm = {
> + DeviceDataHwLocalInt1, sizeof (DeviceDataHwLocalInt1) / sizeof (DeviceDataHwLocalInt1[0]),
> + DeviceDataHwAddrSpace1, sizeof (DeviceDataHwAddrSpace1)/ sizeof (DeviceDataHwAddrSpace1[0])
> +};
> +
> +//
> +// Instantiation of platform PIRQ data.
> +//
> +PLATFORM_PIRQ_DATA mPlatformPirqDataPlatformSRP10nm = {
> + IrqPriorityTable1, sizeof(IrqPriorityTable1) / sizeof(IrqPriorityTable1[0]),
> + PirqTableHead1, sizeof(PirqTableHead1) / sizeof(PirqTableHead1[0])
> +};
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
> new file mode 100644
> index 0000000000..2138810db4
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
> @@ -0,0 +1,19 @@
> +# **Generating ACPI AML Offset table**
> +
> +The StaticSkuDataDxe driver includes AmlOffsetTable.c which contains the AML offset table. This Readme captures the build process for this file.
> +
> +edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py drives the build since ACPI tables are expected to be board specific.
> +
> +The AmlOffsetTable.c file is generated in two key steps:
> +1. Generate the *Dsdt*.offsets.h where *Dsdt* is the DSDT ASL file name specific for this build. For WilsonCityRvp:
> + * The DSDT is WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
> + * The generated file is Build/WhitleyOpenBoardPkg/DEBUG_VS2015x86/X64/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets/OUTPUT/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.offset.h
> + * These are customized in the build_config.cfg file
> +2. Generat the AmlOffsetTable.c using the AmlGenOffset.py script from the MinPlatformPkg. For WilsonCityRvp:
Typo here. "Generat" should be "Generate".
> + * Script is at edk2-platforms/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
> + * Input is Build/WhitleyOpenBoardPkg/DEBUG_VS2015x86/X64/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets/OUTPUT/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.offset.h
> + * Output is edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
> +
> +Common Issues:
> +* The same iasl compiler version must be used to build the AML offset table and to build the DSDT.
> +* The Board/*AmlOffsets*.dsc file name, Board/*AmlOffsets* directory name, Board/AmlOffsets/*AmlOffsets*.inf file name, and the BASE_NAME in *AmlOffsets*.inf must all match exactly.
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
> new file mode 100644
> index 0000000000..c4f0102f59
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
> @@ -0,0 +1,60 @@
> +/** @file
> + UBA static sku data update dxe driver.
> +
> + @copyright
> + Copyright 2013 - 2014 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "StaticSkuDataDxe.h"
> +
> +/**
> + The Driver Entry Point.
> +
> + The function is the driver Entry point.
> +
> + @param ImageHandle A handle for the image that is initializing this driver
> + @param SystemTable A pointer to the EFI system table
> +
> + @retval EFI_SUCCESS: Driver initialized successfully
> + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
> + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +StaticSkuConfigDataDxeEntry (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> +)
> +{
> + EFI_STATUS Status;
> + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
> +
> + Status = gBS->LocateProtocol (
> + &gUbaConfigDatabaseProtocolGuid,
> + NULL,
> + &UbaConfigProtocol
> + );
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Status = InstallMpTableData (UbaConfigProtocol);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Status = InstallPirqData (UbaConfigProtocol);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + Status = InstallAcpiFixupTableData (UbaConfigProtocol);
> + if (EFI_ERROR(Status)) {
> + return Status;
> + }
> +
> + return Status;
> +}
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
> new file mode 100644
> index 0000000000..e54191d4f7
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
> @@ -0,0 +1,41 @@
> +/** @file
> + UBA static sku data update dxe driver.
> +
> + @copyright
> + Copyright 2013 - 2022 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _STATIC_SKU_DATA_DXE_H_
> +#define _STATIC_SKU_DATA_DXE_H_
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +
> +#include <Library/UefiDriverEntryPoint.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/IoLib.h>
> +#include <UncoreCommonIncludes.h>
> +#include <Protocol/UbaCfgDb.h>
> +
> +EFI_STATUS
> +InstallMpTableData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> +);
> +
> +EFI_STATUS
> +InstallPirqData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> +);
> +
> +EFI_STATUS
> +InstallAcpiFixupTableData (
> + IN UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol
> +);
> +
> +#endif // _STATIC_SKU_DATA_DXE_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
> new file mode 100644
> index 0000000000..97a1931c84
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
> @@ -0,0 +1,59 @@
> +## @file
> +# Static Board Data DXE Driver.
> +#
> +# @copyright
> +# Copyright 2018 - 2022 Intel Corporation. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = StaticSkuDataDxeBaseline
> + FILE_GUID = 2C03C058-4305-7829-7E84-C7B3D6232F42
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> +
> + ENTRY_POINT = StaticSkuConfigDataDxeEntry
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = x64
> +#
> +
> +[Sources]
> + StaticSkuDataDxe.c
> + StaticSkuDataDxe.h
> + DeviceDataInstall.c
> + PlatformDeviceDataSRP10nm.c
> + AcpiStaticData.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + WhitleySiliconPkg/SiliconPkg.dec
> + WhitleySiliconPkg/CpRcPkg.dec
> + WhitleyOpenBoardPkg/PlatformPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> + DebugLib
> + IoLib
> + HobLib
> +
> +[Guids]
> + gEfiPlatformInfoGuid
> +
> +[Protocols]
> + gUbaConfigDatabaseProtocolGuid
> +
> +[Depex]
> + gEfiPlatformTypeWilsonCitySMTProtocolGuid OR
> + gEfiPlatformTypeWilsonCityRPProtocolGuid OR
> + gEfiPlatformTypeJunctionCityProtocolGuid
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> index f37093bccd..48b26de427 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
> @@ -30,6 +30,11 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
> }
>
> [Components.X64]
> +#
> +# Currently shared by all platforms
> +#
> +$(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
> +
> #
> # Platform TypeWilsonCityRP
> #
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3 Oram, Isaac W
@ 2022-02-09 3:20 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:20 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel, Gao, Liming, Dong, Eric
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 1/8]
> MinPlatformPkg/AmlGenOffset: Update for python 3
>
> Update for library changes.
> Remove version.
> Changed to not open files as bytes.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Eric Dong <eric.dong@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
> Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py | 13
> ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
> b/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
> index e13ca06471..4799eee1a9 100644
> --- a/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
> +++
> b/Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py
> @@ -32,16 +32,16 @@ if __name__ == '__main__':
> #
> # Create command line argument parser object
> #
> - parser = argparse.ArgumentParser(prog=__prog__, version=__version__,
> usage=__usage__, description=__copyright__, conflict_handler='resolve')
> + parser = argparse.ArgumentParser(prog=__prog__, usage=__usage__,
> + description=__copyright__, conflict_handler='resolve')
> group = parser.add_mutually_exclusive_group(required=True)
> group.add_argument("-e", action="store_true", dest='Encode',
> help='encode file')
> group.add_argument("-d", action="store_true", dest='Decode',
> help='decode file')
> - parser.add_argument("-o", "--output", dest='OutputFile', type=str,
> metavar='filename', help="specify the output filename", required=True)
> + parser.add_argument("-o", "--output", dest='OutputFileName',
> + type=str, metavar='filename', help="specify the output filename",
> + required=True)
> parser.add_argument("-v", "--verbose", dest='Verbose',
> action="store_true", help="increase output messages")
> parser.add_argument("-q", "--quiet", dest='Quiet', action="store_true",
> help="reduce output messages")
> parser.add_argument("--debug", dest='Debug', type=int, metavar='[0-9]',
> choices=range(0,10), default=0, help="set debug level")
> parser.add_argument("--aml_filter", dest='AmlFilterStr', type=str,
> help="specify the AML filter.")
> - parser.add_argument(metavar="input_file", dest='InputFile',
> type=argparse.FileType('rb'), help="specify the input filename")
> + parser.add_argument(metavar="input_file", dest='InputFile',
> + type=argparse.FileType('r'), help="specify the input filename")
>
> #
> # Parse command line arguments
> @@ -49,11 +49,11 @@ if __name__ == '__main__':
> args = parser.parse_args()
>
> if args.Encode:
> - print 'Unsupported'
> + print('Unsupported')
>
> if args.Decode:
> - args.OutputFileName = args.OutputFile
> - args.OutputFile = open(args.OutputFileName, 'wb')
> + args.OutputFileName = os.path.normpath(args.OutputFileName)
> + args.OutputFile = open(args.OutputFileName, 'w')
>
> AmlFilter = args.AmlFilterStr
> filter_pattern = '|'.join(AmlFilter.split(' ')) @@ -69,4 +69,3 @@ if
> __name__ == '__main__':
> if match_obj is not None:
> args.OutputFile.write(line)
> args.OutputFile.close()
> -
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions Oram, Isaac W
@ 2022-02-09 3:20 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:20 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 2/8]
> WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions
>
> Header files for C structures used to build ACPI tables
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h | 91
> +++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h | 30
> +++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h | 37
> ++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h | 206
> ++++++++++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h | 88
> +++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h | 43
> ++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h | 58
> ++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h | 57
> ++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h | 56
> ++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h | 84
> ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h | 58
> ++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h | 50
> +++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h | 45
> +++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h | 120
> ++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h | 87
> +++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h | 48
> +++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h | 59
> ++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTa
> ble.h | 82 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h | 53
> +++++
> Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h | 67
> +++++++
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 7 +-
> Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h |
> 8 +
> 22 files changed, 1430 insertions(+), 4 deletions(-)
>
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
> new file mode 100644
> index 0000000000..0fb913a6a8
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
> @@ -0,0 +1,91 @@
> +/** @file
> + This file describes the contents of the BDAT ACPI.
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _BDAT_H_
> +#define _BDAT_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +
> +#define EFI_BDAT_TABLE_SIGNATURE SIGNATURE_32('B','D','A','T')
> +
> +#define BDAT_PRIMARY_VER 0x0004
> +#define BDAT_SECONDARY_VER 0x0000
> +
> +typedef struct {
> + UINT8 BiosDataSignature[8]; // "BDATHEAD"
> + UINT32 BiosDataStructSize; // sizeof BDAT_STRUCTURE + sizeof
> BDAT_MEMORY_DATA_STRUCTURE + sizeof BDAT_RMT_STRUCTURE
> + UINT16 Crc16; // 16-bit CRC of BDAT_STRUCTURE (calculated with 0
> in this field)
> + UINT16 Reserved;
> + UINT16 PrimaryVersion; // Primary version
> + UINT16 SecondaryVersion; // Secondary version
> + UINT32 OemOffset; // Optional offset to OEM-defined structure
> + UINT32 Reserved1;
> + UINT32 Reserved2;
> +} BDAT_HEADER_STRUCTURE;
> +
> +typedef struct bdatSchemaList {
> + UINT16 SchemaListLength; //Number of Schemas present
> + UINT16 Reserved;
> + UINT16 Year;
> + UINT8 Month;
> + UINT8 Day;
> + UINT8 Hour;
> + UINT8 Minute;
> + UINT8 Second;
> + UINT8 Reserved1;
> + //
> + // This is a dynamic region, where Schema list address is filled out.
> + // Each schema location is 32 bits long and complies with BDAT 4.0 version.
> + //
> +} BDAT_SCHEMA_LIST_STRUCTURE;
> +
> +//BDAT Header Struct which contains information all exisitng BDAT Schemas
> +typedef struct bdatStruct {
> + BDAT_HEADER_STRUCTURE BdatHeader;
> + BDAT_SCHEMA_LIST_STRUCTURE BdatSchemas;
> +} BDAT_STRUCTURE;
> +
> +//
> +// BIOS Data ACPI structure
> +//
> +typedef struct {
> +
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BdatGas;
> +
> +} EFI_BDAT_ACPI_DESCRIPTION_TABLE;
> +
> +//
> +// BIOS Data Parameter Region Generic Address
> +// Information
> +//
> +#define EFI_BDAT_ACPI_POINTER 0x0
> +
> +#define ___INTERNAL_CONVERT_TO_STRING___(a) #a
> +#define CONVERT_TO_STRING(a)
> ___INTERNAL_CONVERT_TO_STRING___(a)
> +
> +//
> +// This is copied from Include\Acpi.h
> +//
> +#define CREATOR_ID_INTEL 0x4C544E49 //"LTNI""INTL"(Intel)
> +#define CREATOR_REV_INTEL 0x20090903
> +
> +#define EFI_ACPI_TABLE_VERSION_ALL
> (EFI_ACPI_TABLE_VERSION_1_0B|EFI_ACPI_TABLE_VERSION_2_0|EFI_ACPI
> _TABLE_VERSION_3_0)
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
> new file mode 100644
> index 0000000000..cfaa9247d8
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
> @@ -0,0 +1,30 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DBG2_H_
> +#define _DBG2_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/DebugPort2Table.h>
> +
> +#pragma pack(1)
> +typedef
> +struct {
> + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Table;
> + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Entry;
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAdressRegister;
> + UINT32 AddressSize;
> + CHAR8 NamespaceString[2];
> +
> +} DBG2_DEBUG_TABLE;
> +#pragma pack()
> +
> +
> +#endif //_DBG2_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
> new file mode 100644
> index 0000000000..56e32c41f5
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
> @@ -0,0 +1,37 @@
> +/** @file
> + This file describes the contents of the ACPI Firmware ACPI Control
> + Structure (FACS). Some additional ACPI values are defined in Acpi1_0.h
> and
> + Acpi2_0.h
> + All changes to the FACS contents should be done in this file.
> +
> + @copyright
> + Copyright 1996 - 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _FACS_H
> +#define _FACS_H
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// FACS Definitions
> +//
> +#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
> +#define EFI_ACPI_GLOBAL_LOCK 0x00000000
> +
> +//
> +// Firmware Control Structure Feature Flags are defined in AcpiX.0.h
> +//
> +#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
> +
> +#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR
> 0x0000000000000000
> +
> +#define EFI_ACPI_OSPM_FLAGS 0x00000000
> +
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
> new file mode 100644
> index 0000000000..004aac350d
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
> @@ -0,0 +1,206 @@
> +/** @file
> + This file describes the contents of the ACPI Fixed ACPI Description Table
> + FADT). Some additional ACPI values are defined in Acpi1_0.h and
> Acpi2_0.h.
> + All changes to the FADT contents should be done in this file.
> +
> + @copyright
> + Copyright 1996 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _FADT_H_
> +#define _FADT_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include "Platform.h"
> +#include <Library/PcdLib.h>
> +
> +//
> +// FADT Definitions
> +//
> +#define EFI_ACPI_OEM_FADT_REVISION 0x00000000
> +//
> +// For ACPI 1.0 supprt
> +// Harwich sets this to #define EFI_ACPI_INT_MODEL 0x01
> +//
> +
> +/*
> +INT_MODEL Field
> +The FADT defines the fixed ACPI information that is needed by the
> operating system as
> +defined in section 5.2.5 of the ACPI 1.0 specification. Currently, this table
> provides a field
> +for INT_MODEL, which was intended to be used to report the interrupt
> mode of the machine.
> +This field is ignored by the Microsoft?Windows?2000 and later operating
> system because the
> +Microsoft Windows 98 operating system only supports programmable
> interrupt controller (PIC) mode.
> +This forces system manufacturers (OEMs) who want to support Windows 98
> to enter a "0" in the INT_MODEL field.
> +This would then preclude using multiple processors on Windows 2000 and
> later versions.
> +Because the INT_MODEL field in the FADT cannot be dynamically updated
> while the machine is running,
> +it cannot be used to report the interrupt mode, and therefore it is ignored
> by Windows 98,
> +and Windows 2000 and later versions.
> +http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx
> +For Watson Creek we set this to 0 and then dynamically update this to 1 in
> the DSDT tables _PIC method and GPIC field.
> +*/
> +#define EFI_ACPI_INT_MODEL 0x0
> +
> +#define EFI_ACPI_PREFERRED_PM_PROFILE 0x04
> +
> +#define EFI_ACPI_SCI_INT 0x0009
> +#define EFI_ACPI_SMI_CMD 0x0
> +
> +#define EFI_ACPI_ACPI_ENABLE 0x00
> +#define EFI_ACPI_ACPI_DISABLE 0x00
> +#define EFI_ACPI_S4_BIOS_REQ 0x00
> +#define EFI_ACPI_CST_CNT 0x00
> +
> +#define EFI_ACPI_PSTATE_CNT 0x00
> +#define EFI_ACPI_GPE1_BASE (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 2)
> +#define EFI_ACPI_P_LVL2_LAT 0x0065
> +#define EFI_ACPI_P_LVL3_LAT 0x03E9
> +//
> +// #define EFI_ACPI_FLUSH_SIZE 0x0400
> +//
> +#define EFI_ACPI_FLUSH_SIZE 0x0000
> +//
> +// #define EFI_ACPI_FLUSH_STRIDE 0x0010
> +//
> +#define EFI_ACPI_FLUSH_STRIDE 0x0000
> +#define EFI_ACPI_DUTY_OFFSET 0x01
> +//
> +// #define EFI_ACPI_DUTY_OFFSET 0x00
> +//
> +#define EFI_ACPI_DUTY_WIDTH 0x00
> +
> +#define EFI_ACPI_DAY_ALRM 0x0D
> +#define EFI_ACPI_MON_ALRM 0x00
> +#define EFI_ACPI_CENTURY 0x32
> +
> +//
> +// IA-PC Boot Architecture Flags, see ACPI 2.0 table specification and
> Acpi6_2.h
> +// No legacy KBC and legcay devices other reported in ASL code
> +//
> +// #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_2_LEGACY_DEVICES |
> EFI_ACPI_6_2_8042)
> +//
> +//#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042
> +#define EFI_ACPI_OS_ASPM_DISABLE (1 << 4)
> +
> +#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042 |
> EFI_ACPI_OS_ASPM_DISABLE
> +
> +//
> +// Fixed Feature Flags, see ACPI 6.2 table specification and Acpi6_2.h
> +//
> +#define EFI_ACPI_FIXED_FEATURE_FLAGS
> (EFI_ACPI_6_2_RESET_REG_SUP | \
> + EFI_ACPI_6_2_RTC_S4 | \
> + EFI_ACPI_6_2_SLP_BUTTON | \
> + EFI_ACPI_6_2_WBINVD | \
> + EFI_ACPI_6_2_PROC_C1 \
> + )
> +
> +//
> +// PM1A Event Register Block Generic Address Information
> +//
> +#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
> +#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS (FixedPcdGet32
> (PcdEfiAcpiPm1aEvtBlkAddress))
> +
> +//
> +// PM1B Event Register Block Generic Address Information
> +//
> +#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
> +#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x00000000
> +
> +//
> +// PM1A Control Register Block Generic Address Information
> +//
> +#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
> +#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS
> (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
> +
> +//
> +// PM1B Control Register Block Generic Address Information
> +//
> +#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
> +#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x00
> +
> +//
> +// PM2 Control Register Block Generic Address Information
> +//
> +#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
> +#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM2_CNT_BLK_ADDRESS
> (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
> +
> +//
> +// Power Management Timer Control Register Block Generic Address
> +// Information
> +//
> +#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
> +#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_PM_TMR_BLK_ADDRESS
> (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
> +
> +//
> +// General Purpose Event 0 Register Block Generic Address
> +// Information
> +//
> +#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100 // size of
> R_PCH_ACPI_GPE0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96 (2*0x80 =
> 0x100)
> +#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
> +#define EFI_ACPI_GPE0_BLK_ADDRESS
> (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x80)
> +
> +//
> +// General Purpose Event 1 Register Block Generic Address
> +// Information
> +//
> +#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0
> +#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0
> +#define EFI_ACPI_GPE1_BLK_ADDRESS 0x0
> +//
> +// Reset Register Generic Address Information
> +//
> +#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
> +#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
> +#define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9
> +#define EFI_ACPI_RESET_VALUE 0x06
> +
> +//
> +// Number of bytes decoded by PM1 event blocks (a and b)
> +//
> +#define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH
> + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
> +
> +//
> +// Number of bytes decoded by PM1 control blocks (a and b)
> +//
> +#define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH
> + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
> +
> +//
> +// Number of bytes decoded by PM2 control block
> +//
> +#define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH /
> 8)
> +
> +//
> +// Number of bytes decoded by PM timer block
> +//
> +#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
> +
> +//
> +// Number of bytes decoded by GPE0 block
> +//
> +#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
> +
> +//
> +// Number of bytes decoded by GPE1 block
> +//
> +#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
> new file mode 100644
> index 0000000000..ad6684acce
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
> @@ -0,0 +1,88 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HMAT_HMAT_H_
> +#define _HMAT_HMAT_H_
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <UncoreCommonIncludes.h>
> +#include "Platform.h"
> +#include "Msars.h"
> +#include "Sllbis.h"
> +#include "Mscis.h"
> +
> +#define
> EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
> +#define EFI_ACPI_OEM_HMAT_REVISION 0x00000001
> +
> +#define EFI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE
> SIGNATURE_32('H', 'M', 'A', 'T')
> +#define MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE 0
> +#define
> SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TY
> PE 1
> +#define MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE 2
> +
> +#define EFI_ACPI_HMAT_MSARS_COUNT (MC_MAX_NODE *
> MAX_CRS_ENTRIES_PER_NODE)
> +#define EFI_ACPI_HMAT_LBIS_COUNT
> (EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES *
> MAX_HMAT_MEMORY_HIERACHY_LEVELS)
> +#define EFI_ACPI_HMAT_MSCIS_COUNT (MC_MAX_NODE *
> MAX_CRS_ENTRIES_PER_NODE)
> +
> +
> +#define HMAT_BW_BASE_UNIT 1024 // 1024 MB/S
> +#define HMAT_LATENCY_BASE_UNIT 1 // 1ns
> +
> +#define HBM_4_NODES_CASE 4
> +#define HBM_2_NODES_CASE 2
> +#define HBM_1_NODE_CASE 1
> +
> +//
> +// In HBM as Cache mode, Cache Flags are only for Last Level of Cache (Flags
> = 1), and 1st Level of Cache (Flags = 2).
> +// So Flag = 0 should be skipped.
> +//
> +#define HMAT_HBM_CACHE_FLAG_OFFSET 1
> +
> +#pragma pack(1)
> +typedef enum {
> + TypeFlatMemoryMode = 1,
> + TypeCacheMemoryMode = 2,
> + TypeHybridMemoryMode = 3,
> +} LBIS_MEMORY_FLAGS_TYPE;
> +
> +typedef struct {
> + UINT8 Valid;
> + UINT32 ElementId;
> + UINT64 MemMapIndexMap;
> + UINT8 Cacheable;
> + UINT64 MemorySideCacheSize;
> + UINT16 NumSmbiosHandles;
> + UINT16 SmbiosHandles[MAX_TYPE17_CACHE_DEVICES];
> + UINT8 PhysicalSocketId;
> +} MEMORY_DOMAIN_LIST_INFO;
> +
> +typedef struct {
> + UINT32 ProcessorDomainNumber;
> + UINT32 MemoryDomainNumber;
> + UINT16 ProcessorDomainList
> [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS];
> + MEMORY_DOMAIN_LIST_INFO MemoryDomainList
> [EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS];
> + UINT8 SncEnabled;
> + UINT8 SncNumOfCluster;
> + UINT8 VirtualNumaEnabled;
> + UINT8 VirtualNumOfCluster;
> + UINT8 ProcessorDomainSocketIdList
> [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS];
> +} HMAT_PROXIMITY_DOMAIN_DATA_STRUCTURE;
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT32 Reserved; // To make the structures 8 byte aligned
> +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
> +
> +typedef struct {
> + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
> HmatHeader;
> + MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE
> Msars[EFI_ACPI_HMAT_MSARS_COUNT];
> + LATENCY_BANDWIDTH_INFO_STRUCTURE
> Lbis[EFI_ACPI_HMAT_LBIS_COUNT];
> + MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE
> MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT];
> +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
> +#pragma pack()
> +
> +#endif /* _HMAT_H_ */
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
> new file mode 100644
> index 0000000000..a3b9ef256a
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
> @@ -0,0 +1,43 @@
> +/** @file
> + This file describes the contents of the ACPI High Precision Event Timer
> Description Table
> + HPET). Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h,
> and Acpi3_0.h
> + All changes to the HPET contents should be done in this file.
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HPET_H_
> +#define _HPET_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/HighPrecisionEventTimerTable.h>
> +
> +//
> +// HPET Definitions
> +//
> +#define EFI_ACPI_OEM_HPET_REVISION 0x00000001
> +
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A701
> +
> +//
> +// Event Timer Block Base Address Information
> +//
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_MEMORY
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
> +#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
> +#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS
> 0x00000000FED00000
> +
> +#define EFI_ACPI_HPET_NUMBER 0x00
> +
> +#define EFI_ACPI_MIN_CLOCK_TICK 0x0080
> +
> +#define EFI_ACPI_HPET_ATTRIBUTES 0x00
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
> new file mode 100644
> index 0000000000..7277961baa
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
> @@ -0,0 +1,58 @@
> +/** @file
> + ACPI Memory mapped configuration space base address Description Table
> + implementation, based on PCI Firmware Specification Revision 3.0 final
> draft,
> + downloadable at http://www.pcisig.com/home
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MCFG_H_
> +#define _MCFG_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include
> <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
> +#include "Platform.h"
> +//
> +// "MCFG" Static Resource Affinity Table
> +//
> +#define
> EFI_ACPI_6_2_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABL
> E_SIGNATURE 0x4746434D
> +
> +//
> +// MCFG Definitions, see specification for details.
> +//
> +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
> +
> +//
> +// Define the number of each table type.
> +// This is where the table layout is modified.
> +//
> +#define
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT MAX_SOCKET
> +
> +//
> +// MCFG Table definition. The table must be defined in a platform
> +// specific manner.
> +//
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +
> +typedef struct {
> +
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HE
> ADER Header;
> +
> +#if
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT > 0
> +
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_
> ADDRESS_ALLOCATION_STRUCTURE Segment[
> +
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT];
> +#endif
> +
> +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE;
> +
> +#pragma pack()
> +
> +#endif // _MCFG_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
> new file mode 100644
> index 0000000000..058ae67717
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
> @@ -0,0 +1,57 @@
> +/** @file
> + This file describes the contents of the MIGT ACPI table.
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MIGT_H_
> +#define _MIGT_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// MIGT ACPI structure
> +//
> +typedef struct {
> +
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + // MIGT Specific Entries
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ControlRegister;
> + UINT32 ControlRegisterValue;
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ActionRegion;
> +
> +} EFI_MIGT_ACPI_DESCRIPTION_TABLE;
> +
> +
> +//
> +// MIGT ACPI Definitions
> +//
> +#define MIGT_SMI_SERVICE_ID 0xFD // Door Bell
> +
> +#define EFI_MIGT_ACPI_TABLE_SIGNATURE
> SIGNATURE_32('M','I','G','T')
> +#define EFI_MIGT_ACPI_DESCRIPTION_TABLE_REVISION 0x01
> +#define EFI_MIGT_ACPI_OEM_REVISION 0x00000000
> +
> +//
> +// MIGT Control Register Generic Address Information
> +//
> +#define EFI_MIGT_CR_ACPI_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_MIGT_CR_ACPI_REGISTER_BIT_WIDTH 0x8
> +#define EFI_MIGT_CR_ACPI_REGISTER_BIT_OFFSET 0x0
> +#define EFI_MIGT_CR_ACPI_SMI_ADDRESS 0xB2
> +
> +//
> +// MIGT Action Region Generic Address Information
> +//
> +#define EFI_MIGT_AR_ACPI_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_MEMORY
> +#define EFI_MIGT_AR_ACPI_REGISTER_BIT_WIDTH 64
> +#define EFI_MIGT_AR_ACPI_REGISTER_BIT_OFFSET 0x0
> +#define EFI_MIGT_AR_ACPI_MEMORY_ADDRESS 0x0
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
> new file mode 100644
> index 0000000000..a088d66ea5
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
> @@ -0,0 +1,56 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MSARS_H_
> +#define _MSARS_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT16 ProcessorDomainValid:1;
> + UINT16 MemoryDomainValid:1;
> + UINT16 ReservationHint:1;
> + UINT16 Reserved_15_3:13;
> +} MSARS_FLAGS_BITS;
> +
> +typedef union {
> + UINT16 Value;
> + MSARS_FLAGS_BITS Bits;
> +} MSARS_FLAGS;
> +
> +typedef struct {
> + UINT16 Type;
> + UINT16 Reserved_2_4;
> + UINT32 Length;
> + MSARS_FLAGS Flags;
> + UINT16 Reserved_10_12;
> + UINT32 ProcessorProximityDomain;
> + UINT32 MemoryProximityDomain;
> + UINT32 Reserved_20_24;
> + UINT64 AddrBase; //System Physical Address Range Base
> + UINT64 AddrLength; //System Physical Address Range Length
> +} MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE;
> +#pragma pack()
> +
> +// MSARS_INIT Macro
> +// Used to initialize MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE
> +#define MSARS_INIT() { \
> + (UINT16) MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE, \
> + (UINT16) 0, \
> + (UINT32) sizeof(MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE), \
> + {(UINT16) 0}, \
> + (UINT16) 0, \
> + (UINT32) 0, \
> + (UINT32) 0, \
> + (UINT32) 0, \
> + (UINT64) 0, \
> + (UINT64) 0, \
> + },
> +
> +#endif /* _MSARS_H_ */
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
> new file mode 100644
> index 0000000000..44d80910e2
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
> @@ -0,0 +1,84 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MSCIS_H_
> +#define _MSCIS_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define EFI_ACPI_HMAT_CACHE_LEVEL_NONE 0
> +#define EFI_ACPI_HMAT_ONE_LEVEL_CACHE 1
> +#define EFI_ACPI_HMAT_TWO_LEVEL_CACHE 2
> +#define EFI_ACPI_HMAT_THREE_LEVEL_CACHE 3
> +
> +#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_NONE 0
> +#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_DIRECT_MAPPED 1
> +#define
> EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_COIMPLEX_CACHE_INDEXING 2
> +
> +#define EFI_ACPI_HMAT_WRITE_POLICY_NONE 0
> +#define EFI_ACPI_HMAT_WRITE_POLICY_WB 1
> +#define EFI_ACPI_HMAT_WRITE_POLICY_WT 2
> +
> +#define HBM_CACHE_LINE_SIZE 72
> +#define DDR4_CACHE_LINE_SIZE 64
> +
> +//
> +// MAX_CH = MAX_IMC * MAX_MC_CH
> +// MAX_IMC = Maximum memory controllers per socket
> +// MAX_MC_CH = Max number of channels per MC
> +// For each channel, 1 DDR can act as 2LM cache. This is the maximum
> number of cache devices per memory domain
> +//
> +#define MAX_TYPE17_CACHE_DEVICES MAX_CH
> +
> +#pragma pack(1)
> +typedef struct {
> + UINT32 TotalCacheLevels:4;
> + UINT32 CacheLevel:4;
> + UINT32 CacheAssociativity:4;
> + UINT32 WritePolicy:4;
> + UINT32 CacheLineSize:16;
> +} CACHE_ATTRIBUTES_BITS;
> +
> +typedef union {
> + UINT32 Data;
> + CACHE_ATTRIBUTES_BITS Bits;
> +} CACHE_ATTRIBUTES;
> +
> +typedef struct {
> + UINT16 Type;
> + UINT16 Reserved_2_4;
> + UINT32 Length;
> + UINT32 MemoryProximityDomain;
> + UINT32 Reserved_12_16;
> + UINT64 MemorySideCacheSize;
> + CACHE_ATTRIBUTES CacheAttributes;
> + UINT16 Reserved_28_30;
> + UINT16 NumSmbiosHandles;
> + UINT16 SmbiosHandles [MAX_TYPE17_CACHE_DEVICES];
> +} MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE;
> +#pragma pack()
> +
> +// MSCIS_INIT Macro
> +// Used to initialize MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE
> +#define MSCIS_INIT() { \
> + (UINT16) MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE, \
> + (UINT16) 0, \
> + (UINT32) sizeof(MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE), \
> + (UINT32) 0, \
> + (UINT32) 0, \
> + (UINT64) 0, \
> + {(UINT32) 0}, \
> + (UINT16) 0, \
> + (UINT16) 0, \
> + },
> +/*
> + SMBIOS handles not used for 2LM. Will be added for HBM
> + {(UINT16) 0}, \
> + },
> +*/
> +#endif /* _MSCIS_H_ */
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
> new file mode 100644
> index 0000000000..31c6e0f580
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
> @@ -0,0 +1,58 @@
> +/** @file
> + This file describes the contents of the ACPI Maximum System
> Characteristics Table (MSCT).
> + Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h, and
> Acpi3_0.h.
> + All changes to the MSCT contents should be done in this file.
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MSCT_H_
> +#define _MSCT_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include <Platform.h>
> +#include <UncoreCommonIncludes.h>
> +
> +//
> +// MSCT Definitions, see specification for details.
> +//
> +#ifndef
> EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE
> +#define
> EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE
> 0x5443534D
> +#endif
> +#define
> EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION
> 0x01
> +#define EFI_ACPI_OEM_MSCT_REVISION 0x00000001
> +#define
> EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_R
> EVISION 0x01
> +
> +
> +//
> +// MSCT Table definition
> +//
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT8 Revision;
> + UINT8 Length;
> + UINT32 ProxDomRangeLow;
> + UINT32 ProxDomRangeHigh;
> + UINT32 MaxProcessorCapacity;
> + UINT64 MaxMemoryCapacity;
> +}
> EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT32 OffsetProxDomInfo;
> + UINT32 MaxNumProxDom;
> + UINT32 MaxNumClockDom;
> + UINT64 MaxPhysicalAddress;
> + EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE
> ProxDomInfoStructure[MAX_SOCKET];
> +} EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE;
> +
> +#pragma pack()
> +
> +#endif //_MSCT_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
> new file mode 100644
> index 0000000000..5ea51b6d59
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
> @@ -0,0 +1,50 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// The version of NvDimm F/W Interface Table (Nfit) supported has been
> updated to ASWG-ECR-Draft4-RC6_93.doc
> +// This file contains definitions for Acpi side for the Nfit creation and
> publication of Nfit tables.
> +// A BIG NOTE: When ever the NVDIMM_FW_INTERFACE_TABLE defined
> either here or what is in Nfit.h of CrystalRidge Protocol driver
> +// changes, the same changes need to relect in both the files.
> +
> +#ifndef _NFIT_DEFS_H_
> +#define _NFIT_DEFS_H_
> +
> +#include <IndustryStandard/Acpi62.h>
> +
> +#define NVDIMM_FW_INTERFACE_TABLE_SIGNATURE
> EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGN
> ATURE
> +#define NVDIMM_FW_INTERFACE_TABLE_REVISION
> EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION
> +
> +#define MAX_NFIT_SIZE 0x18000
> +
> +
> +//
> +// NVDIMM Firmware Interface Table struct
> +// IMPORTANT NOTE: Num of various sub-table fields of the Nfit has been
> eliminated in the latest Nfit Spec (0.8k)
> +// And also since there is NO memory allocation scheme for Nfit (all globals),
> Adding a buffer NfitTables with the,
> +// max nfit size currently set to 4k. Will need to watch if we will ever
> overrun this buffer. It is expected that
> +// Nfit parser will need to parse the NfitTables field to understand the
> various other Nfit Tables in this buffer
> +// based on the Type and Length field of these tables.
> +//
> +#pragma pack(1)
> +typedef struct _NVDIMM_FW_INT_TBL {
> + UINT32 Signature; // 'NFIT' should be the signature for this
> table
> + UINT32 Length; // Length in bytes fir the entire table
> + UINT8 Revision; // Revision # of this table, initial is '1'
> + UINT8 Checksum; // Entire Table Checksum must sum to 0
> + UINT8 OemID[6]; // OemID
> + UINT8 OemTblID[8]; // Should be Manufacturer's Model #
> + UINT32 OemRevision; // Oem Revision of for Supplied OEM
> Table ID
> + UINT32 CreatorID; // Vendor ID of the utility that is creating
> this table
> + UINT32 CreatorRev; // Revision of utility that is creating this
> table
> + UINT32 Reserved;
> + UINT8 NfitTables[MAX_NFIT_SIZE]; // See Description above
> (IMPORTANT).
> +} NVDIMM_FW_INTERFACE_TABLE;
> +#pragma pack()
> +
> +#endif // _NFIT_DEFS_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
> new file mode 100644
> index 0000000000..ceb0684f17
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
> @@ -0,0 +1,45 @@
> +/** @file
> + Pcat.h
> +
> + @copyright
> + Copyright 2014 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCAT_DEFS_H_
> +#define _PCAT_DEFS_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +/// @brief PCAT Signature to put in table header
> +#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_SIGNATURE
> SIGNATURE_32('P', 'C', 'A', 'T')
> +
> +#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_REVISION
> 0x11
> +
> +#define MAX_PCAT_SIZE 0x200
> +
> +typedef struct {
> + UINT32 Signature; // 'PCAT' should be the signature for this
> table
> + UINT32 Length; // Length in bytes for the entire table
> + UINT8 Revision; // Revision # of this table, initial is '1'
> + UINT8 Checksum; // Entire Table Checksum must sum to 0
> + UINT8 OemID[6]; // OemID
> + UINT8 OemTblID[8]; // Should be Manufacturer's Model #
> + UINT32 OemRevision; // Oem Revision of for Supplied OEM
> Table ID
> + UINT32 CreatorID; // Vendor ID of the utility that is creating
> this table
> + UINT32 CreatorRev; // Revision of utility that is creating this
> table
> + UINT32 Reserved; // Alignement for size modulo 8 = 0
> + UINT8 PCATTables[MAX_PCAT_SIZE];
> +} NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE,
> *PNVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE;
> +
> +/// @brief Layout of SSKU Attribute Extension Table header
> +typedef struct {
> + UINT16 Type; // Type for Mgmt Info Struct, type should be
> 3
> + UINT16 Length; // Length in Bytes for Entire SSKU Attribute
> Extension Table size.
> + UINT16 Rsvd;
> + UINT16 VendorID; // Vendor ID
> + EFI_GUID Guid; // Intel defined SSKU Attribute Extension
> Table. guid: F93032E5-B045-40ef-91C8-F02B06AD948D
> +} NVDIMM_SSKU_ATTR_EXT_TABLE, *PNVDIMM_SSKU_ATTR_EXT_TABLE;
> +
> +#endif //_PCAT_DEFS_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
> new file mode 100644
> index 0000000000..923483f2da
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
> @@ -0,0 +1,120 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _ACPI_PMTT_H_
> +#define _ACPI_PMTT_H_
> +
> +//
> +// Includes
> +//
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/SmBios.h>
> +#include <Platform.h>
> +#include <UncoreCommonIncludes.h>
> +
> +//
> +// PMTT Definitions
> +//
> +#define ACPI_PMTT_TABLE_SIGNATURE 0x54544D50
> +#define ACPI_PMTT_TABLE_REVISION 0x02
> +#define ACPI_PMTT_OEM_REVISION 1
> +
> +#define PMTT_TOP_LEVEL_AGGREGATOR_DEVICE 0x0001
> +#define PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY 0x0002
> +#define PMTT_AEP_DIMM 0x0004
> +
> +#define ACPI_TOP_LEVEL_SOCKET 0x00
> +#define ACPI_TOP_LEVEL_IMC 0x01
> +#define PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM 0x02
> +#define ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE 0xFF
> +
> +// PMTT GUID variables
> +#define PMTT_TYPE_DIE_GUID { 0xA2555053, 0xCDE4, 0x40A5, {0x80, 0x76,
> 0x00, 0xE3, 0xAB, 0xA6, 0xCA, 0xA7} }
> +#define PMTT_TYPE_CHANNEL_GUID { 0x23BF9281, 0xE69c, 0x471F, {0xB2,
> 0x99, 0xB0, 0x98, 0x2B, 0x2F, 0x55, 0xF9} }
> +#define PMTT_TYPE_SLOT_GUID { 0xFDCB2a68, 0xC203, 0x4312, {0xB2,
> 0x91, 0xB8, 0xE8, 0x62, 0x86, 0xC2, 0xC1} }
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + UINT32 SmbiosHandle;
> +} ACPI_PMTT_DIMM_DEVICE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + GUID TypeUuid;
> + UINT16 SlotId;
> + UINT16 Rsvd2;
> + ACPI_PMTT_DIMM_DEVICE Dimm;
> +} ACPI_PMTT_SLOT_DEVICE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + GUID TypeUuid;
> + UINT16 ChannelId;
> + UINT16 Rsvd2;
> + ACPI_PMTT_SLOT_DEVICE Slot[MAX_DIMM];
> +} ACPI_PMTT_CHANNEL_DEVICE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + UINT16 ImcId;
> + UINT16 Rsvd2;
> + ACPI_PMTT_CHANNEL_DEVICE Channel[MAX_MC_CH];
> +} ACPI_PMTT_IMC_DEVICE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + GUID TypeUuid;
> + UINT16 DieId;
> + UINT16 Rsvd2;
> + ACPI_PMTT_IMC_DEVICE Imc[MAX_IMC];
> +} ACPI_PMTT_DIE_DEVICE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Rsvd;
> + UINT16 Length;
> + UINT16 Flag;
> + UINT16 Rsvd1;
> + UINT32 NumOfMemoryDevices;
> + UINT16 SckIdent;
> + UINT16 Rsvd2;
> + ACPI_PMTT_DIE_DEVICE Die[MAX_DIE];
> +} ACPI_PMTT_SOCKET_DEVICE;
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT32 NumOfMemoryDevices;
> + ACPI_PMTT_SOCKET_DEVICE Socket[MAX_SOCKET];
> +} ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE;
> +
> +#endif // _ACPI_PMTT_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
> new file mode 100644
> index 0000000000..c119a0f712
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
> @@ -0,0 +1,87 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2017 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SLLBIS_H_
> +#define _SLLBIS_H_
> +
> +#include <UncoreCommonIncludes.h>
> +
> +#define EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS
> MC_MAX_NODE
> +#define EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS
> (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE)
> +
> +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_MEMORY 0
> +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_LAST_LEVEL_MEMORY 1
> +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_FIRST_LEVEL_MEMORY 2
> +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_SECOND_LEVEL_MEMORY
> 3
> +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_THIRD_LEVEL_MEMORY 4
> +
> +
> +#define EFI_ACPI_HMAT_ACCESS_LATENCY 0
> +#define EFI_ACPI_HMAT_READ_LATENCY 1
> +#define EFI_ACPI_HMAT_WRITE_LATENCY 2
> +#define EFI_ACPI_HMAT_ACCESS_BANDWIDTH 3
> +#define EFI_ACPI_HMAT_READ_BANDWIDTH 4
> +#define EFI_ACPI_HMAT_WRITE_BANDWIDTH 5
> +
> +#define EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES 4
> +#define EFI_ACPI_HMAT_NUMBER_SLLBIS_DATA_TYPES 6
> +
> +#define EFI_ACPI_HMAT_ELEMENT_BASE_UNIT_VALUE 10
> +
> +#define MAX_HMAT_MEMORY_HIERACHY_LEVELS 3 // Flat, Cache, and
> Hybrid
> +#define HMAT_PERFORMANCE_UNIFORM_ACCESS 1
> +#define HMAT_PERFORMANCE_NONUNIFORM_ACCESS 0
> +
> +#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_LENGTH 4
> +#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_START_BIT
> 4
> +
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT16 Type;
> + UINT16 Reserved_2_4;
> + UINT32 Length;
> + UINT8 Flags;
> + UINT8 DataType;
> + UINT16 Reserved_10_12;
> + UINT32 InitiatorProximityDomainsNumber;
> + UINT32 TargetProximityDomainsNumber;
> + UINT32 Reserved_20_24;
> + UINT64 EntryBaseUnit;
> + UINT32
> InitiatorProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_D
> OMAINS];
> + UINT32
> TargetProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOM
> AINS];
> + UINT16
> RelativeDistanceEntry[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAI
> NS][EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS];
> +} LATENCY_BANDWIDTH_INFO_STRUCTURE;
> +#pragma pack()
> +
> +// LBIS Macros
> +// Used to initialize LATENCY_BANDWIDTH_INFO_STRUCTURE
> +#define LBIS_START() { \
> + (UINT16)
> SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TY
> PE, \
> + (UINT16) 0, \
> + (UINT32) sizeof(LATENCY_BANDWIDTH_INFO_STRUCTURE), \
> + (UINT8) 0, \
> + (UINT8) 0, \
> + (UINT16) 0, \
> + (UINT32) 0, \
> + (UINT32) 0, \
> + (UINT32) 0, \
> + (UINT64) 0, \
> + {(UINT32) 0}, \
> + {(UINT32) 0}, \
> + {
> +
> +#define RELATIVE_DISTANCE() \
> + {(UINT16) 0},
> +
> +#define LBIS_END() \
> + }, \
> +},
> +
> +#endif /* _SLLBIS_H_ */
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
> new file mode 100644
> index 0000000000..90ea2c24cb
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
> @@ -0,0 +1,48 @@
> +/** @file
> + This file describes the contents of the ACPI Serial Port Console Redirection
> + Table (SPCR). Some additional ACPI 2.0 values are defined in Acpi2_0.h.
> + All changes to the Spcr contents should be done in this file.
> +
> + @copyright
> + Copyright 1999 - 2002 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SPCR_H_
> +#define _SPCR_H_
> +
> +//
> +// SPCR Definitions, see TBD specification for details.
> +//
> +
> +#define EFI_ACPI_OEM_SPCR_REVISION 0x00000000 // TBD
> +
> +#define EFI_ACPI_INTERFACE_TYPE 0x00 // full 16550 interface.
> +
> +//
> +// Base Address
> +//
> +#define EFI_ACPI_BASE_ADDRESS_ADDRESS_SPACE_ID
> EFI_ACPI_6_2_SYSTEM_IO
> +#define EFI_ACPI_BASE_ADDRESS_BIT_WIDTH 0x08
> +#define EFI_ACPI_BASE_ADDRESS_BIT_OFFSET 0x00
> +#define EFI_ACPI_BASE_ADDRESS_ADDRESS 0x0000000000000000 //
> Updated at run time
> +
> +#define EFI_ACPI_INTERRUPT_TYPE 0x03 // Dual-8259 and IOAPIC
> +#define EFI_ACPI_IRQ 0x04 // Updated at run time
> +#define EFI_ACPI_GLOBAL_SYSTEM_INTERRUPT 0x04 // Updated at
> run time
> +#define EFI_ACPI_BAUD_RATE 0x07 // 115200
> +#define EFI_ACPI_PARITY 0x00 // No parity
> +#define EFI_ACPI_STOP_BITS 0x00 // 0 stop bit
> +#define EFI_ACPI_FLOW_CONTROL 0x00 // No flow control
> +#define EFI_ACPI_TERMINAL_TYPE 0x03 // ANSI
> +#define EFI_ACPI_LANGUAGE 0x00 // Reserved
> +#define EFI_ACPI_PCI_DEVICE_ID 0xFFFF
> +#define EFI_ACPI_PCI_VENDOR_ID 0xFFFF
> +#define EFI_ACPI_PCI_BUS_NUMBER 0x00
> +#define EFI_ACPI_PCI_DEVICE_NUMBER 0x00
> +#define EFI_ACPI_PCI_FUNCTION_NUMBER 0x00
> +#define EFI_ACPI_PCI_FLAGS 0x00000000
> +#define EFI_ACPI_PCI_SEGMENT 0x00
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
> new file mode 100644
> index 0000000000..576c390bd6
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
> @@ -0,0 +1,59 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SPMI_H_
> +#define _SPMI_H_
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// Spmi Definitions, see specification for details.
> +//
> +#ifndef
> EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIG
> NATURE
> +#define
> EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIG
> NATURE 0x494D5053
> +#endif
> +
> +#define
> EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISIO
> N 0x05
> +#define EFI_ACPI_OEM_SPMI_REVISION
> 0x00000001
> +#define EFI_ACPI_SPMI_SPECIFICATION_REVISION
> 0x0200
> +
> +
> +//
> +// SPMI Table definition
> +//
> +#pragma pack(1)
> +
> +#define KEYBOARD_CONTROLLER_STYLE 0x01
> +#define SYSTEM_IO 0x01
> +#define IPMI_DEFAULT_IO_BASE 0xCA2
> +
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT8 InterfaceType; // 36
> + UINT8 Reserved37; // 37
> + UINT16 SpecificationRevision; // 38 - 39
> + UINT8 InterruptType; // 40
> + UINT8 GPE; // 41
> + UINT8 Reserved42; // 42
> + UINT8 PciDeviceFlag; // 43
> + UINT32 GlobalSystemInterrupt; // 44 - 47
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress;
> // 48 - 59
> + UINT8 UidByte1; // 60 LSB
> + UINT8 UidByte2; // 61
> + UINT8 UidByte3; // 62
> + UINT8 UidByte4; // 63 MSB
> + UINT8 Reserved64; // 64
> +} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE;
> +
> +
> +#pragma pack()
> +
> +#endif //_SPMI_H_
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescription
> Table.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescription
> Table.h
> new file mode 100644
> index 0000000000..fe25f5b4e3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescription
> Table.h
> @@ -0,0 +1,82 @@
> +/** @file
> + ACPI Watchdog Description Table as defined in Intel
> + ICH Family Watchdog Timer (WDT) Application Note (AP-725)
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_
> +#define _WATCH_DOG_DESCRIPTION_TABLE_H_
> +
> +//
> +// Include files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// Ensure proper structure formats
> +//
> +#pragma pack(1)
> +//
> +// WDDT structure ACPI 6.2 compliant
> +//
> +typedef struct {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT16 SpecVersion;
> + UINT16 TableVersion;
> + UINT16 Vid;
> + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress;
> + UINT16 TimerMaxCount;
> + UINT16 TimerMinCount;
> + UINT16 TimerCountPeriod;
> + UINT16 Status;
> + UINT16 Capability;
> +} EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE;
> +
> +//
> +// "WDDT" Watchdog Description Table signatures
> +//
> +#define EFI_ACPI_WDDT_SIGNATURE 0x54444457
> +
> +#pragma pack()
> +
> +//
> +// WDDT Revision
> +//
> +#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01
> +
> +//
> +// WDDT Spec Version
> +//
> +#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01
> +
> +//
> +// WDDT Description Table Version
> +//
> +#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01
> +
> +//
> +// WDT Status
> +//
> +#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
> +#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
> +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
> +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
> +#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
> +#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
> +#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
> +#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
> +
> +//
> +// WDT Capability
> +//
> +#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
> +#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
> +#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
> +#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
> +#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
> new file mode 100644
> index 0000000000..9ffe2c6e89
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
> @@ -0,0 +1,53 @@
> +/** @file
> + This file describes the contents of the ACPI Watchdog Description
> + Table (WDDT). Some additional ACPI values are defined in Acpi1_0.h and
> + Acpi2_0.h.
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _WDDT_H
> +#define _WDDT_H
> +
> +//
> +// Statements that include other files
> +//
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// WDDT Definitions, ACPI 6.2
> +//
> +#define EFI_ACPI_WDDT_DESCRIPTION_TABLE_REVISION 1
> +#define EFI_ACPI_OEM_WDDT_REVISION 0x00000001
> +#define EFI_ACPI_WDDT_SPEC_VERSION 0x0100
> +#define EFI_ACPI_WDDT_TABLE_VERSION 0x0100
> +#define EFI_ACPI_WDDT_TIMER_MAX_COUNT 0x003f
> +#define EFI_ACPI_WDDT_TIMER_MIN_VALUE 0x0004
> +#define EFI_ACPI_WDDT_TIMER_PERIOD_COUNT 600
> +//
> +// WDDT_STATUS bits
> +//
> +#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001
> +#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002
> +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000
> +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004
> +#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800
> +#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000
> +#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000
> +#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000
> +
> +//
> +// WDDT Capability bits
> +//
> +#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001
> +#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002
> +#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004
> +#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008
> +#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010
> +
> +#pragma pack()
> +
> +#endif
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
> new file mode 100644
> index 0000000000..112e162931
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
> @@ -0,0 +1,67 @@
> +/** @file
> +
> + @copyright
> + Copyright 2017 - 2020 Intel Corporation.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +
> +#ifndef _WSMT_H_
> +#define _WSMT_H_
> +
> +//
> +// Statements that include other files
> +//
> +
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// signature "WSMT"
> +//
> +
> +#define ACPI_WSMT_SIGNATURE 0x544D5357
> +#define ACPI_WSMT_LENGTH 40
> +#define ACPI_OEM_WSMT_REVISION 0x00000000
> +#define EFI_ACPI_WSMT_REVISION 0x00000001
> +#define WSMT_PROTECTION_FLAG (BIT0 | BIT1 | BIT2 )
> +
> +
> +#pragma pack(1)
> +
> +typedef union {
> + struct {
> + //
> + //BIT0:
> + //If set, expresses that for all synchronous SMM entries,
> + //SMM will validate that input and output buffers lie entirely within the
> expected fixed memory regions.
> + //
> + UINT32 FixedCommBuffers:1;
> + //
> + //BIT1: COMM_BUFFER_NESTED_PTR_PROTECTION
> + //If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and
> + //output pointers embedded within the fixed communication buffer only
> refer to address ranges
> + //that lie entirely within the expected fixed memory regions.
> + //
> + UINT32 CommBufferNestedPointerProtection:1;
> + //
> + //BIT2: SYSTEM_RESOURCE_PROTECTION
> + //Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
> + //
> + UINT32 SystemResourceProtection:1;
> + UINT32 Reserved:29;
> + } Bits;
> + UINT32 Flags;
> +} EFI_ACPI_WSMT_PROTECTION_FLAGS;
> +
> +//
> +// WSMT ACPI table
> +//
> +typedef struct _ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE {
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + EFI_ACPI_WSMT_PROTECTION_FLAGS ProtectionFlags;
> +} ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE;
> +
> +#pragma pack()
> +
> +#endif //_WSMT_H_
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
> index 5e27d9beb4..4d416325ae 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
> @@ -16,8 +16,8 @@
> PACKAGE_VERSION = 0.91
>
> [Includes]
> - Include
> - Include/Protocol
> + Include
> + Include/Protocol
>
> #TODO: Move these generated temp files into include.
> Uba/BoardInit/Dxe
> @@ -159,8 +159,7 @@
>
> [PcdsFixedAtBuild]
>
> -#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid'
> used here to it, or move these values to the SocketPkg where the GUID is
> defined
> -# Using a GUID defined in another .DEC file is a violation of the UEFI
> packaging standards.
> +
> gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress|0x00000500|UINT
> 32|0x00000031
>
> gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000
> |UINT32|0x3000000E
> gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000
> |UINT32|0x3000000F
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
> b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
> index 0ea93e9a78..7af4eb72f6 100644
> --- a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
> +++ b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h
> @@ -80,6 +80,8 @@
> #define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max
> number of memory nodes
> #endif
>
> +#define MAX_CRS_ENTRIES_PER_NODE 8 // Max number of
> ranges allowed on a memory node
> +
> #ifndef TOTAL_CB3_DEVICES
> #define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS *
> MAX_SOCKET. Note: this covers up to 8S.
> #endif
> @@ -108,4 +110,10 @@
> #define MAX_B2P_MAILBOX_GROUPS 32
> #endif // !MAX_B2P_MAILBOX_GROUPS
>
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL"
> +#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009
> +
> #endif
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL Oram, Isaac W
@ 2022-02-09 3:21 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:21 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 3/8]
> WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
>
> LBG ACPI DSDT content
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.as
> l | 833 ++++++++++++++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHd
> a.asl | 307 ++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNv
> s.asl | 271 +++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPci
> e.asl | 203 +++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSa
> ta.asl | 50 ++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXh
> ci.asl | 558 +++++++++++++
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_
> ADR.asl | 15 +
>
> Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trace
> HubDebug.asl | 150 ++++
> Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 1 +
> 28 files changed, 2673 insertions(+)
>
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> new file mode 100644
> index 0000000000..a8ea35534c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.
> asl
> @@ -0,0 +1,833 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Register/PchRegsPcr.h>
> +
> +Name (PNVB, 0xFFFF0000) // PCH NVS Base address
> +Name (PNVL, 0xAA55) // PCH NVS Length
> +Include ("PchNvs.asl")
> +
> +//
> +// Trace Hub debug library
> +// Include it earlier so the debug function can be used as soon as possible
> +//
> +Include ("TraceHubDebug.asl")
> +
> +Name(SPTH,1)
> +Name(SPTL,2)
> +Method(PCHV) {
> + If(LEqual(PCHS, 1)) { Return (SPTH) } // series=H -> SPT-H
> + If(LEqual(PCHS, 2)) { Return (SPTL) } // series=LP -> SPT-LP
> + Return (0)
> +}
> +
> +//
> +// This PME event (PCH's GPE 6Dh) is received when any PCH internal
> device with
> +// PCI Power Management capabilities on bus 0 asserts the equivalent of
> the PME# signal.
> +//
> +Scope(\_GPE) {
> + Method(_L6D, 0, Serialized) {
> + \_SB.PC00.XHCI.GPEH()
> + \_SB.PC00.CAVS.GPEH()
> + \_SB.PC00.GBE1.GPEH()
> + }
> +}
> +
> +Scope (\_SB.PC00) {
> +
> + //
> + // PCH reserved resource
> + //
> + Device(PRRE) {
> + Name(_HID,EISAID("PNP0C02")) // motherboard resource
> + Name(_UID,"PCHRESV")
> + Name(_STA,0x3) // device present and decodes its resources, but not to
> be displayed in OSPM
> +
> + Method(_CRS,0,Serialized)
> + {
> + Name(BUF0,ResourceTemplate(){
> + //
> + // PCH RESERVED MMIO RANGE
> + // 0xFD000000 to 0xFE7FFFFF
> + // to skip over address range that might be claimed by the GPIO, Intel
> Serial IO, Thermal, TraceHub and CIO2 devices
> + // need to split this into 5 ranges
> + // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC
> device.
> + //
> + Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 -
> 0xFDABFFFF
> + // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3
> + Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 -
> 0xFDADFFFF, only cover GPIO_COMM2 range
> + // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1
> + Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 -
> 0xFDFFFFFF
> + Memory32Fixed(ReadWrite,0xFE000000,0x00010000) // 0xFE000000 -
> 0xFE00FFFF
> + Memory32Fixed(ReadWrite,0xFE011000,0x0000f000) // 0xFE011000 -
> 0xFE01FFFF
> + // Skip 0xFE020000 - 0xFE035FFF for Serial IO
> + Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 -
> 0xFE03BFFF
> + // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode
> + Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 -
> 0xFE3FFFFF
> + // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode
> + Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 -
> 0xFE7FFFFF
> + })
> + Return(BUF0)
> + }
> + }
> + Device(IOTR) {
> + //
> + // This device claims IO range reserved for IO traps
> + // to prevent OS from reusing it for other purposes
> + //
> + Name(_HID,EISAID("PNP0C02"))
> + Name(_UID,"IoTraps")
> + Name(BUF0,ResourceTemplate(){
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG0)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG1)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG2)
> + Io(Decode16,0x0,0x0,0x1,0xFF,TAG3)
> + })
> + CreateWordField(BUF0,TAG0._MIN,AMI0)
> + CreateWordField(BUF0,TAG0._MAX,AMA0)
> + CreateWordField(BUF0,TAG1._MIN,AMI1)
> + CreateWordField(BUF0,TAG1._MAX,AMA1)
> + CreateWordField(BUF0,TAG2._MIN,AMI2)
> + CreateWordField(BUF0,TAG2._MAX,AMA2)
> + CreateWordField(BUF0,TAG3._MIN,AMI3)
> + CreateWordField(BUF0,TAG3._MAX,AMA3)
> + CreateByteField(BUF0,TAG0._LEN,LEN0)
> + CreateByteField(BUF0,TAG1._LEN,LEN1)
> + CreateByteField(BUF0,TAG2._LEN,LEN2)
> + CreateByteField(BUF0,TAG3._LEN,LEN3)
> + Method(_CRS) {
> + Store(ITA0,AMI0);Store(ITA0,AMA0)
> + Store(ITA1,AMI1);Store(ITA1,AMA1)
> + Store(ITA2,AMI2);Store(ITA2,AMA2)
> + Store(ITA3,AMI3);Store(ITA3,AMA3)
> + if(LNotEqual(ITS0,1)) { Store(0, LEN0) }
> + if(LNotEqual(ITS1,1)) { Store(0, LEN1) }
> + if(LNotEqual(ITS2,1)) { Store(0, LEN2) }
> + if(LNotEqual(ITS3,1)) { Store(0, LEN3) }
> + return (BUF0)
> + }
> + }
> +
> +
> + //
> + // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory
> Region declare,
> + // it's better to be declared as early as possible since it's widely used in
> whole ACPI name space.
> + // Please add any code which needs to reference any register of it after
> this
> + //
> + Scope (\_SB.PC00.LPC0) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> +
> + OperationRegion(LPC, PCI_Config, 0x00, 0x100)
> + Field(LPC, AnyAcc, NoLock, Preserve)
> + {
> + Offset(0x02),
> + CDID, 16,
> + Offset(0x08),
> + CRID, 8,
> + Offset(0x80),
> + IOD0, 8,
> + IOD1, 8,
> + Offset(0xA0),
> + , 9,
> + PRBL, 1,
> + Offset(0xAC),
> + , 8,
> + , 8,
> + XUSB, 1,
> + Offset(0xB8),
> + , 22,
> + GR0B, 2,
> + , 8,
> + Offset(0xBC),
> + , 2,
> + GR19, 2,
> + , 28,
> + Offset(0xDC),
> + , 2,
> + ESPI, 1,
> + }
> + }
> +
> + //
> + // PCH Power Management Controller
> + //
> + Scope(\_SB.PC00.PMC1) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> +
> + OperationRegion(PMCB, PCI_Config, 0x00, 0x100)
> + Field(PMCB, AnyAcc, NoLock, Preserve) {
> + VDID, 32,
> + Offset(0x40),
> + , 8,
> + ACBA, 8,
> + Offset(0x48),
> + , 12,
> + PWBA, 20,
> + }
> + }
> +
> + //
> + // SMBus Controller - Device 31, Function 4
> + //
> + Device(SBUS) {
> + Name(_ADR,0x001F0004)
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> + }
> +}
> +
> +Scope(\)
> +{
> + //
> + // PCR Register Access Methods
> + //
> + // PCR Dword Read
> + // arg0: PID
> + // arg1: Offset
> + //
> + Method (PCRR, 2, Serialized) {
> + Add (ShiftLeft (arg0, 16), arg1, Local0)
> + Add (SBRG, Local0, Local0)
> + OperationRegion (PCR0, SystemMemory, Local0, 0x4)
> + Field(PCR0,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT0, 32
> + } // End Field PCR0
> + Return (DAT0)
> + } // End Method PCRR
> +
> + //
> + // PCR Dword Write
> + // arg0: PID
> + // arg1: Offset
> + // arg2: write data
> + //
> + Method (PCRW, 3, Serialized) {
> + Add (ShiftLeft (arg0, 16), arg1, Local0)
> + Add (SBRG, Local0, Local0)
> + OperationRegion (PCR0, SystemMemory, Local0, 0x4)
> + Field(PCR0,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT0, 32
> + } // End Field PCR0
> + Store (arg2, DAT0)
> +
> + // read back for PCR back to back limitation
> + OperationRegion (PCR1, SystemMemory, ADD (SBRG, 0x00C73418), 0x4)
> + Field(PCR1,DWordAcc,Lock,Preserve) {
> + Offset(0x00),
> + DAT1, 32
> + } // End Field PCR1
> + } // End Method PCRW
> +
> + //
> + // PCR Dword Or
> + // arg0: PID
> + // arg1: Offset
> + // arg2: Or data
> + //
> + Method (PCRO, 3, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(Or(Local0,arg2),Local1) // Or data
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + //
> + // PCR Dword And
> + // arg0: PID
> + // arg1: Offset
> + // arg2: And data
> + //
> + Method (PCRA, 3, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(And(Local0,arg2),Local1) // And data
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + //
> + // PCR Dword AndThenOr
> + // arg0: PID
> + // arg1: Offset
> + // arg2: And data
> + // arg3: Or data
> + //
> + Method (PCAO, 4, Serialized) {
> + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0
> + Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr
> + PCRW(arg0,arg1,Local1) // Write data back
> + }
> +
> + Name (PMBV, 0) // ACPI I/O base address value
> + Method (PMB1, 0) {
> + If (LEqual(PMBV, 0)) {
> + Store (ShiftLeft (\_SB.PC00.PMC1.ACBA, 8), PMBV)
> + }
> + Return (PMBV)
> + }
> +
> + Name (PWRV, 0) // PWRM base address value
> + Method (PWRM, 0) {
> + If (LEqual(PWRV, 0)) {
> + Store (ShiftLeft (\_SB.PC00.PMC1.PWBA, 12), PWRV)
> + }
> + Return (PWRV)
> + }
> +
> +
> + //
> + // Define PCH ACPIBASE I/O as an ACPI operating region. The base address
> + // can be found in Device 31, Function 2, Offset 40h.
> + //
> + OperationRegion(PMIO, SystemIo, PMB1, 0x80)
> + Field(PMIO, ByteAcc, NoLock, Preserve) {
> + , 8,
> + PBSS, 1, // Power Button Status
> + Offset(0x40), // General Purpose Event Control
> + , 17,
> + GPEC, 1 // Software GPE Control
> + }
> + OperationRegion(PMLP, SystemIo, Add(\PMB1,0x80), 0x20)
> + Field(PMLP, ByteAcc, NoLock, Preserve) {
> + Offset(0x10), // GPE0 Enable
> + , 8,
> + GE08, 1,
> + , 8,
> + GE17, 1,
> + , 17,
> + GE35, 1,
> + , 9,
> + GE45, 1,
> + , 2,
> + GE48, 1,
> + , 2,
> + GE51, 1,
> + , 76,
> + }
> + Field(PMLP, ByteAcc, NoLock, WriteAsZeros) {
> + Offset(0x00), // GPE0 Status
> + , 8,
> + GS08, 1,
> + , 8,
> + GS17, 1,
> + , 17,
> + GS35, 1,
> + , 9,
> + GS45, 1,
> + , 2,
> + GS48, 1,
> + , 2,
> + GS51, 1,
> + , 2,
> + GS54, 1,
> + GS55, 1,
> + , 42,
> + GS98, 1,
> + , 29,
> + }
> +
> +
> +
> + //
> + // PWRM register definitions
> + //
> + OperationRegion(PWMR, SystemMemory, \PWRM, 0x800)
> + Field(PWMR, AnyAcc, NoLock, Preserve) {
> + Offset(0x0E0),
> + , 16,
> + DWLE, 1, // Deep-Sx WLAN Phy Power Enable
> + HWLE, 1, // Host Wireless LAN Phy Power Enable
> + }
> +
> + //
> + //
> + OperationRegion(PMST, SystemMemory, PWRV, 0x80)
> + Field(PMST, DWordAcc, NoLock, Preserve) {
> + Offset(0x18), // Power Management Configuration Reg 1 (PM_CFG)
> + , 25, //
> + USBP, 1, // Allow USB2 PHY Core Power Gating
> (ALLOW_USB2_CORE_PG)
> + Offset(0x1C), // PCH Power Management Status (PCH_PM_STS)
> + , 24, //
> + PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS)
> + Offset(0x20), // Message to PMC (MTPMC)
> + MPMC, 32, // Message to PMC (MTPMC)
> + Offset(0x24), // PCH Power Management Status (PCH_PM_STS2)
> + , 20, //
> + UWAB, 1, // USB2 Workaround Available Bit
> + }
> +
> +} //end Scope(\)
> +
> +Scope (\_SB.PC00) {
> + Name(LTRN, 0)
> + Name(OBFN, 0)
> +
> + Name(LMSL, 0)
> + Name(LNSL, 0)
> +
> + //
> + // LAN Controller - Device 31, Function 6
> + //
> + Scope(\_SB.PC00.GBE1) {
> + Method(_DSM,4,serialized){if(PCIC(Arg0)) {
> return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0x00})}
> + OperationRegion(GLBA, PCI_Config, 0,0x100)
> + Field(GLBA,AnyAcc,NoLock,Preserve)
> + {
> + DVID, 16,
> + Offset(0xCC),
> + , 8,
> + PMEE, 1, // PME Enable
> + , 6,
> + PMES, 1, // PME Status
> + }
> +
> + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4
> state
> +
> + Method(_DSW, 3)
> + {
> + Store(Arg0, PMEE)
> + }
> +
> + //
> + // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME
> + //
> + Method(GPEH)
> + {
> + If(LEqual(DVID, 0xFFFF)) {
> + Return()
> + }
> + If(LAnd(PMEE, PMES)) {
> + Store(1, PMES) // clear PME Status
> + Notify(GBE1, 0x02)
> + }
> + }
> + } // end "GbE Controller"
> +
> +} //scope
> +
> +//
> +// xHCI Controller - Device 20, Function 0
> +//
> +Include("PchXhci.asl")
> +
> +// xDCI (OTG) Controller is not used in Server
> +// Comment out as ifdefs don't work at Trim stage of ASL preparation
> +
> +Scope(\_SB_.PC00) {
> + //
> + // High Definition Audio Controller - Device 31, Function 3
> + //
> + include("PchHda.asl")
> +
> + //
> + // PCIE Root Port #01
> + //
> + Scope(\_SB.PC00.RP01) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR1, LTRN)
> + Store (PML1, LMSL)
> + Store (PNL1, LNSL)
> + Store (OBF1, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #01"
> +
> + //
> + // PCIE Root Port #02
> + //
> + Scope(\_SB.PC00.RP02) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR2, LTRN)
> + Store (PML2, LMSL)
> + Store (PNL2, LNSL)
> + Store (OBF2, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #02"
> +
> + //
> + // PCIE Root Port #03
> + //
> + Scope(\_SB.PC00.RP03) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR3, LTRN)
> + Store (PML3, LMSL)
> + Store (PNL3, LNSL)
> + Store (OBF3, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #03"
> +
> + //
> + // PCIE Root Port #04
> + //
> + Scope(\_SB.PC00.RP04) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR4, LTRN)
> + Store (PML4, LMSL)
> + Store (PNL4, LNSL)
> + Store (OBF4, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #04"
> +
> + //
> + // PCIE Root Port #05
> + //
> + Scope(\_SB.PC00.RP05) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR5, LTRN)
> + Store (PML5, LMSL)
> + Store (PNL5, LNSL)
> + Store (OBF5, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #05"
> +
> + //
> + // PCIE Root Port #06
> + //
> + Scope(\_SB.PC00.RP06) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR6, LTRN)
> + Store (PML6, LMSL)
> + Store (PNL6, LNSL)
> + Store (OBF6, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #06"
> +
> + //
> + // PCIE Root Port #07
> + //
> + Scope(\_SB.PC00.RP07) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR7, LTRN)
> + Store (PML7, LMSL)
> + Store (PNL7, LNSL)
> + Store (OBF7, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #07"
> +
> + //
> + // PCIE Root Port #08
> + //
> + Scope(\_SB.PC00.RP08) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR8, LTRN)
> + Store (PML8, LMSL)
> + Store (PNL8, LNSL)
> + Store (OBF8, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #08"
> +
> + //
> + // PCIE Root Port #09
> + //
> + Scope(\_SB.PC00.RP09) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTR9, LTRN)
> + Store (PML9, LMSL)
> + Store (PNL9, LNSL)
> + Store (OBF9, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #09"
> +
> + //
> + // PCIE Root Port #10
> + //
> + Scope(\_SB.PC00.RP10) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRA, LTRN)
> + Store (PMLA, LMSL)
> + Store (PNLA, LNSL)
> + Store (OBFA, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #10"
> +
> + //
> + // PCIE Root Port #11
> + //
> + Scope(\_SB.PC00.RP11) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRB, LTRN)
> + Store (PMLB, LMSL)
> + Store (PNLB, LNSL)
> + Store (OBFB, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #11"
> +
> + //
> + // PCIE Root Port #12
> + //
> + Scope(\_SB.PC00.RP12) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRC, LTRN)
> + Store (PMLC, LMSL)
> + Store (PNLC, LNSL)
> + Store (OBFC, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #12"
> +
> + //
> + // PCIE Root Port #13
> + //
> + Scope(\_SB.PC00.RP13) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRD, LTRN)
> + Store (PMLD, LMSL)
> + Store (PNLD, LNSL)
> + Store (OBFD, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #13"
> +
> + //
> + // PCIE Root Port #14
> + //
> + Scope(\_SB.PC00.RP14) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRE, LTRN)
> + Store (PMLE, LMSL)
> + Store (PNLE, LNSL)
> + Store (OBFE, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #14"
> +
> + //
> + // PCIE Root Port #15
> + //
> + Scope(\_SB.PC00.RP15) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRF, LTRN)
> + Store (PMLF, LMSL)
> + Store (PNLF, LNSL)
> + Store (OBFF, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #15"
> +
> + //
> + // PCIE Root Port #16
> + //
> + Scope(\_SB.PC00.RP16) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRG, LTRN)
> + Store (PMLG, LMSL)
> + Store (PNLG, LNSL)
> + Store (OBFG, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #16"
> +
> + //
> + // PCIE Root Port #17
> + //
> + Scope(\_SB.PC00.RP17) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRH, LTRN)
> + Store (PMLH, LMSL)
> + Store (PNLH, LNSL)
> + Store (OBFH, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #17"
> +
> + //
> + // PCIE Root Port #18
> + //
> + Scope(\_SB.PC00.RP18) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRI, LTRN)
> + Store (PMLI, LMSL)
> + Store (PNLI, LNSL)
> + Store (OBFI, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #18"
> +
> + //
> + // PCIE Root Port #19
> + //
> + Scope(\_SB.PC00.RP19) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRJ, LTRN)
> + Store (PMLJ, LMSL)
> + Store (PNLJ, LNSL)
> + Store (OBFJ, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #19"
> +
> + //
> + // PCIE Root Port #20
> + //
> + Scope(\_SB.PC00.RP20) {
> + //
> + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes.
> + //
> + Method(_INI)
> + {
> + Store (LTRK, LTRN)
> + Store (PMLK, LMSL)
> + Store (PNLK, LNSL)
> + Store (OBFK, OBFN)
> + }
> + Include("PchPcie.asl")
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + } // end "PCIE Root Port #20"
> +
> + //
> + // Serial ATA Host Controller - Device 31, Function 2
> + //
> +External(\_SB.PC00.SAT0.SDSM, MethodObj)
> +
> +Scope (\_SB.PC00.SAT1) {
> + Include ("PchSata.asl")
> + Device(PRT6)
> + {
> + Name(_ADR,0x0006FFFF) // Port 6
> + }
> + Device(PRT7)
> + {
> + Name(_ADR,0x0007FFFF) // Port 7
> + }
> +}
> +Scope (\_SB.PC00.SAT2) {
> + Include ("PchSata.asl")
> +}
> + //Server does not support CIO Camera I/O
> +
> + //
> + // Thermal Device
> + //
> + Scope(\_SB.PC00.TERM) {
> + Name (_HID, "INT3536")
> + Name (_UID, 1)
> + Name (RBUF, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFE03C000, 0x00001000, BAR0)
> + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { 18 }
> + })
> +
> + CreateDWordField(RBUF,IRQ._INT,IRQN)
> + Method (_CRS, 0x0, NotSerialized) {
> + Store(TIRQ, IRQN)
> +
> + Return (RBUF)
> + }
> +
> + Method (_STA, 0x0, NotSerialized)
> + {
> + If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI mode
> + If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated
> + Return(0xF)
> + }
> + }
> +}
> +
> +// Comment out as ifdefs don't work at Trim stage of ASL preparation
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> new file mode 100644
> index 0000000000..ab5b5c42dd
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Hda.asl
> @@ -0,0 +1,307 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Bit Difinitions
> +//
> +#ifndef BIT0
> +#define BIT0 0x0001
> +#define BIT1 0x0002
> +#define BIT2 0x0004
> +#define BIT3 0x0008
> +#define BIT4 0x0010
> +#define BIT5 0x0020
> +#define BIT6 0x0040
> +#define BIT7 0x0080
> +#define BIT8 0x0100
> +#define BIT9 0x0200
> +#endif //BIT0
> +
> +//
> +// High Definition Audio Controller - Device 31, Function 3
> +//
> +Scope(\_SB.PC00.CAVS) {
> +
> +#ifndef BIT0
> +#define BIT0 0x00000001
> +#endif
> +#ifndef BIT1
> +#define BIT1 0x00000002
> +#endif
> +#ifndef BIT2
> +#define BIT2 0x00000004
> +#endif
> +#ifndef BIT3
> +#define BIT3 0x00000008
> +#endif
> +#ifndef BIT4
> +#define BIT4 0x00000010
> +#endif
> +#ifndef BIT5
> +#define BIT5 0x00000020
> +#endif
> +#ifndef BIT6
> +#define BIT6 0x00000040
> +#endif
> +#ifndef BIT7
> +#define BIT7 0x00000080
> +#endif
> +#ifndef BIT8
> +#define BIT8 0x00000100
> +#endif
> +#ifndef BIT9
> +#define BIT9 0x00000200
> +#endif
> +#ifndef BIT10
> +#define BIT10 0x00000400
> +#endif
> +#ifndef BIT11
> +#define BIT11 0x00000800
> +#endif
> +#ifndef BIT12
> +#define BIT12 0x00001000
> +#endif
> +#ifndef BIT13
> +#define BIT13 0x00002000
> +#endif
> +#ifndef BIT14
> +#define BIT14 0x00004000
> +#endif
> +#ifndef BIT15
> +#define BIT15 0x00008000
> +#endif
> +#ifndef BIT16
> +#define BIT16 0x00010000
> +#endif
> +#ifndef BIT17
> +#define BIT17 0x00020000
> +#endif
> +#ifndef BIT18
> +#define BIT18 0x00040000
> +#endif
> +#ifndef BIT19
> +#define BIT19 0x00080000
> +#endif
> +#ifndef BIT20
> +#define BIT20 0x00100000
> +#endif
> +#ifndef BIT21
> +#define BIT21 0x00200000
> +#endif
> +#ifndef BIT22
> +#define BIT22 0x00400000
> +#endif
> +#ifndef BIT23
> +#define BIT23 0x00800000
> +#endif
> +#ifndef BIT24
> +#define BIT24 0x01000000
> +#endif
> +#ifndef BIT25
> +#define BIT25 0x02000000
> +#endif
> +#ifndef BIT26
> +#define BIT26 0x04000000
> +#endif
> +#ifndef BIT27
> +#define BIT27 0x08000000
> +#endif
> +#ifndef BIT28
> +#define BIT28 0x10000000
> +#endif
> +#ifndef BIT29
> +#define BIT29 0x20000000
> +#endif
> +#ifndef BIT30
> +#define BIT30 0x40000000
> +#endif
> +#ifndef BIT31
> +#define BIT31 0x80000000
> +#endif
> +
> + //
> + // Define a Memory Region that will allow access to the HDA PCI
> Configuration Space
> + //
> + OperationRegion(HDAR, PCI_Config, 0x00, 0x100)
> + Field(HDAR,WordAcc,NoLock,Preserve) {
> + VDID,32, // 0x00, VID DID
> + Offset(0x48), // 0x48, CGCTL - Clock Gating Control
> + ,6,
> + MBCG,1, // MISCBDCGE [BIT6]
> + Offset(0x54), // 0x54, Power Management Control and Status Register
> + ,8,
> + PMEE,1,
> + ,6,
> + PMES,1 // PME Status
> + }
> +
> + Name(_S0W, 3) // Device can wake itself from D3 in S0
> +
> + Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable
> +
> +
> + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state
> +
> + // GPE handler for HDA, this is part of _Lxx handler for bus 0 PME
> + Method(GPEH) {
> + If(LEqual(VDID, 0xFFFFFFFF)) {
> + Return()
> + }
> +
> + If(LAnd(PMEE, PMES)) {
> + ADBG("HDAS GPEH")
> + Store(1, PMES) // clear PME Status
> + Notify(CAVS, 0x02)
> + }
> + }
> +
> + // NHLT Table memory descriptor, returned from _DSM
> + Name(NBUF, ResourceTemplate () {
> + // NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN -
> 1) and length (_LEN)
> + QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed,
> NonCacheable, ReadOnly,
> + 0x1, // AddressGranularity
> + 0x0000000000000000, // AddressMinimum _MIN
> + 0x0000000000000000, // AddressMaximum _MAX
> + 0x0,
> + 0x0, // RangeLength _LEN
> + , , NHLT, AddressRangeACPI,)
> + })
> +
> + Method(AUWA,0,Serialized)
> + {
> + If(LEqual(PCHS, 1)) {
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-H A0
> stepping (RevID = 0x0)
> + } else {
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP A0
> stepping (RevID = 0x0)
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP A1
> stepping (RevID = 0x1)
> + If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP A2
> stepping (RevID = 0x9)
> + }
> + Return (0)
> + }
> +
> + Method(_INI) {
> + // Update resource according to NVS
> + ADBG("HDAS _INI")
> +
> + // Set NHLT base address and length
> + CreateQWordField(NBUF, ^NHLT._MIN, NBAS)
> + CreateQWordField(NBUF, ^NHLT._MAX, NMAS)
> + CreateQWordField(NBUF, ^NHLT._LEN, NLEN)
> + Store(NHLA, NBAS)
> + Add(NHLA, Subtract(NHLL, 1), NMAS)
> + Store(NHLL, NLEN)
> +
> + If(LEqual(AUWA(), 1)) {
> + Store(0, \_SB.PC00.CAVS.MBCG)
> + }
> + }
> +
> + Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj,
> PkgObj}) {
> + // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer)
> + // Arg1 - Revision ID: 0x01 (Integer)
> + // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details.
> + // Arg3 - Depends on Function Index - See below for details.
> + // Return - Depends on Function Index - See below for details.
> +
> + ADBG("HDAS _DSM")
> +
> + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> +
> + // Verify UUID
> + If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) {
> +
> + Switch(ToInteger(Arg2)) {
> +
> + // Function 0: Function Support Query
> + // Arg2 - Function Index: 0x00 (Integer)
> + // Arg3: Unused
> + // Return: Bitmask of functions supported. (Buffer)
> + Case(0) {
> + // Supports function 0 - 3
> + Return(Buffer(One) { 0x0F })
> + }
> +
> + // Function 1: Query Non HD Audio Descriptor Table
> + // Used by the Intel Offload Engine Driver to discover the
> + // non HD Audio devices supported by the Audio DSP.
> + // Arg2 - Function Index: 0x01 (Integer)
> + // Arg3 - Unused
> + // Return - ACPI Table describing the non HD Audio links and devices
> supported by the ADSP (ResourceBuffer)
> + Case(1) {
> + ADBG("_DSM Fun 1 NHLT")
> + // NBUF - Memory Resource Descriptor buffer with address and
> length of NHLT
> + Return(NBUF)
> + }
> +
> + // Function 2: Query Feature Mask
> + // Used by the Intel Offload Engine Driver to retrieve a
> bitmask
> + // of features allowable on this platform.
> + // Arg2 - Function Index: 0x02 (Integer)
> + // Arg3: Unused
> + // Return: Bitmask of supported features.
> + Case (2) {
> + ADBG("_DSM Fun 2 FMSK")
> + // Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported
> + // Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported
> + // Bit 2 == '1', codec based VAD support allowable
> + // Bit 3 - 4 Reserved
> + // Bit 5 == '1', BT Intel HFP SCO is supported
> + // Bit 6 == '1', BT Intel A2DP is supported
> + // Bit 7 == '1', DSP based speech pre-processing disabled
> + // Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on
> Voice
> + // Bit 9 - 31 Reserved, shall be set to '0'
> + // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy
> + Return(ADFM)
> + }
> +
> + // Function 3: Query Pre/Post Processing Module Support
> + // Used by the Intel Offload Engine Driver to determine if a
> + // specified PP Module is allowed to be supported on this
> platform
> + // Arg2 - Function Index: 0x03 (Integer)
> + // Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer)
> + // Return - TRUE if PP Module supported, else FALSE.
> + Case (3) {
> + ADBG("_DSM Fun 3 PPMS")
> + // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated
> from PchPolicy: HdaConfig->DspPpModuleMask
> +
> + //
> + // Example (to be updated with real GUIDs of supported 3rd party
> IP):
> + //
> + // 3rd Party DSP Processing Module 1 placeholder (enabled by policy
> HdaConfig->DspPpModuleMask |= BIT0)
> + // Check PP module with GUID AABBCCDD-EEFF-1122-3344-
> 556677889900
> + // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-
> 556677889900"))){
> + // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] /
> ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true)
> + // }
> + //
> + // 3rd Party DSP Processing Module 5 placeholder (enabled by policy
> HdaConfig->DspPpModuleMask |= BIT5)
> + // Check PP module with GUID 11111111-2222-3333-4444-
> AABBCCDDEEFF
> + // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-
> AABBCCDDEEFF"))){
> + // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] /
> ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true)
> + // }
> + //
> + // Implement for all supported PP modules
> + //
> + Return(Buffer() {0x00}) // Is not supported
> + }
> +
> + Default {
> + // Function not supported (Arg2)
> + ADBG("_DSM Fun NOK")
> + Return(Buffer(One) { 0x00 })
> + }
> + } // Switch(Arg2) End
> + } // If(Arg0, UUID) End
> +
> +
> + // UUID not supported (Arg0)
> + ADBG("_DSM UUID NOK")
> + //Fix warning: not all control paths return a value
> + Return(Buffer() {0x00})
> + } // _DSM End
> +
> +} // end "High Definition Audio Controller"
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> new file mode 100644
> index 0000000000..bd27ca7342
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Nvs.asl
> @@ -0,0 +1,271 @@
> +/** @file
> +
> + @copyright
> + Copyright 2013 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // Define PCH NVS Area operatino region.
> + //
> +
> +
> +
> + OperationRegion(PNVA,SystemMemory,PNVB,PNVL)
> + Field(PNVA,AnyAcc,Lock,Preserve)
> + {
> + Offset(0), RCRV, 32, // Offset(0), RC Revision
> + Offset(4), PCHS, 16, // Offset(4), PCH Series
> + Offset(6), PCHG, 16, // Offset(6), PCH Generation
> + Offset(8), RPA1, 32, // Offset(8), Root Port address 1
> + Offset(12), RPA2, 32, // Offset(12), Root Port address 2
> + Offset(16), RPA3, 32, // Offset(16), Root Port address 3
> + Offset(20), RPA4, 32, // Offset(20), Root Port address 4
> + Offset(24), RPA5, 32, // Offset(24), Root Port address 5
> + Offset(28), RPA6, 32, // Offset(28), Root Port address 6
> + Offset(32), RPA7, 32, // Offset(32), Root Port address 7
> + Offset(36), RPA8, 32, // Offset(36), Root Port address 8
> + Offset(40), RPA9, 32, // Offset(40), Root Port address 9
> + Offset(44), RPAA, 32, // Offset(44), Root Port address 10
> + Offset(48), RPAB, 32, // Offset(48), Root Port address 11
> + Offset(52), RPAC, 32, // Offset(52), Root Port address 12
> + Offset(56), RPAD, 32, // Offset(56), Root Port address 13
> + Offset(60), RPAE, 32, // Offset(60), Root Port address 14
> + Offset(64), RPAF, 32, // Offset(64), Root Port address 15
> + Offset(68), RPAG, 32, // Offset(68), Root Port address 16
> + Offset(72), RPAH, 32, // Offset(72), Root Port address 17
> + Offset(76), RPAI, 32, // Offset(76), Root Port address 18
> + Offset(80), RPAJ, 32, // Offset(80), Root Port address 19
> + Offset(84), RPAK, 32, // Offset(84), Root Port address 20
> + Offset(88), NHLA, 64, // Offset(88), HD-Audio NHLT ACPI address
> + Offset(96), NHLL, 32, // Offset(96), HD-Audio NHLT ACPI length
> + Offset(100), ADFM, 32, // Offset(100), HD-Audio DSP Feature Mask
> + Offset(104), SBRG, 32, // Offset(104), SBREG_BAR
> + Offset(108), GPEM, 32, // Offset(108), GPP_X to GPE_DWX mapping
> + Offset(112), G2L0, 32, // Offset(112), GPE 2-tier level edged enabled
> Gpio pads (Group Index 0)
> + Offset(116), G2L1, 32, // Offset(116), GPE 2-tier level edged enabled
> Gpio pads (Group Index 1)
> + Offset(120), G2L2, 32, // Offset(120), GPE 2-tier level edged enabled
> Gpio pads (Group Index 2)
> + Offset(124), G2L3, 32, // Offset(124), GPE 2-tier level edged enabled
> Gpio pads (Group Index 3)
> + Offset(128), G2L4, 32, // Offset(128), GPE 2-tier level edged enabled
> Gpio pads (Group Index 4)
> + Offset(132), G2L5, 32, // Offset(132), GPE 2-tier level edged enabled
> Gpio pads (Group Index 5)
> + Offset(136), G2L6, 32, // Offset(136), GPE 2-tier level edged enabled
> Gpio pads (Group Index 6)
> + Offset(140), G2L7, 32, // Offset(140), GPE 2-tier level edged enabled
> Gpio pads (Group Index 7)
> + Offset(144), G2L8, 32, // Offset(144), GPE 2-tier level edged enabled
> Gpio pads (Group Index 8)
> + Offset(148), G2L9, 32, // Offset(148), GPE 2-tier level edged enabled
> Gpio pads (Group Index 9)
> + Offset(152), G2LA, 32, // Offset(152), GPE 2-tier level edged enabled
> Gpio pads (Group Index 10)
> + Offset(156), G2LB, 32, // Offset(156), GPE 2-tier level edged enabled
> Gpio pads (Group Index 11)
> + Offset(160), G2LC, 32, // Offset(160), GPE 2-tier level edged enabled
> Gpio pads (Groip Index 12)
> +
> + Offset(164), PML1, 16, // Offset(164), PCIE LTR max snoop Latency 1
> + Offset(166), PML2, 16, // Offset(166), PCIE LTR max snoop Latency 2
> + Offset(168), PML3, 16, // Offset(168), PCIE LTR max snoop Latency 3
> + Offset(170), PML4, 16, // Offset(170), PCIE LTR max snoop Latency 4
> + Offset(172), PML5, 16, // Offset(172), PCIE LTR max snoop Latency 5
> + Offset(174), PML6, 16, // Offset(174), PCIE LTR max snoop Latency 6
> + Offset(176), PML7, 16, // Offset(176), PCIE LTR max snoop Latency 7
> + Offset(178), PML8, 16, // Offset(178), PCIE LTR max snoop Latency 8
> + Offset(180), PML9, 16, // Offset(180), PCIE LTR max snoop Latency 9
> + Offset(182), PMLA, 16, // Offset(182), PCIE LTR max snoop Latency 10
> + Offset(184), PMLB, 16, // Offset(184), PCIE LTR max snoop Latency 11
> + Offset(186), PMLC, 16, // Offset(186), PCIE LTR max snoop Latency 12
> + Offset(188), PMLD, 16, // Offset(188), PCIE LTR max snoop Latency 13
> + Offset(190), PMLE, 16, // Offset(190), PCIE LTR max snoop Latency 14
> + Offset(192), PMLF, 16, // Offset(192), PCIE LTR max snoop Latency 15
> + Offset(194), PMLG, 16, // Offset(194), PCIE LTR max snoop Latency 16
> + Offset(196), PMLH, 16, // Offset(196), PCIE LTR max snoop Latency 17
> + Offset(198), PMLI, 16, // Offset(198), PCIE LTR max snoop Latency 18
> + Offset(200), PMLJ, 16, // Offset(200), PCIE LTR max snoop Latency 19
> + Offset(202), PMLK, 16, // Offset(202), PCIE LTR max snoop Latency 20
> + Offset(204), PNL1, 16, // Offset(204), PCIE LTR max no snoop Latency 1
> + Offset(206), PNL2, 16, // Offset(206), PCIE LTR max no snoop Latency 2
> + Offset(208), PNL3, 16, // Offset(208), PCIE LTR max no snoop Latency 3
> + Offset(210), PNL4, 16, // Offset(210), PCIE LTR max no snoop Latency 4
> + Offset(212), PNL5, 16, // Offset(212), PCIE LTR max no snoop Latency 5
> + Offset(214), PNL6, 16, // Offset(214), PCIE LTR max no snoop Latency 6
> + Offset(216), PNL7, 16, // Offset(216), PCIE LTR max no snoop Latency 7
> + Offset(218), PNL8, 16, // Offset(218), PCIE LTR max no snoop Latency 8
> + Offset(220), PNL9, 16, // Offset(220), PCIE LTR max no snoop Latency 9
> + Offset(222), PNLA, 16, // Offset(222), PCIE LTR max no snoop Latency 10
> + Offset(224), PNLB, 16, // Offset(224), PCIE LTR max no snoop Latency 11
> + Offset(226), PNLC, 16, // Offset(226), PCIE LTR max no snoop Latency 12
> + Offset(228), PNLD, 16, // Offset(228), PCIE LTR max no snoop Latency 13
> + Offset(230), PNLE, 16, // Offset(230), PCIE LTR max no snoop Latency 14
> + Offset(232), PNLF, 16, // Offset(232), PCIE LTR max no snoop Latency 15
> + Offset(234), PNLG, 16, // Offset(234), PCIE LTR max no snoop Latency 16
> + Offset(236), PNLH, 16, // Offset(236), PCIE LTR max no snoop Latency 17
> + Offset(238), PNLI, 16, // Offset(238), PCIE LTR max no snoop Latency 18
> + Offset(240), PNLJ, 16, // Offset(240), PCIE LTR max no snoop Latency 19
> + Offset(242), PNLK, 16, // Offset(242), PCIE LTR max no snoop Latency 20
> + Offset(244), U0C0, 32, // Offset(244), SerialIo Hidden UART0 BAR 0
> + Offset(248), U1C0, 32, // Offset(248), SerialIo Hidden UART1 BAR 0
> + Offset(252), ADPM, 32, // Offset(252), HD-Audio DSP Post-Processing
> Module Mask
> + Offset(256), XHPC, 8, // Offset(256), Number of HighSpeed ports
> implemented in XHCI controller
> + Offset(257), XRPC, 8, // Offset(257), Number of USBR ports
> implemented in XHCI controller
> + Offset(258), XSPC, 8, // Offset(258), Number of SuperSpeed ports
> implemented in XHCI controller
> + Offset(259), XSPA, 8, // Offset(259), Address of 1st SuperSpeed port
> + Offset(260), HPTB, 32, // Offset(260), HPET base address
> + Offset(264), HPTE, 8, // Offset(264), HPET enable
> + //110-bytes large SerialIo block
> + Offset(265), SMD0, 8, // Offset(265), SerialIo controller 0 (sdma) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(266), SMD1, 8, // Offset(266), SerialIo controller 1 (i2c0) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(267), SMD2, 8, // Offset(267), SerialIo controller 2 (i2c1) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(268), SMD3, 8, // Offset(268), SerialIo controller 3 (spi0) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(269), SMD4, 8, // Offset(269), SerialIo controller 4 (spi1) mode (0:
> disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(270), SMD5, 8, // Offset(270), SerialIo controller 5 (ua00) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(271), SMD6, 8, // Offset(271), SerialIo controller 6 (ua01) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(272), SMD7, 8, // Offset(272), SerialIo controller 7 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(273), SMD8, 8, // Offset(273), SerialIo controller 8 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(274), SMD9, 8, // Offset(274), SerialIo controller 9 (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(275), SMDA, 8, // Offset(275), SerialIo controller A (shdc) mode
> (0: disabled, 1: pci, 2: acpi, 3: debug port)
> + Offset(276), SIR0, 8, // Offset(276), SerialIo controller 0 (sdma) irq
> number
> + Offset(277), SIR1, 8, // Offset(277), SerialIo controller 1 (i2c0) irq
> number
> + Offset(278), SIR2, 8, // Offset(278), SerialIo controller 2 (i2c1) irq
> number
> + Offset(279), SIR3, 8, // Offset(279), SerialIo controller 3 (spi0) irq
> number
> + Offset(280), SIR4, 8, // Offset(280), SerialIo controller 4 (spi1) irq
> number
> + Offset(281), SIR5, 8, // Offset(281), SerialIo controller 5 (ua00) irq
> number
> + Offset(282), SIR6, 8, // Offset(282), SerialIo controller 6 (ua01) irq
> number
> + Offset(283), SIR7, 8, // Offset(283), SerialIo controller 7 (shdc) irq
> number
> + Offset(284), SIR8, 8, // Offset(284), SerialIo controller 8 (shdc) irq
> number
> + Offset(285), SIR9, 8, // Offset(285), SerialIo controller 9 (shdc) irq
> number
> + Offset(286), SIRA, 8, // Offset(286), SerialIo controller A (shdc) irq
> number
> + Offset(287), SB00, 32, // Offset(287), SerialIo controller 0 (sdma) BAR0
> + Offset(291), SB01, 32, // Offset(291), SerialIo controller 1 (i2c0) BAR0
> + Offset(295), SB02, 32, // Offset(295), SerialIo controller 2 (i2c1) BAR0
> + Offset(299), SB03, 32, // Offset(299), SerialIo controller 3 (spi0) BAR0
> + Offset(303), SB04, 32, // Offset(303), SerialIo controller 4 (spi1) BAR0
> + Offset(307), SB05, 32, // Offset(307), SerialIo controller 5 (ua00) BAR0
> + Offset(311), SB06, 32, // Offset(311), SerialIo controller 6 (ua01) BAR0
> + Offset(315), SB07, 32, // Offset(315), SerialIo controller 7 (shdc) BAR0
> + Offset(319), SB08, 32, // Offset(319), SerialIo controller 8 (shdc) BAR0
> + Offset(323), SB09, 32, // Offset(323), SerialIo controller 9 (shdc) BAR0
> + Offset(327), SB0A, 32, // Offset(327), SerialIo controller A (shdc) BAR0
> + Offset(331), SB10, 32, // Offset(331), SerialIo controller 0 (sdma) BAR1
> + Offset(335), SB11, 32, // Offset(335), SerialIo controller 1 (i2c0) BAR1
> + Offset(339), SB12, 32, // Offset(339), SerialIo controller 2 (i2c1) BAR1
> + Offset(343), SB13, 32, // Offset(343), SerialIo controller 3 (spi0) BAR1
> + Offset(347), SB14, 32, // Offset(347), SerialIo controller 4 (spi1) BAR1
> + Offset(351), SB15, 32, // Offset(351), SerialIo controller 5 (ua00) BAR1
> + Offset(355), SB16, 32, // Offset(355), SerialIo controller 6 (ua01) BAR1
> + Offset(359), SB17, 32, // Offset(359), SerialIo controller 7 (shdc) BAR1
> + Offset(363), SB18, 32, // Offset(363), SerialIo controller 8 (shdc) BAR1
> + Offset(367), SB19, 32, // Offset(367), SerialIo controller 9 (shdc) BAR1
> + Offset(371), SB1A, 32, // Offset(371), SerialIo controller A (shdc) BAR1
> + //end of SerialIo block
> + Offset(375), GPEN, 8, // Offset(375), GPIO enabled
> + Offset(376), SGIR, 8, // Offset(376), GPIO IRQ
> + Offset(377), NIT1, 8, // Offset(377), RST PCIe Storage Cycle Router#1
> Interface Type
> + Offset(378), NIT2, 8, // Offset(378), RST PCIe Storage Cycle Router#2
> Interface Type
> + Offset(379), NIT3, 8, // Offset(379), RST PCIe Storage Cycle Router#3
> Interface Type
> + Offset(380), NPM1, 8, // Offset(380), RST PCIe Storage Cycle Router#1
> Power Management Capability Pointer
> + Offset(381), NPM2, 8, // Offset(381), RST PCIe Storage Cycle Router#2
> Power Management Capability Pointer
> + Offset(382), NPM3, 8, // Offset(382), RST PCIe Storage Cycle Router#3
> Power Management Capability Pointer
> + Offset(383), NPC1, 8, // Offset(383), RST PCIe Storage Cycle Router#1
> PCIe Capabilities Pointer
> + Offset(384), NPC2, 8, // Offset(384), RST PCIe Storage Cycle Router#2
> PCIe Capabilities Pointer
> + Offset(385), NPC3, 8, // Offset(385), RST PCIe Storage Cycle Router#3
> PCIe Capabilities Pointer
> + Offset(386), NL11, 16, // Offset(386), RST PCIe Storage Cycle Router#1
> L1SS Capability Pointer
> + Offset(388), NL12, 16, // Offset(388), RST PCIe Storage Cycle Router#2
> L1SS Capability Pointer
> + Offset(390), NL13, 16, // Offset(390), RST PCIe Storage Cycle Router#3
> L1SS Capability Pointer
> + Offset(392), ND21, 8, // Offset(392), RST PCIe Storage Cycle Router#1
> Endpoint L1SS Control Data2
> + Offset(393), ND22, 8, // Offset(393), RST PCIe Storage Cycle Router#2
> Endpoint L1SS Control Data2
> + Offset(394), ND23, 8, // Offset(394), RST PCIe Storage Cycle Router#3
> Endpoint L1SS Control Data2
> + Offset(395), ND11, 32, // Offset(395), RST PCIe Storage Cycle Router#1
> Endpoint L1SS Control Data1
> + Offset(399), ND12, 32, // Offset(399), RST PCIe Storage Cycle Router#2
> Endpoint L1SS Control Data1
> + Offset(403), ND13, 32, // Offset(403), RST PCIe Storage Cycle Router#3
> Endpoint L1SS Control Data1
> + Offset(407), NLR1, 16, // Offset(407), RST PCIe Storage Cycle Router#1
> LTR Capability Pointer
> + Offset(409), NLR2, 16, // Offset(409), RST PCIe Storage Cycle Router#2
> LTR Capability Pointer
> + Offset(411), NLR3, 16, // Offset(411), RST PCIe Storage Cycle Router#3
> LTR Capability Pointer
> + Offset(413), NLD1, 32, // Offset(413), RST PCIe Storage Cycle Router#1
> Endpoint LTR Data
> + Offset(417), NLD2, 32, // Offset(417), RST PCIe Storage Cycle Router#2
> Endpoint LTR Data
> + Offset(421), NLD3, 32, // Offset(421), RST PCIe Storage Cycle Router#3
> Endpoint LTR Data
> + Offset(425), NEA1, 16, // Offset(425), RST PCIe Storage Cycle Router#1
> Endpoint LCTL Data
> + Offset(427), NEA2, 16, // Offset(427), RST PCIe Storage Cycle Router#2
> Endpoint LCTL Data
> + Offset(429), NEA3, 16, // Offset(429), RST PCIe Storage Cycle Router#3
> Endpoint LCTL Data
> + Offset(431), NEB1, 16, // Offset(431), RST PCIe Storage Cycle Router#1
> Endpoint DCTL Data
> + Offset(433), NEB2, 16, // Offset(433), RST PCIe Storage Cycle Router#2
> Endpoint DCTL Data
> + Offset(435), NEB3, 16, // Offset(435), RST PCIe Storage Cycle Router#3
> Endpoint DCTL Data
> + Offset(437), NEC1, 16, // Offset(437), RST PCIe Storage Cycle Router#1
> Endpoint DCTL2 Data
> + Offset(439), NEC2, 16, // Offset(439), RST PCIe Storage Cycle Router#2
> Endpoint DCTL2 Data
> + Offset(441), NEC3, 16, // Offset(441), RST PCIe Storage Cycle Router#3
> Endpoint DCTL2 Data
> + Offset(443), NRA1, 16, // Offset(443), RST PCIe Storage Cycle Router#1
> RootPort DCTL2 Data
> + Offset(445), NRA2, 16, // Offset(445), RST PCIe Storage Cycle Router#2
> RootPort DCTL2 Data
> + Offset(447), NRA3, 16, // Offset(447), RST PCIe Storage Cycle Router#3
> RootPort DCTL2 Data
> + Offset(449), NMB1, 32, // Offset(449), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X Table BAR
> + Offset(453), NMB2, 32, // Offset(453), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X Table BAR
> + Offset(457), NMB3, 32, // Offset(457), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X Table BAR
> + Offset(461), NMV1, 32, // Offset(461), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X Table BAR value
> + Offset(465), NMV2, 32, // Offset(465), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X Table BAR value
> + Offset(469), NMV3, 32, // Offset(469), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X Table BAR value
> + Offset(473), NPB1, 32, // Offset(473), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X PBA BAR
> + Offset(477), NPB2, 32, // Offset(477), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X PBA BAR
> + Offset(481), NPB3, 32, // Offset(481), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X PBA BAR
> + Offset(485), NPV1, 32, // Offset(485), RST PCIe Storage Cycle Router#1
> Endpoint unique MSI-X PBA BAR value
> + Offset(489), NPV2, 32, // Offset(489), RST PCIe Storage Cycle Router#2
> Endpoint unique MSI-X PBA BAR value
> + Offset(493), NPV3, 32, // Offset(493), RST PCIe Storage Cycle Router#3
> Endpoint unique MSI-X PBA BAR value
> + Offset(497), , 8, // Offset(497), Flag indicating Exit Boot Service, to
> inform SMM
> + Offset(498), SXRB, 32, // Offset(498), Sx handler reserved MMIO base
> + Offset(502), SXRS, 32, // Offset(502), Sx handler reserved MMIO size
> + Offset(506), CIOE, 8, // Offset(506), Cio2 Device Enabled as ACPI device
> + Offset(507), CIOI, 8, // Offset(507), Cio2 Interrupt Number
> + Offset(508), TAEN, 8, // Offset(508), Thermal Device Acpi mode enabled
> + Offset(509), TIRQ, 8, // Offset(509), Thermal Device IRQ number
> + Offset(510), XWMB, 32, // Offset(510), XHCI memory base address
> + Offset(514), EMH4, 8, // Offset(514), eMMC HS400 mode enabled
> + Offset(515), CSKU, 8, // Offset(515), CPU SKU
> + Offset(516), ITA0, 16, // Offset(516),
> + Offset(518), ITA1, 16, // Offset(518),
> + Offset(520), ITA2, 16, // Offset(520),
> + Offset(522), ITA3, 16, // Offset(522),
> + Offset(524), ITS0, 8, // Offset(524),
> + Offset(525), ITS1, 8, // Offset(525),
> + Offset(526), ITS2, 8, // Offset(526),
> + Offset(527), ITS3, 8, // Offset(527),
> + Offset(528), LTR1, 8, // Offset(528), Latency Tolerance Reporting Enable
> + Offset(529), LTR2, 8, // Offset(529), Latency Tolerance Reporting Enable
> + Offset(530), LTR3, 8, // Offset(530), Latency Tolerance Reporting Enable
> + Offset(531), LTR4, 8, // Offset(531), Latency Tolerance Reporting Enable
> + Offset(532), LTR5, 8, // Offset(532), Latency Tolerance Reporting Enable
> + Offset(533), LTR6, 8, // Offset(533), Latency Tolerance Reporting Enable
> + Offset(534), LTR7, 8, // Offset(534), Latency Tolerance Reporting Enable
> + Offset(535), LTR8, 8, // Offset(535), Latency Tolerance Reporting Enable
> + Offset(536), LTR9, 8, // Offset(536), Latency Tolerance Reporting Enable
> + Offset(537), LTRA, 8, // Offset(537), Latency Tolerance Reporting Enable
> + Offset(538), LTRB, 8, // Offset(538), Latency Tolerance Reporting Enable
> + Offset(539), LTRC, 8, // Offset(539), Latency Tolerance Reporting Enable
> + Offset(540), LTRD, 8, // Offset(540), Latency Tolerance Reporting Enable
> + Offset(541), LTRE, 8, // Offset(541), Latency Tolerance Reporting Enable
> + Offset(542), LTRF, 8, // Offset(542), Latency Tolerance Reporting Enable
> + Offset(543), LTRG, 8, // Offset(543), Latency Tolerance Reporting Enable
> + Offset(544), LTRH, 8, // Offset(544), Latency Tolerance Reporting Enable
> + Offset(545), LTRI, 8, // Offset(545), Latency Tolerance Reporting Enable
> + Offset(546), LTRJ, 8, // Offset(546), Latency Tolerance Reporting Enable
> + Offset(547), LTRK, 8, // Offset(547), Latency Tolerance Reporting Enable
> + Offset(548), OBF1, 8, // Offset(548), Optimized Buffer Flush and Fill
> + Offset(549), OBF2, 8, // Offset(549), Optimized Buffer Flush and Fill
> + Offset(550), OBF3, 8, // Offset(550), Optimized Buffer Flush and Fill
> + Offset(551), OBF4, 8, // Offset(551), Optimized Buffer Flush and Fill
> + Offset(552), OBF5, 8, // Offset(552), Optimized Buffer Flush and Fill
> + Offset(553), OBF6, 8, // Offset(553), Optimized Buffer Flush and Fill
> + Offset(554), OBF7, 8, // Offset(554), Optimized Buffer Flush and Fill
> + Offset(555), OBF8, 8, // Offset(555), Optimized Buffer Flush and Fill
> + Offset(556), OBF9, 8, // Offset(556), Optimized Buffer Flush and Fill
> + Offset(557), OBFA, 8, // Offset(557), Optimized Buffer Flush and Fill
> + Offset(558), OBFB, 8, // Offset(558), Optimized Buffer Flush and Fill
> + Offset(559), OBFC, 8, // Offset(559), Optimized Buffer Flush and Fill
> + Offset(560), OBFD, 8, // Offset(560), Optimized Buffer Flush and Fill
> + Offset(561), OBFE, 8, // Offset(561), Optimized Buffer Flush and Fill
> + Offset(562), OBFF, 8, // Offset(562), Optimized Buffer Flush and Fill
> + Offset(563), OBFG, 8, // Offset(563), Optimized Buffer Flush and Fill
> + Offset(564), OBFH, 8, // Offset(564), Optimized Buffer Flush and Fill
> + Offset(565), OBFI, 8, // Offset(565), Optimized Buffer Flush and Fill
> + Offset(566), OBFJ, 8, // Offset(566), Optimized Buffer Flush and Fill
> + Offset(567), OBFK, 8, // Offset(567), Optimized Buffer Flush and Fill
> + Offset(568), ECR1, 8, // Offset(568), External Change Request
> + Offset(569), AG1L, 64, // Offset(569), HDA PP module custom GUID 1 -
> first 64bit [0-63]
> + Offset(577), AG1H, 64, // Offset(577), HDA PP module custom GUID 1 -
> second 64bit [64-127]
> + Offset(585), AG2L, 64, // Offset(585), HDA PP module custom GUID 2 -
> first 64bit [0-63]
> + Offset(593), AG2H, 64, // Offset(593), HDA PP module custom GUID 2 -
> second 64bit [64-127]
> + Offset(601), AG3L, 64, // Offset(601), HDA PP module custom GUID 3 -
> first 64bit [0-63]
> + Offset(609), AG3H, 64, // Offset(609), HDA PP module custom GUID 3 -
> second 64bit [64-127]
> + Offset(617), MCFG, 32 // Offset(617), PcieMmCfgBaseAddress
> + }
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> new file mode 100644
> index 0000000000..21d68c55bc
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Pcie.asl
> @@ -0,0 +1,203 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + OperationRegion(PXCS,PCI_Config,0x00,0x480)
> + Field(PXCS,AnyAcc, NoLock, Preserve)
> + {
> + Offset(0),
> + VDID, 32,
> + Offset(0x50), // LCTL - Link Control Register
> + L0SE, 1, // 0, L0s Entry Enabled
> + , 3,
> + LDIS, 1,
> + , 3,
> + Offset(0x52), // LSTS - Link Status Register
> + , 13,
> + LASX, 1, // 0, Link Active Status
> + Offset(0x5A), // SLSTS[7:0] - Slot Status Register
> + ABPX, 1, // 0, Attention Button Pressed
> + , 2,
> + PDCX, 1, // 3, Presence Detect Changed
> + , 2,
> + PDSX, 1, // 6, Presence Detect State
> + , 1,
> + Offset(0x60), // RSTS - Root Status Register
> + , 16,
> + PSPX, 1, // 16, PME Status
> + Offset(0xA4),
> + D3HT, 2, // Power State
> + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register
> + , 30,
> + HPEX, 1, // 30, Hot Plug SCI Enable
> + PMEX, 1, // 31, Power Management SCI Enable
> + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable
> + , 2,
> + L23E, 1, // 2, L23_Rdy Entry Request (L23ER)
> + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
> + Offset(0x324),
> + , 3,
> + LEDM, 1, // PCIEDBG.DMIL1EDM
> + Offset(0x420), // Offset 420h: PCIEPMECTL - PCIe PM Extension Control
> + , 30,
> + DPGE, 1, // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY
> Lane Power Gating Enable (DLSULPPGE):
> + }
> + Field(PXCS,AnyAcc, NoLock, WriteAsZeros)
> + {
> + Offset(0xDC), // SMSCS - SMI/SCI Status Register
> + , 30,
> + HPSX, 1, // 30, Hot Plug SCI Status
> + PMSX, 1 // 31, Power Management SCI Status
> + }
> +
> +
> + Name(LTRV, Package(){0,0,0,0})
> +
> + //
> + // _DSM Device Specific Method
> + //
> + // Arg0: UUID Unique function identifier
> + // Arg1: Integer Revision Level
> + // Arg2: Integer Function Index (0 = Return Supported Functions)
> + // Arg3: Package Parameters
> + Method(_DSM, 4, Serialized) {
> + //
> + // Switch based on which unique function identifier was passed in
> + //
> + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
> + //
> + // _DSM Definitions for Latency Tolerance Reporting
> + //
> + // Arguments:
> + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> + // Arg1: Revision ID: 2
> + // Arg2: Function Index: 1, 4 or 6
> + // Arg3: Empty Package
> + //
> + // Return:
> + // A Package of four integers corresponding with the LTR encoding
> defined
> + // in the PCI Express Base Specification, as follows:
> + // Integer 0: Maximum Snoop Latency Scale
> + // Integer 1: Maximum Snoop Latency Value
> + // Integer 2: Maximum No-Snoop Latency Scale
> + // Integer 3: Maximum No-Snoop Latency Value
> + // These values correspond directly to the LTR Extended Capability
> Structure
> + // fields described in the PCI Express Base Specification.
> + //
> + //
> + // Switch by function index
> + //
> + Switch(ToInteger(Arg2)) {
> + //
> + // Function Index:0
> + // Standard query - A bitmask of functions supported
> + //
> + Case (0) {
> + Name(OPTS,Buffer(2){0,0})
> + CreateBitField(OPTS,0,FUN0)
> + CreateBitField(OPTS,4,FUN4)
> + CreateBitField(OPTS,6,FUN6)
> + CreateBitField(OPTS,8,FUN8)
> + CreateBitField(OPTS,9,FUN9)
> +
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + Store(1,FUN0)
> + if (LTRE){
> + Store(1,Fun6)
> + }
> + if (OBFF){
> + Store(1,Fun4)
> + }
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3
> + Store(1,Fun8)
> + Store(1,Fun9)
> + }
> + }
> + }
> + Return (OPTS)
> + }
> + //
> + // Function Index: 4
> + //
> + Case(4) {
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + if (OBFN){
> + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable,
> offset 4[08h]
> + } else {
> + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0})
> + }
> + }
> + }
> + //
> + // Function Index: 6
> + // LTR Extended Capability Structure
> + //
> + Case(6) {
> + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2
> + if (LTRN){
> + if (LOr(LEqual(LMSL, 0),LEqual(LNSL, 0)))
> + {
> + if (LEqual (PCHS, SPTH)) {
> + Store (0x0846, LMSL)
> + Store (0x0846, LNSL)
> + } elseif (LEqual (PCHS, SPTL)) {
> + Store (0x1003, LMSL)
> + Store (0x1003, LNSL)
> + }
> + }
> + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))
> + Store(And(LMSL,0x3FF), Index(LTRV, 1))
> + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))
> + Store(And(LNSL,0x3FF), Index(LTRV, 3))
> +
> + Return (LTRV)
> + } else {
> + Return (0)
> + }
> + }
> + }
> + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for
> Avoiding Power-On Reset Delay Duplication on Sx Resume
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
> + return (1)
> + }
> + }
> + }
> + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for
> Specifying Device Readiness Durations
> + if(LEqual(ECR1,1)){
> + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3
> + return(Package(5){50000,Ones,Ones,50000,Ones})
> + }
> + }
> + }
> + } // End of switch(Arg2)
> + } // End of if
> + return (Buffer() {0x00})
> + } // End of _DSM
> +
> + Device(PXSX)
> + {
> + Name(_ADR, 0x00000000)
> +
> + // NOTE: Any PCIE Hot-Plug dependency for this port is
> + // specific to the CRB. Please modify the code based on
> + // your platform requirements.
> + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4
> state
> + }
> +
> + //
> + // PCI_EXP_STS Handler for PCIE Root Port
> + //
> + Method(HPME,0,Serialized) {
> + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists
> and has PME SCI Status set...
> + Notify (PXSX, 0x2) //notify child device; this will cause its driver to clear
> PME_Status from device
> + Store(1,PMSX) // clear rootport's PME SCI status
> + Store(1,PSPX) // consume one pending PME notification to prevent it
> from blocking the queue
> + }
> + }
> +
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> new file mode 100644
> index 0000000000..4150833906
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Sata.asl
> @@ -0,0 +1,50 @@
> +/** @file
> +
> + @copyright
> + Copyright 2013 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#define ROOTPORT_READ 0
> +#define ROOTPORT_WRITE 1
> +#define ENDPOINT_READ 2
> +#define ENDPOINT_WRITE 3
> +
> +//
> +// SDSM is Device Specific Method supporting AHCI DEVSLP
> +// It is not guaranteed to be available on every boot
> +//
> +// move one level up to Pch.asl
> +
> + Method(_DSM,4,serialized){
> + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) };
> + if(CondRefOf(\_SB.PC00.SAT0.SDSM)) { return
> (\_SB.PC00.SAT0.SDSM(Arg0,Arg1,Arg2,Arg3)) };
> + Return(Buffer() {0})
> + }
> +
> + Device(PRT0)
> + {
> + Name(_ADR,0x0000FFFF) // Port 0
> + }
> + Device(PRT1)
> + {
> + Name(_ADR,0x0001FFFF) // Port 1
> + }
> + Device(PRT2)
> + {
> + Name(_ADR,0x0002FFFF) // Port 2
> + }
> + Device(PRT3)
> + {
> + Name(_ADR,0x0003FFFF) // Port 3
> + }
> + Device(PRT4)
> + {
> + Name(_ADR,0x0004FFFF) // Port 4
> + }
> + Device(PRT5)
> + {
> + Name(_ADR,0x0005FFFF) // Port 5
> + }
> +
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> new file mode 100644
> index 0000000000..5b9d7ed57e
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch
> Xhci.asl
> @@ -0,0 +1,558 @@
> +/** @file
> +
> + @copyright
> + Copyright 2010 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +External(\_SB.PC00.XHCI.PS0X, MethodObj)
> +External(\_SB.PC00.XHCI.PS3X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj)
> +External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj)
> +
> +
> +Scope(\_SB_.PC00.XHCI) {
> +
> + OperationRegion(XPRT,PCI_Config,0x00,0x100)
> + Field(XPRT,AnyAcc,NoLock,Preserve)
> + {
> + DVID, 16,
> + Offset(0x74),
> + D0D3, 2, // 0x74 BIT[1:0]
> + , 6,
> + PMEE, 1, // PME Enable
> + , 6,
> + PMES, 1, // PME Status
> + Offset(0xA8), // SSCFG Reg for WPTLP
> + , 13,
> + MW13, 1, // 0xA8 BIT[13]
> + MW14, 1, // 0xA8 BIT[14]
> + , 17,
> + Offset(0xB0), // SSCFG Reg for LPTLP
> + , 13,
> + MB13, 1, // 0xB0 BIT[13]
> + MB14, 1, // 0xB0 BIT[14]
> + , 17,
> + Offset(0xD0),
> + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
> + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
> + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
> + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
> + }
> +
> + //
> + // Variable to store the maximum D state supported in S0.
> + //
> + Name (XFLT, 0)
> + //
> + // XHCI controller won't go into D3Hot during S0 until _DSM method is
> evaluated by filter driver.
> + //
> + Method(_DSM,4,serialized){
> + If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> + //
> + // Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23
> + //
> + If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf,
> 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 }))
> + {
> + //
> + // Only Supported value is "0x3"
> + //
> + If(LEqual(Arg1, 0x3))
> + {
> + Store(Arg1,XFLT)
> + }
> + }
> + Return(Buffer() {0})
> + }
> +
> + Method(_S3D, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S4D, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S3W, 0, NotSerialized)
> + {
> + Return(3)
> + }
> + Method(_S4W, 0, NotSerialized)
> + {
> + Return(3)
> + }
> +
> + //
> + // Once the filter driver is installed, D3 is allowed.
> + //
> + Method(_S0W, 0x0, NotSerialized)
> + {
> + If(LEqual(XFLT, Zero))
> + {
> + Return(0x0)
> + }
> + Else
> + {
> + Return(0x3)
> + }
> + }
> +
> + Method(_PRW, 0)
> + {
> + Return(GPRW(0x6D, 4)) // can wakeup from S4 state
> + }
> +
> + Method(_DSW, 3)
> + {
> + Store(Arg0, PMEE)
> + }
> +
> + Method(_INI) {
> + // _INI for RTD3 run conditionally if implemented in platform specific
> code
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3
> + \_SB.PC00.XHCI.RHUB.INIR()
> + }
> + }
> +
> + //
> + // GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME
> + //
> + Method(GPEH)
> + {
> + If(LEqual(DVID, 0xFFFF)) {
> + Return()
> + }
> + Store(PMES, Local0)
> + Store(1, PMES) // clear PME Status
> + If(LAnd(PMEE, Local0)) {
> + Notify(XHCI, 0x02)
> + }
> + }
> +
> + OperationRegion(XHCP, SystemMemory, Add(MCFG, 0xA0000), 0x100)
> + Field(XHCP,AnyAcc,Lock,Preserve)
> + {
> + Offset(0x4),
> + PDBM, 16,
> + Offset(0x10),
> + MEMB, 64
> + }
> +
> + //
> + // USRA (USbR port Address), method for calculating address of first USBR
> port in XHCI controller
> + //
> + Method(USRA,0,Serialized) {
> + If(LEqual(PCHV, SPTH)) { // SPT-H
> + Return (15)
> + } Else { // SPT-LP
> + Return (11)
> + }
> + }
> +
> + //
> + // SSPA (SuperSpeed Port Address), method for calculating address of
> first SS port in XHCI controller
> + //
> + Method(SSPA,0,Serialized) {
> + If(LEqual(PCHV, SPTH)) { // SPT-H
> + Return (17)
> + } Else { // SPT-LP
> + Return (13)
> + }
> + }
> +
> + Name(XRST, Zero)
> +
> + Method(_PS0,0,Serialized)
> + {
> +
> + If(LEqual(^DVID,0xFFFF))
> + {
> + Return()
> + }
> +
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + //
> + // Switch to D0
> + //
> + Store(0,^D0D3)
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + //
> + //
> + //
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + //
> + // Call platform XHC PS0 method if present
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.PS0X))
> + {
> + \_SB.PC00.XHCI.PS0X()
> + }
> + //
> + //
> + If(LAnd(UWAB,LEqual(D0D3,0))) {
> +
> + //
> + // If the USB WA Bit is set and any XHCI or XDCI controller is in D0
> + //
> + //
> + // USB2 PHPY Power Gating - SW WA
> + //
> + // 1. BIOS writes a new command to the MTPMC register to cause the
> PMC to disable power gating
> + Store(1,MPMC)
> +
> + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
> + // In parallel and in response to the previous command from BIOS,
> PMC FW will:
> + // * Make the USB2 force common lane PG match the BIOS policy
> (common lane PG disallowed)
> + // * Disable SUS power gating in XHCI
> + // * Wait for USB2 PHY side_pok to be 1
> + // * Disable core power gating in USB2 PHY
> + // * Disable common lane power gating in USB2 PHY (probably not
> necessary, consider removal)
> + // * Wait for USB2 SUS restoration status to be set, and do USB2
> SUS power gating restoration
> + // * Get the PHY in the correct state before allowing transition to
> D0.
> + // * Clear MSG_FULL_STS
> + // BIOS sees MSG_FULL_STS clear and exits the method
> + //
> + While(PMFS) {
> + Sleep(10)
> + }
> + } // End If(UWAB)
> +
> + }
> +
> + Method(_PS3,0,Serialized)
> + {
> +
> + If(LEqual(^DVID,0xFFFF))
> + {
> + Return()
> + }
> +
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + //
> + // Switch back to D0
> + //
> + Store(0,^D0D3)
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + //
> + //
> + //
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + //
> + // Switch back to D3
> + //
> + Store(3,^D0D3)
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + //
> + // Call platform XHC PS3 method if present
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.PS3X))
> + {
> + \_SB.PC00.XHCI.PS3X()
> + }
> + If(LAnd(UWAB,LEqual(D0D3,3))) {
> + //
> + // If the USB WA Bit is set and XHCI is in D3
> + //
> +
> + // 1. BIOS writes a new command to the MTPMC register to enable
> power gating
> + Store(3,MPMC)
> +
> + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0
> + // In parallel and in response to the previous command from BIOS,
> PMC FW will:
> + // * Make the USB2 force common lane PG match the BIOS policy
> (common lane PG allowed)
> + // * Enable SUS power gating in XHCI
> + // * Enable core power gating in USB2 PHY
> + // * Enable common lane power gating in the USB2 PHY
> + // * Clear MSG_FULL_STS
> + // BIOS sees MSG_FULL_STS clear and exits the method
> + //
> + While(PMFS) {
> + Sleep(10)
> + }
> + } // End If(UWAB)
> + }
> +
> +
> + // Apply S3 workaround.
> + // Arguments :
> + // None
> + // Changes 8090 Bit 10 before S3.
> + //
> + Method(XHCS,0, Serialized) {
> + Store(^MEMB,Local2) // Save MBAR
> + Store(^PDBM,Local1) // Save CMD
> +
> + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME
> +
> + Store(\XWMB,^MEMB) // Set MBAR
> + Or(Local1,0x0002,^PDBM) // Set MSE
> +
> + OperationRegion(MC11,SystemMemory,\XWMB,0x9000)
> + Field(MC11,DWordAcc,Lock,Preserve)
> + {
> + Offset(0x8090), // HC Transfer Manager - TRM
> + , 10,
> + UCLI, 1, // CLEAR IN EP
> + }
> +
> + Store(0x1,UCLI)
> +
> + And(^PDBM,Not(0x02),^PDBM) // Clear MSE
> +
> + Store(Local2,^MEMB) // Restore MBAR
> + Store(Local1,^PDBM) // Restore CMD
> +
> + }
> +
> + //
> + //
> + // Check for XHCI switch UUID
> + //
> + // Arguments:
> + // Arg0 (Buffer) : UUID
> + //
> + // Returns:
> + // 1: It's valid UUID
> + // 0: Invalid UUID
> + //
> + Method(CUID,1,Serialized) {
> + If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) {
> + Return(1)
> + }
> + Return(0)
> + }
> +
> + Device(RHUB)
> + {
> + Name(_ADR, Zero)
> +
> + // PS0 Method for xHCI Root Hub
> + Method(_PS0,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS0 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS0X()
> + }
> + }
> +
> + // PS2 Method for xHCI Root Hub
> + Method(_PS2,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS2 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS2X()
> + }
> + }
> +
> + // PS3 Method for xHCI Root Hub
> + Method(_PS3,0,Serialized)
> + {
> + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF))
> + {
> + Return()
> + }
> + //
> + // Call platform XHC.RHUB PS3 method if present.
> + //
> + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X))
> + {
> + \_SB.PC00.XHCI.RHUB.PS3X()
> + }
> + }
> +
> + //
> + // High Speed Ports (without USBR)
> + //
> + Device(HS01)
> + {
> + Name(_ADR, 0x01)
> + }
> +
> + Device(HS02)
> + {
> + Name(_ADR, 0x02)
> + }
> +
> + Device(HS03)
> + {
> + Name(_ADR, 0x03)
> + }
> +
> + Device(HS04)
> + {
> + Name(_ADR, 0x04)
> + }
> +
> + Device(HS05)
> + {
> + Name(_ADR, 0x05)
> + }
> +
> + Device(HS06)
> + {
> + Name(_ADR, 0x06)
> + }
> +
> + Device(HS07)
> + {
> + Name(_ADR, 0x07)
> + }
> +
> + Device(HS08)
> + {
> + Name(_ADR, 0x08)
> + }
> +
> + Device(HS09)
> + {
> + Name(_ADR, 0x09)
> + }
> +
> + Device(HS10)
> + {
> + Name(_ADR, 0x0A)
> + }
> +
> + //
> + // USBR port will be known as USBR instead of HS09 / HS15
> + //
> + Device(USR1)
> + {
> + Method(_ADR) { Return (Add(USRA(),0)) }
> + }
> +
> + //
> + // USBR port 2 will be known as USBR instead of xxxx
> + //
> + Device(USR2)
> + {
> + Method(_ADR) { Return (Add(USRA(),1)) }
> + }
> +
> + //
> + // Super Speed Ports
> + //
> + Device(SS01)
> + {
> + Method(_ADR) { Return (Add(SSPA(),0)) }
> + }
> +
> + Device(SS02)
> + {
> + Method(_ADR) { Return (Add(SSPA(),1)) }
> + }
> +
> + Device(SS03)
> + {
> + Method(_ADR) { Return (Add(SSPA(),2)) }
> + }
> +
> + Device(SS04)
> + {
> + Method(_ADR) { Return (Add(SSPA(),3)) }
> + }
> +
> + Device(SS05)
> + {
> + Method(_ADR) { Return (Add(SSPA(),4)) }
> + }
> +
> + Device(SS06)
> + {
> + Method(_ADR) { Return (Add(SSPA(),5)) }
> + }
> +
> + } // device rhub
> +} //scope
> +
> +//
> +// SPT-H
> +//
> +
> + Scope(\_SB_.PC00.XHCI.RHUB) {
> +
> +
> +
> + Device(HS11)
> + {
> + Name(_ADR, 0xB)
> + }
> +
> +
> + Device(HS12)
> + {
> + Name(_ADR, 0xC)
> + }
> +
> + Device(HS13)
> + {
> + Name(_ADR, 0xD)
> + }
> +
> + Device(HS14)
> + {
> + Name(_ADR, 0xE)
> + }
> +
> + Device(SS07)
> + {
> + Method(_ADR) { Return (Add(SSPA(),6)) }
> + }
> +
> + Device(SS08)
> + {
> + Method(_ADR) { Return (Add(SSPA(),7)) }
> + }
> +
> + Device(SS09)
> + {
> + Method(_ADR) { Return (Add(SSPA(),8)) }
> + }
> +
> + Device(SS10)
> + {
> + Method(_ADR) { Return (Add(SSPA(),9)) }
> + }
> +
> + } //scope
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> new file mode 100644
> index 0000000000..cfacfdbfd4
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 1_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA1,0)) {
> + Return (RPA1)
> + } Else {
> + Return (0x001C0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> new file mode 100644
> index 0000000000..14d239597c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 2_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA2,0)) {
> + Return (RPA2)
> + } Else {
> + Return (0x001C0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> new file mode 100644
> index 0000000000..e116aa3fcf
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 3_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA3,0)) {
> + Return (RPA3)
> + } Else {
> + Return (0x001C0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> new file mode 100644
> index 0000000000..a89ba41f87
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 4_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA4,0)) {
> + Return (RPA4)
> + } Else {
> + Return (0x001C0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> new file mode 100644
> index 0000000000..82ac284b8c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 5_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA5,0)) {
> + Return (RPA5)
> + } Else {
> + Return (0x001C0004)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> new file mode 100644
> index 0000000000..153b4b3fce
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 6_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA6,0)) {
> + Return (RPA6)
> + } Else {
> + Return (0x001C0005)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> new file mode 100644
> index 0000000000..b8f93ff22b
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 7_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA7,0)) {
> + Return (RPA7)
> + } Else {
> + Return (0x001C0006)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> new file mode 100644
> index 0000000000..ad786680b1
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 8_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA8,0)) {
> + Return (RPA8)
> + } Else {
> + Return (0x001C0007)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> new file mode 100644
> index 0000000000..8fea09fb6d
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP0
> 9_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPA9,0)) {
> + Return (RPA9)
> + } Else {
> + Return (0x001D0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> new file mode 100644
> index 0000000000..e5faa36089
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 0_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAA,0)) {
> + Return (RPAA)
> + } Else {
> + Return (0x001D0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> new file mode 100644
> index 0000000000..f35101300c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 1_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAB,0)) {
> + Return (RPAB)
> + } Else {
> + Return (0x001D0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> new file mode 100644
> index 0000000000..b8b8b305cd
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 2_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAC,0)) {
> + Return (RPAC)
> + } Else {
> + Return (0x001D0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> new file mode 100644
> index 0000000000..c81ce74af9
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 3_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAD,0)) {
> + Return (RPAD)
> + } Else {
> + Return (0x001D0004)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> new file mode 100644
> index 0000000000..3a79d7b90b
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 4_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAE,0)) {
> + Return (RPAE)
> + } Else {
> + Return (0x001D0005)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> new file mode 100644
> index 0000000000..6c5e812a02
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 5_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAF,0)) {
> + Return (RPAF)
> + } Else {
> + Return (0x001D0006)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> new file mode 100644
> index 0000000000..0099005840
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 6_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAG,0)) {
> + Return (RPAG)
> + } Else {
> + Return (0x001D0007)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> new file mode 100644
> index 0000000000..745d5523b0
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 7_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAH,0)) {
> + Return (RPAH)
> + } Else {
> + Return (0x001B0000)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> new file mode 100644
> index 0000000000..e32e1ab276
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 8_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAI,0)) {
> + Return (RPAI)
> + } Else {
> + Return (0x001B0001)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> new file mode 100644
> index 0000000000..06b8a23ab4
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP1
> 9_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAJ,0)) {
> + Return (RPAJ)
> + } Else {
> + Return (0x001B0002)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> new file mode 100644
> index 0000000000..baa96d405c
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP2
> 0_ADR.asl
> @@ -0,0 +1,15 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (_ADR, 0) {
> + If (LNotEqual(RPAK,0)) {
> + Return (RPAK)
> + } Else {
> + Return (0x001B0003)
> + }
> +}
> diff --git
> a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> new file mode 100644
> index 0000000000..4c1dd36692
> --- /dev/null
> +++
> b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Trac
> eHubDebug.asl
> @@ -0,0 +1,150 @@
> +/** @file
> + Trace Hub debug library for ASL code.
> +
> + @copyright
> + Copyright 2015 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +External(PTHM, IntObj)
> +External(\_SB.PC00.PTHT.THEN, MethodObj, IntObj)
> +External(\_SB.PTHH.THEN, MethodObj, IntObj)
> +
> +Name (THMN, 0x20) // Master number should align with
> gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster
> +Name (THCN, 0x16) // Channel number could be different from
> gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel, 0~80h are available
> +
> +//
> +// @note Only include register definition macros in ASL.
> +// GCC will leak C function definitions in to ASL
> +// code, causing compilation errors in some cases.
> +//
> +#include <PchReservedResources.h>
> +#include <Register/PchRegsTraceHub.h>
> +
> +Scope(\) {
> + // Trace Hub debug address
> + // This is internal helper runtine of THDS
> + // Arg0 : Master number
> + // Arg1 : Channel number
> + Method (THDA, 2, Serialized) {
> + // Local0 = PCH_TRACE_HUB_SW_BASE_ADDRESS + 0x40 *
> (V_PCH_TRACE_HUB_MTB_CHLCNT * (Master -
> V_PCH_TRACE_HUB_MTB_STHMSTR)) + 0x40 * Channel;
> + Store (PCH_TRACE_HUB_SW_BASE_ADDRESS, Local0)
> + Add (Local0, Multiply (0x40, Multiply (V_PCH_TRACE_HUB_MTB_CHLCNT,
> Subtract (Arg0, V_PCH_TRACE_HUB_MTB_STHMSTR))), Local0)
> + Add (Local0, Multiply (0x40, Arg1), Local0)
> + Return (Local0)
> + }
> +
> + // String to raw data
> + // This is internal helper runtine of THDS
> + // Arg0 : string
> + // Arg1 : Index
> + // Arg2 : size
> + Method (STRD, 3, Serialized) {
> + If (LGreater (Add (Arg1, Arg2), SizeOf (Arg0))) {
> + Return (0)
> + }
> + // Local0 is return value
> + // Lccal1 is loop index
> + // Local2 is char of string
> + // Local3 is buffer of string
> + ToBuffer (Arg0, Local3)
> + Store (0, Local0)
> + Store (0, Local1)
> + While (LLess (Local1, Arg2)) {
> + Store (DeRefOf (Index (Local3, Add (Arg1, Local1))), Local2)
> + Add (Local0, ShiftLeft (Local2, Multiply (8, Local1)), Local0)
> + Increment (Local1)
> + }
> + Return (Local0)
> + }
> +
> + // Trace Hub debug string
> + // Arg0 : debug string
> + Method (THDS, 1, Serialized) {
> + //
> + // Check if BIOS trace is enabled.
> + //
> + If (LEqual (PTHM, 0)) {
> + Return
> + } ElseIf (LEqual (PTHM, 1)) {
> + If (LNot (\_SB.PC00.PTHT.THEN())) {
> + Return
> + }
> + } ElseIf (LEqual (PTHM, 2)) {
> + If (LNot (\_SB.PTHH.THEN())) {
> + Return
> + }
> + } Else {
> + Return
> + }
> +
> + // Local0 is the length of string
> + // Local1 is the debug base address
> + Store (Sizeof (Arg0), Local0)
> + Store (THDA (THMN, THCN), Local1)
> + OperationRegion (THBA, SystemMemory, local1, 0x40)
> + Field (THBA, QWordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + QO00, 64,
> + }
> + Field (THBA, DWordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + DO00, 32,
> + Offset (0x10),
> + DO10, 32,
> + offset (0x30),
> + DO30, 32,
> + }
> + Field (THBA, WordAcc, NoLock, Preserve) {
> + Offset (0x00),
> + WO00, 16,
> + }
> + Field (THBA, ByteAcc, NoLock, Preserve) {
> + Offset (0x00),
> + BO00, 8,
> + }
> +
> + // time stamp
> + Store (0x01000242, DO10)
> + // length of string
> + Store (Local0, WO00)
> + // string
> + Store (0, Local6)
> + Store (Local0, Local7)
> + while (LGreaterEqual(Local7, 8)) {
> + Store (STRD (Arg0, Local6, 8), QO00)
> + Add (Local6, 8, Local6)
> + Subtract (Local7, 8, Local7)
> + }
> + If (LGreaterEqual(Local7, 4)) {
> + Store (STRD (Arg0, Local6, 4), DO00)
> + Add (Local6, 4, Local6)
> + Subtract (Local7, 4, Local7)
> + }
> + If (LGreaterEqual(Local7, 2)) {
> + Store (STRD (Arg0, Local6, 2), WO00)
> + Add (Local6, 2, Local6)
> + Subtract (Local7, 2, Local7)
> + }
> + If (LGreaterEqual(Local7, 1)) {
> + Store (STRD (Arg0, Local6, 1), BO00)
> + Add (Local6, 1, Local6)
> + Subtract (Local7, 1, Local7)
> + }
> + // flag
> + Store (0, DO30)
> + }
> +
> + // Trace Hub debug Hex string
> + // Arg0 : Integer, buffer
> + Method (THDH, 1, Serialized) {
> + THDS (ToHexString (Arg0))
> + }
> +
> + // Trace Hub debug decimal string
> + // Arg0 : Integer, buffer
> + Method (THDD, 1, Serialized) {
> + THDS (ToDecimalString (Arg0))
> + }
> +}
> diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> index c4993cb897..e03ee6d5d8 100644
> --- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
> @@ -19,6 +19,7 @@
> Security/Include
> Pch/SouthClusterLbg
> Pch/SouthClusterLbg/Include
> + Pch/SouthClusterLbg/AcpiTables/Dsdt
>
> Cpu/Include
>
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables Oram, Isaac W
@ 2022-02-09 3:21 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:21 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 4/8]
> WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables
>
> Static ACPI tables for WilsonCityRvp
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.
> aslc | 54 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG
> 2.aslc | 81 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs6
> 2.aslc | 72 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt6
> 2.aslc | 171 ++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hma
> t.aslc | 972 ++++++++++++++++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet
> .aslc | 61 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg
> .aslc | 74 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.
> aslc | 68 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct
> .aslc | 137 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.a
> slc | 48 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.
> aslc | 44 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt
> 10nm.aslc | 136 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.
> aslc | 89 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi
> .aslc | 53 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wdd
> t1.0.aslc | 74 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Ws
> mt.aslc | 74 ++
> 16 files changed, 2208 insertions(+)
>
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bd
> at.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bd
> at.aslc
> new file mode 100644
> index 0000000000..734f11200f
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bd
> at.aslc
> @@ -0,0 +1,54 @@
> +/** @file
> +
> + @copyright
> + Copyright 2005 - 2012 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Bdat.h>
> +
> +//
> +// Bdat Access Handler instance data structure
> +//
> +STATIC
> +EFI_BDAT_ACPI_DESCRIPTION_TABLE mBdatAcpiTable = \
> +{
> + {EFI_BDAT_TABLE_SIGNATURE, // Signature
> + sizeof (EFI_BDAT_ACPI_DESCRIPTION_TABLE), // Length
> + 0x01, // Revision [01]
> + //
> + // Checksum will be updated during boot
> + //
> + 0, // Checksum
> + {' ', // OEM ID
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '},
> + 0, // OEM Table ID
> + 0, // OEM Revision [0x00000000]
> + 0, // Creator ID
> + 0}, // Creator Revision
> + {0, // System Memory Address Space ID
> + 0,
> + 0,
> + 0,
> + //
> + // Pointer will be updated during boot
> + //
> + EFI_BDAT_ACPI_POINTER}
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + return (VOID*)&mBdatAcpiTable;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/D
> BG2.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/D
> BG2.aslc
> new file mode 100644
> index 0000000000..dcad37ac05
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/D
> BG2.aslc
> @@ -0,0 +1,81 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +
> +#include <IndustryStandard/DebugPort2Table.h>
> +#include <Acpi/Dbg2.h>
> +
> +
> +DBG2_DEBUG_TABLE DBG2 =
> +{
> + {
> + {EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE,
> + sizeof (DBG2_DEBUG_TABLE),
> + 0,
> +
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> +
> + //
> + // It is expected that these values will be programmed at runtime
> + //
> + {' ', ' ', ' ', ' ', ' ', ' '},
> +
> + 0,
> + 0,
> + 0,
> + 0
> + },
> + //
> + // Beginning of DBG2 specific fields
> + //
> + sizeof(EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE),
> + 1
> + },
> + {
> + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
> + sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT),
> + 1,
> + 2,
> + sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT) +
> sizeof(EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE) + 4,
> + 0,
> + 0,
> + EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
> + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550,
> + {0, 0},
> + sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT),
> + sizeof(EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT) +
> sizeof(EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE)
> + },
> + {
> + EFI_ACPI_6_2_SYSTEM_IO,
> + 16,
> + 0,
> + EFI_ACPI_6_2_BYTE,
> + 0x3F8
> + },
> + 4,
> + "."
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&DBG2;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Fac
> s62.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Fac
> s62.aslc
> new file mode 100644
> index 0000000000..48753f7939
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Fac
> s62.aslc
> @@ -0,0 +1,72 @@
> +/** @file
> +
> + @copyright
> + Copyright 1996 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Facs.h>
> +
> +//
> +// Firmware ACPI Control Structure
> +// Please modify all values in Facs.h only.
> +//
> +EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
> + EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
> + sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE),
> + //
> + // Hardware Signature will be updated at runtime
> + //
> + 0x00000000,
> +
> + EFI_ACPI_FIRMWARE_WAKING_VECTOR,
> + EFI_ACPI_GLOBAL_LOCK,
> + EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
> + EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
> + EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
> + {EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE},
> + EFI_ACPI_OSPM_FLAGS,
> + {EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE}
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Facs;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fad
> t62.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fad
> t62.aslc
> new file mode 100644
> index 0000000000..f37cf0a508
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fad
> t62.aslc
> @@ -0,0 +1,171 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +
> +#include <Acpi/Fadt.h>
> +
> +//
> +// Fixed ACPI Description Table
> +// Please modify all values in Fadt.h only.
> +//
> +EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> + {EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> + sizeof (EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE),
> + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + {' ', ' ', ' ', ' ', ' ', ' '}, // OEMID
> + 0, // OEM Table ID
> + EFI_ACPI_OEM_FADT_REVISION,
> + 0, // Creator ID
> + 0}, // Creator Revision
> + //
> + // These addresses will be updated at runtime
> + //
> + 0x00000000, // FIRMWARE_CTRL
> + 0x00000000, // DSDT
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_PREFERRED_PM_PROFILE,
> + EFI_ACPI_SCI_INT,
> + EFI_ACPI_SMI_CMD,
> + EFI_ACPI_ACPI_ENABLE,
> + EFI_ACPI_ACPI_DISABLE,
> + EFI_ACPI_S4_BIOS_REQ,
> + EFI_ACPI_PSTATE_CNT,
> +
> + EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
> + EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
> + EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
> + EFI_ACPI_PM1B_CNT_BLK_ADDRESS,
> + EFI_ACPI_PM2_CNT_BLK_ADDRESS,
> + EFI_ACPI_PM_TMR_BLK_ADDRESS,
> + EFI_ACPI_GPE0_BLK_ADDRESS,
> + EFI_ACPI_GPE1_BLK_ADDRESS,
> + EFI_ACPI_PM1_EVT_LEN,
> + EFI_ACPI_PM1_CNT_LEN,
> + EFI_ACPI_PM2_CNT_LEN,
> + EFI_ACPI_PM_TMR_LEN,
> + EFI_ACPI_GPE0_BLK_LEN,
> + EFI_ACPI_GPE1_BLK_LEN,
> + EFI_ACPI_GPE1_BASE,
> +
> + EFI_ACPI_CST_CNT,
> + EFI_ACPI_P_LVL2_LAT,
> + EFI_ACPI_P_LVL3_LAT,
> + EFI_ACPI_FLUSH_SIZE,
> + EFI_ACPI_FLUSH_STRIDE,
> + EFI_ACPI_DUTY_OFFSET,
> + EFI_ACPI_DUTY_WIDTH,
> + EFI_ACPI_DAY_ALRM,
> + EFI_ACPI_MON_ALRM,
> + EFI_ACPI_CENTURY,
> + EFI_ACPI_IAPC_BOOT_ARCH,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_FIXED_FEATURE_FLAGS | EFI_ACPI_6_2_SLP_BUTTON,
> + //
> + // Reset Register Block
> + //
> + {EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
> + EFI_ACPI_RESET_REG_BIT_WIDTH,
> + EFI_ACPI_RESET_REG_BIT_OFFSET,
> + EFI_ACPI_6_2_BYTE,
> + EFI_ACPI_RESET_REG_ADDRESS},
> +
> + EFI_ACPI_RESET_VALUE,
> + EFI_ACPI_RESERVED_WORD, // EFI_ACPI_6_2_ARM_BOOT_ARCH
> + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
> + //
> + // These addresses will be updated at runtime
> + //
> + 0x0000000000000000, // X_FIRMWARE_CTRL
> + 0x0000000000000000, // X_DSDT
> + //
> + // X_PM1a Event Register Block
> + //
> + {EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
> + EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_WORD,
> + EFI_ACPI_PM1A_EVT_BLK_ADDRESS},
> + //
> + // X_PM1b Event Register Block
> + //
> + {EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
> + EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_UNDEFINED,
> + EFI_ACPI_PM1B_EVT_BLK_ADDRESS},
> + //
> + // X_PM1a Control Register Block
> + //
> + {EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
> + EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_WORD,
> + EFI_ACPI_PM1A_CNT_BLK_ADDRESS},
> + //
> + // X_PM1b Control Register Block
> + //
> + {EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
> + EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_UNDEFINED,
> + EFI_ACPI_PM1B_CNT_BLK_ADDRESS},
> + //
> + // X_PM2 Control Register Block
> + //
> + {EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
> + EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_UNDEFINED,
> + EFI_ACPI_PM2_CNT_BLK_ADDRESS},
> + //
> + // X_PM Timer Control Register Block
> + //
> + {EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
> + EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_DWORD,
> + EFI_ACPI_PM_TMR_BLK_ADDRESS},
> + //
> + // X_General Purpose Event 0 Register Block
> + //
> + {EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_GPE0_BLK_BIT_WIDTH,
> + EFI_ACPI_GPE0_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_BYTE,
> + EFI_ACPI_GPE0_BLK_ADDRESS},
> + //
> + // X_General Purpose Event 1 Register Block
> + //
> + {EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
> + EFI_ACPI_GPE1_BLK_BIT_WIDTH,
> + EFI_ACPI_GPE1_BLK_BIT_OFFSET,
> + EFI_ACPI_6_2_UNDEFINED,
> + EFI_ACPI_GPE1_BLK_ADDRESS}
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the executable.
> + //
> + return (VOID*)&Fadt;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/H
> mat.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/H
> mat.aslc
> new file mode 100644
> index 0000000000..ae6efeaee5
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/H
> mat.aslc
> @@ -0,0 +1,972 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include "Acpi/Hmat.h"
> +
> +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
> + // EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
> + {
> + // EFI_ACPI_DESCRIPTION_HEADER
> + {
> + EFI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
> + sizeof (EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE),
> + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION,
> + 0x00, // Checksum, updated at runtime
> + {' ', ' ', ' ', ' ', ' ', ' '}, // OEM ID, programmed at runtime
> + 0,
> + EFI_ACPI_OEM_HMAT_REVISION,
> + 0,
> + 0
> + }, // EFI_ACPI_DESCRIPTION_HEADER
> + (UINT32) 0
> + }, // EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
> +
> + // Beginning of HMAT substructures
> +#if EFI_ACPI_HMAT_MSARS_COUNT > 0
> + { //
> MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE[EFI_ACPI_HMAT_MS
> ARS_COUNT]
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#if MC_MAX_NODE > 1
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 2
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 3
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 4
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 5
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 6
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 7
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 8
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 9
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 10
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 11
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 12
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 13
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 14
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> +#if MC_MAX_NODE > 15
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> + MSARS_INIT()
> +#endif
> + }, //
> MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE[EFI_ACPI_HMAT_MS
> ARS_COUNT]
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 0
> + { // LATENCY_BANDWIDTH_INFO_STRUCTURE
> Lbis[EFI_ACPI_HMAT_LBIS_COUNT]
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 1
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 2
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 3
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 4
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 5
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 6
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 7
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 8
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 9
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 10
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> +#if EFI_ACPI_HMAT_LBIS_COUNT > 11
> + LBIS_START()
> + RELATIVE_DISTANCE()
> +#if MC_MAX_NODE > 1
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 2
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 3
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 4
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 5
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 6
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 7
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 8
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 9
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 10
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 11
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 12
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 13
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 14
> + RELATIVE_DISTANCE()
> +#endif
> +#if MC_MAX_NODE > 15
> + RELATIVE_DISTANCE()
> +#endif
> + LBIS_END()
> +#endif
> + }, // LATENCY_BANDWIDTH_INFO_STRUCTURE
> Lbis[EFI_ACPI_HMAT_LBIS_COUNT]
> +#endif
> +#if EFI_ACPI_HMAT_MSCIS_COUNT > 0
> + { // MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE
> MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT]
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#if MC_MAX_NODE > 1
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 2
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 3
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 4
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 5
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 6
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 7
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 8
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 9
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 10
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 11
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 12
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 13
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 14
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> +#if MC_MAX_NODE > 15
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> + MSCIS_INIT()
> +#endif
> + }, // MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE
> MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT]
> +#endif
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the executable
> + //
> + return (VOID*)&Hmat;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hp
> et.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hp
> et.aslc
> new file mode 100644
> index 0000000000..37b680ad6b
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hp
> et.aslc
> @@ -0,0 +1,61 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Hpet.h>
> +
> +//
> +// High Precision Event Timer Table
> +// Please modify all values in Hpet.h only.
> +//
> +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = {
> + {EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, //
> Signature
> + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), //
> Length
> + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, //
> Revision [01]
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00, // Checksum
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + {' ',
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '},
> + 0,
> + EFI_ACPI_OEM_HPET_REVISION, // OEM Revision
> [0x00000001]
> + 0, // Creator ID
> + 0}, // Creator Revision
> + EFI_ACPI_EVENT_TIMER_BLOCK_ID, // Event Timer Block ID
> (4B) [0x8086A201]
> + {EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID, // 2
> [EFI_ACPI_6_2_SYSTEM_MEMORY]
> + EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH, // 3 [0x00]
> + EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET, // 4 [0x00]
> + EFI_ACPI_EVENT_TIMER_ACCESS_SIZE, // [0x00]
> + EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS}, // HPET Block
> BASE_ADDRESS (12B) [0x00000000FED00000]
> + EFI_ACPI_HPET_NUMBER, // HPET Number [00]
> + EFI_ACPI_MIN_CLOCK_TICK, // Main Counter Minimum
> Clock tick [0x0080]
> + EFI_ACPI_HPET_ATTRIBUTES // Page Protection & OEM
> attribute [0x00]
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Hpet;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mc
> fg.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/M
> cfg.aslc
> new file mode 100644
> index 0000000000..6e9a84aa49
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/M
> cfg.aslc
> @@ -0,0 +1,74 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Mcfg.h>
> +
> +//
> +// MCFG Table definition
> +//
> +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE
> Mcfg = {
> +
> {{EFI_ACPI_6_2_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TA
> BLE_SIGNATURE,
> + sizeof
> (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE),
> +
> EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_RE
> VISION,
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> + //
> + // It is expected that these values will be programmed at runtime
> + //
> + {' ',
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '},
> +
> + 0,
> + EFI_ACPI_OEM_MCFG_REVISION,
> + 0,
> + 0},
> + //
> + // Beginning of MCFG specific fields
> + //
> + EFI_ACPI_RESERVED_QWORD},
> + //
> + // Sample Memory Mapped Configuration Space Base Address Structure
> + //
> + // 0x0, // Base Address
> + // 0x0, // PCI Segment Group Number
> + // 0x0, // Start Bus Number
> + // 0x0, // End Bus Number
> + // EFI_ACPI_RESERVED_DWORD, // Reserved
> + //
> + // Memory Mapped Configuration Space Base Address Structure
> + //
> +#if
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT > 0
> + {{0x0, // Base Address, will be updated by AcpiPlatform
> + 0x0, // PCI Segment Group Number
> + 0x0, // Start Bus Number
> + 0xff, // End Bus Number
> + EFI_ACPI_RESERVED_DWORD}} // Reserved
> +#endif //
> EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRE
> SS_STRUCTURE_COUNT
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Mcfg;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Mi
> gt.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Mi
> gt.aslc
> new file mode 100644
> index 0000000000..5efe5afee1
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Mi
> gt.aslc
> @@ -0,0 +1,68 @@
> +/** @file
> +
> + @copyright
> + Copyright 2005 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Migt.h>
> +
> +//
> +// Please modify all values in Migt.h only.
> +//
> +EFI_MIGT_ACPI_DESCRIPTION_TABLE Migt = {
> + {EFI_MIGT_ACPI_TABLE_SIGNATURE, // Signature
> + sizeof (EFI_MIGT_ACPI_DESCRIPTION_TABLE), // Length
> + EFI_MIGT_ACPI_DESCRIPTION_TABLE_REVISION, // Revision
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00, // Checksum
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + {' ',
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '},
> + 0,
> + EFI_MIGT_ACPI_OEM_REVISION, // OEM Revision
> + 0, // Creator ID
> + 0}, // Creator Revision
> + //
> + // MIGT Speicific Entries
> + // Control Register GAS structure
> + //
> + {EFI_MIGT_CR_ACPI_ADDRESS_SPACE_ID, // IO Type ID.
> + EFI_MIGT_CR_ACPI_REGISTER_BIT_WIDTH,
> + EFI_MIGT_CR_ACPI_REGISTER_BIT_OFFSET,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_MIGT_CR_ACPI_SMI_ADDRESS},
> +
> + MIGT_SMI_SERVICE_ID, // SMI Door Bell
> +
> + //
> + // Action Region GAS structure
> + //
> + {EFI_MIGT_AR_ACPI_ADDRESS_SPACE_ID, // Memory Type ID
> + EFI_MIGT_AR_ACPI_REGISTER_BIT_WIDTH,
> + EFI_MIGT_AR_ACPI_REGISTER_BIT_OFFSET,
> + EFI_ACPI_RESERVED_BYTE,
> + // update during boot
> + EFI_MIGT_AR_ACPI_MEMORY_ADDRESS}
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + return (VOID*)&Migt;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Ms
> ct.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Ms
> ct.aslc
> new file mode 100644
> index 0000000000..e0e1bebd0a
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Ms
> ct.aslc
> @@ -0,0 +1,137 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Msct.h>
> +
> +//
> +// Maximum System Characteristics Table definition
> +//
> +EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE Msct = {
> +
> {EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE
> ,
> + sizeof (EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE), //
> Length
> + EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION, //
> Revision
> + 0x00, // Checksum will be updated at runtime
> + {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
> + 0, // OemTableId
> + EFI_ACPI_OEM_MSCT_REVISION, // OemRevision
> + EFI_ACPI_CREATOR_ID, // CreaterId
> + EFI_ACPI_CREATOR_REVISION}, // CreaterRevision
> + //
> + // Beginning of MSCT specific fields
> + //
> + 0x00000038, // OffsetProxDomInfo
> + MAX_SOCKET - 1, // MaxNumProxDom
> + 0x00000000, // MaxNumClockDom
> + 0x0000000000000000, // MaxPhysicalAddress
> + //
> + // Proximity Domain Information Structure 0
> + //
> +
> {{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE
> _REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +
> +#if MAX_SOCKET > 1
> + //
> + // Proximity Domain Information Structure 1
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 2
> + //
> + // Proximity Domain Information Structure 2
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 3
> + //
> + // Proximity Domain Information Structure 3
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 4
> + //
> + // Proximity Domain Information Structure 4
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 5
> + //
> + // Proximity Domain Information Structure 5
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 6
> + //
> + // Proximity Domain Information Structure 6
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> +
> +#if MAX_SOCKET > 7
> + //
> + // Proximity Domain Information Structure 7
> + //
> +
> ,{EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_
> REVISION, // Revision
> + sizeof
> (EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE),
> // Length
> + 0x00000000, // ProxDomRangeLow
> + 0x00000000, // ProxDomRangeHigh
> + 0x00000000, // MaxProcessorCapacity
> + 0x0000000000000000} // MaxMemoryCapacity
> +#endif
> + }
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + return (VOID*)&Msct;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfi
> t.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfi
> t.aslc
> new file mode 100644
> index 0000000000..389c43ce3c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfi
> t.aslc
> @@ -0,0 +1,48 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Nfit.h>
> +
> +//
> +// NFIT Table
> +// Please modify all values in Nfit.h only.
> +//
> +NVDIMM_FW_INTERFACE_TABLE Nfit = {
> + NVDIMM_FW_INTERFACE_TABLE_SIGNATURE, // Signature
> + sizeof (NVDIMM_FW_INTERFACE_TABLE), // Length
> + NVDIMM_FW_INTERFACE_TABLE_REVISION, // Revision [01]
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00, // Checksum
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + {' ', // TODO any other static values to be filled in?
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '}
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Nfit;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pc
> at.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pc
> at.aslc
> new file mode 100644
> index 0000000000..e43c865c64
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pc
> at.aslc
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + @copyright
> + Copyright 2015 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Pcat.h>
> +
> +//
> +// PCAT Table
> +// Please modify all values in Pcat.h only.
> +//
> +NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE Pcat = {
> + NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_SIGNATURE, //
> Signature
> + sizeof (NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE), // Length
> + NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_REVISION, // Revision
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00, // Checksum
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + {' '}, // TODO any other static values?
> +
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Pcat;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pm
> tt10nm.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/P
> mtt10nm.aslc
> new file mode 100644
> index 0000000000..a0b4dc2756
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/P
> mtt10nm.aslc
> @@ -0,0 +1,136 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Pmtt.h>
> +//
> +// PMTT Table
> +//
> +#define PHYSICAL_COMP_IDENTIFIER \
> + {PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_DIMM_DEVICE), \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + 0xFFFFFFFF}
> +
> +#define SLOT \
> + {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_SLOT_DEVICE) - sizeof(ACPI_PMTT_DIMM_DEVICE),
> \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + PMTT_TYPE_SLOT_GUID, \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + PHYSICAL_COMP_IDENTIFIER}
> +
> +#define CHANNEL \
> + {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_CHANNEL_DEVICE) - MAX_DIMM *
> sizeof(ACPI_PMTT_SLOT_DEVICE), \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + PMTT_TYPE_CHANNEL_GUID, \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + {SLOT, \
> + SLOT} \
> + }
> +
> +#define MEM_IMC \
> + {ACPI_TOP_LEVEL_IMC, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_IMC_DEVICE) - MAX_MC_CH *
> sizeof(ACPI_PMTT_CHANNEL_DEVICE), \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + {CHANNEL, \
> + CHANNEL} \
> + }
> +
> +#define DIE \
> + {ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_DIE_DEVICE) - MAX_IMC *
> sizeof(ACPI_PMTT_IMC_DEVICE), \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + PMTT_TYPE_DIE_GUID, \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + {MEM_IMC, \
> + MEM_IMC, \
> + MEM_IMC, \
> + MEM_IMC}}
> +
> +#define SKT_LEVEL \
> + {ACPI_TOP_LEVEL_SOCKET, \
> + EFI_ACPI_RESERVED_BYTE, \
> + sizeof (ACPI_PMTT_SOCKET_DEVICE) - sizeof(ACPI_PMTT_DIE_DEVICE),
> \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + 0x00000000, \
> + 0x00000000, \
> + EFI_ACPI_RESERVED_BYTE, \
> + {DIE} \
> + },
> +#pragma pack(1)
> +
> +ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE mPmttTable = {
> + {ACPI_PMTT_TABLE_SIGNATURE, // Signature 'PMTT'
> + sizeof (ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE), // Length
> + ACPI_PMTT_TABLE_REVISION, // Revision
> + 0x00, // CheckSum
> + {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
> + 0, // OemTableId
> + ACPI_PMTT_OEM_REVISION, // OemRevision
> + EFI_ACPI_CREATOR_ID, // CreaterId
> + EFI_ACPI_CREATOR_REVISION}, // CreaterRevision
> + 0, // NumOfMemoryDevices
> + { SKT_LEVEL
> +#if MAX_SOCKET > 1
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 2
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 3
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 4
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 5
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 6
> + SKT_LEVEL
> +#endif
> +#if MAX_SOCKET > 7
> + SKT_LEVEL
> +#endif
> + }
> +};
> +
> +#pragma pack()
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +{
> + return (VOID*)&mPmttTable;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Sp
> cr.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Sp
> cr.aslc
> new file mode 100644
> index 0000000000..26603102a2
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Sp
> cr.aslc
> @@ -0,0 +1,89 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2002 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> +#include <Acpi/Spcr.h>
> +
> +//
> +// Serial Port Console Redirection Table
> +// Please modify all values in Spcr.h only.
> +//
> +
> +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> +
> {EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> + sizeof (EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE),
> + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
> +
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> +
> + //
> + // It is expected that these values will be programmed at runtime
> + //
> + {' ', ' ', ' ', ' ', ' ', ' '},
> +
> + 0,
> + EFI_ACPI_OEM_SPCR_REVISION,
> + 0,
> + 0},
> +
> + //
> + // Beginning of SPCR specific fields
> + //
> + EFI_ACPI_INTERFACE_TYPE,
> + {EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE},
> +
> + //
> + // Base Address Block
> + //
> + {EFI_ACPI_BASE_ADDRESS_ADDRESS_SPACE_ID,
> + EFI_ACPI_BASE_ADDRESS_BIT_WIDTH,
> + EFI_ACPI_BASE_ADDRESS_BIT_OFFSET,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_BASE_ADDRESS_ADDRESS},
> +
> + EFI_ACPI_INTERRUPT_TYPE,
> + EFI_ACPI_IRQ,
> + EFI_ACPI_GLOBAL_SYSTEM_INTERRUPT,
> + EFI_ACPI_BAUD_RATE,
> + EFI_ACPI_PARITY,
> + EFI_ACPI_STOP_BITS,
> + EFI_ACPI_FLOW_CONTROL,
> + EFI_ACPI_TERMINAL_TYPE,
> + EFI_ACPI_LANGUAGE,
> + EFI_ACPI_PCI_DEVICE_ID,
> + EFI_ACPI_PCI_VENDOR_ID,
> + EFI_ACPI_PCI_BUS_NUMBER,
> + EFI_ACPI_PCI_DEVICE_NUMBER,
> + EFI_ACPI_PCI_FUNCTION_NUMBER,
> + EFI_ACPI_PCI_FLAGS,
> + EFI_ACPI_PCI_SEGMENT,
> + EFI_ACPI_RESERVED_DWORD
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the exeutable
> + //
> + return (VOID*)&Spcr;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Sp
> mi.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Sp
> mi.aslc
> new file mode 100644
> index 0000000000..74855daee4
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Sp
> mi.aslc
> @@ -0,0 +1,53 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/Spmi.h>
> +
> +//
> +// Server processor management interface table definition
> +//
> +EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE Spmi =
> {
> +
> {EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SI
> GNATURE,
> + sizeof
> (EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE),
> // Length
> +
> EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISIO
> N, // Revision
> + 0x00, // Checksum will be updated at
> runtime
> + {'I', 'N', 'T', 'E', 'L', ' '}, // OemId
> + 0, // OemTableId
> + EFI_ACPI_OEM_SPMI_REVISION, // OemRevision
> + 0, // CreaterId
> + 0}, // CreaterRevision
> + //
> + // Beginning of Spmi specific fields
> + //
> + 0x00, // InterfaceType
> + 0x01, // Reserved37, always 1
> + EFI_ACPI_SPMI_SPECIFICATION_REVISION, //
> SpecificationRevision
> + 0x00, // InterruptType
> + 0x00, // GPE
> + 0x00, // Reserved42
> + 0x00, // PciDeviceFlag
> + 0x00000000, // GlobalSystemInterrupt
> + {0x00, 0x00, 0x00, 0x00, 0x00}, // GAS
> + 0x00, // UidByte1
> + 0x00, // UidByte2
> + 0x00, // UidByte3
> + 0x00, // UidByte4
> + 0x00 // Reserved64
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + return (VOID*)&Spmi;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/W
> ddt1.0.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/W
> ddt1.0.aslc
> new file mode 100644
> index 0000000000..fe0db504fd
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/W
> ddt1.0.aslc
> @@ -0,0 +1,74 @@
> +/** @file
> +
> + @copyright
> + Copyright 1999 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Statements that include other files
> +//
> +#include <Acpi/WatchdogDescriptionTable.h>
> +#include <Acpi/Wddt.h>
> +
> +//
> +// Watchdog Description Table , ACPI 6.2 compliant
> +//
> +EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE Wddt = {
> + {EFI_ACPI_WDDT_SIGNATURE,
> + sizeof (EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE),
> + EFI_ACPI_WDDT_DESCRIPTION_TABLE_REVISION,
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> + //
> + // It is expected that these values will be programmed at runtime
> + //
> + {' ',
> + ' ',
> + ' ',
> + ' ',
> + ' ',
> + ' '},
> + 0,
> + 0,
> + 0,
> + 0},
> + //
> + // WDDT specific fields
> + //
> + //
> + // This is LPC bridge VID it must be patched in
> + //
> + 0,
> + EFI_ACPI_WDDT_SPEC_VERSION,
> + EFI_ACPI_WDDT_TABLE_VERSION,
> + //
> + // Base Address
> + //
> + {0x01,
> + 0xff,
> + 0x00,
> + 0x00,
> + //
> + // This is AcpiBase(PmBase)+60 and must be patched in
> + //
> + 0000},
> + EFI_ACPI_WDDT_TIMER_MAX_COUNT,
> + EFI_ACPI_WDDT_TIMER_MIN_VALUE,
> + EFI_ACPI_WDDT_TIMER_PERIOD_COUNT,
> + EFI_ACPI_WDDT_STATUS_AVAILABLE,
> + 00
> +
> +};
> +
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + return (VOID*)&Wddt;
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/W
> smt.aslc
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/W
> smt.aslc
> new file mode 100644
> index 0000000000..83484b7cd7
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/W
> smt.aslc
> @@ -0,0 +1,74 @@
> +/** @file
> +
> + @copyright
> + Copyright 2017 - 2020 Intel Corporation.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +
> + //
> + // Statements that include other files
> + //
> +
> +#include <Acpi/Wsmt.h>
> +
> + //
> + // Windows SMM Security Mitigations Table
> + // Please modify all values in Wsmt.h only.
> + //
> +
> +ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE Wsmt = {
> + //
> + // Header
> + //
> + {
> + ACPI_WSMT_SIGNATURE,
> + ACPI_WSMT_LENGTH,
> + EFI_ACPI_WSMT_REVISION,
> +
> + //
> + // Checksum will be updated at runtime
> + //
> + 0x00,
> +
> + //
> + // It is expected that these values will be updated at runtime
> + //
> + { ' ', ' ', ' ', ' ', ' ', ' ' },
> + 0,
> + ACPI_OEM_WSMT_REVISION,
> + 0,
> + 0
> + },
> + //
> + // Protection Flags
> + //
> + {
> + { 0 }
> + }
> +
> +};
> +
> +#if defined (__GNUC__)
> +VOID*
> +ReferenceAcpiTable (
> + VOID
> + )
> +
> +{
> + //
> + // Reference the table being generated to prevent the optimizer from
> removing the
> + // data structure from the executable
> + //
> + return (VOID*)&Wsmt;
> +}
> +#else
> +VOID
> +main (
> + VOID
> + )
> +
> +{
> +}
> +#endif
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table Oram, Isaac W
@ 2022-02-09 3:21 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:21 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 7/8]
> WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table
>
> Add PreBuild step to generate the AML offset table for the ACPI tables.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
> Platform/Intel/.gitignore | 2 +
> Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc |
> 41 +++++++++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffset
> s.inf | 26 ++++++++
> Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py |
> 63 ++++++++++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg |
> 15 +++++
> 5 files changed, 147 insertions(+)
>
> diff --git a/Platform/Intel/.gitignore b/Platform/Intel/.gitignore new file
> mode 100644 index 0000000000..548fee5bea
> --- /dev/null
> +++ b/Platform/Intel/.gitignore
> @@ -0,0 +1,2 @@
> +WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
> +__init__.py
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
> new file mode 100644
> index 0000000000..2e5ebf432a
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
> @@ -0,0 +1,41 @@
> +## @file
> +# Build file for generating AML offset table # # @copyright # Copyright
> +(C) 2021 Intel Corporation.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent ##
> +
> +[Defines]
> + PLATFORM_NAME = $(RP_PKG)
> + PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> + OUTPUT_DIRECTORY = Build/$(RP_PKG)
> + SUPPORTED_ARCHITECTURES = IA32|X64
> + BUILD_TARGETS = DEBUG|RELEASE
> + PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
> + DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
> + PEI_ARCH = IA32
> + DXE_ARCH = X64
> +
> +!if $(CPUTARGET) == "CPX"
> + DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
> + DEFINE IIO_INSTANCE = Skx
> +!elseif $(CPUTARGET) == "ICX"
> + DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
> + DEFINE IIO_INSTANCE = Icx
> +!else
> + DEFINE IIO_INSTANCE = UnknownCpu
> +!endif
> +
> + #
> + # Platform On/Off features are defined here # !include
> + $(RP_PKG)/PlatformPkgConfig.dsc
> +
> +[Components.X64]
> + $(RP_PKG)/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
> +
> +!include $(RP_PKG)/Include/Dsc/BuildOptions.dsc
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffs
> ets.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffs
> ets.inf
> new file mode 100644
> index 0000000000..8945f372e3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOff
> +++ sets.inf
> @@ -0,0 +1,26 @@
> +## @file
> +# Generate AML offset table EPRPPlatform10nm.offset.h via edk2 build #
> +# @copyright # Copyright (C) 2022 Intel Corporation.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent ##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = AmlOffsets
> + FILE_GUID = d7641589-753a-44c5-91c2-bd09686205c6
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> +
> +WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm
> .asl
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + WhitleySiliconPkg/SiliconPkg.dec
> +
> +[BuildOptions]
> + # add -vr and -so to generate offset.h
> + *_*_*_ASL_FLAGS = -oi -vr -so
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
> b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
> index a0c31e4558..5f625f5f92 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py
> @@ -23,6 +23,7 @@ def pre_build_ex(config, functions):
> :returns: nothing
> """
> print("pre_build_ex")
> +
> config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
> 'Build',
> config["PLATFORM_BOARD_PACKAGE"], @@ -53,6
> +54,68 @@ def pre_build_ex(config, functions):
>
> if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
> raise ValueError("FSP API Mode is currently unsupported on Ice Lake
> Xeon Scalable")
> +
> + # Build the ACPI AML offset table *.offset.h
> + print("Info: re-generating PlatformOffset header files")
> +
> + execute_script = functions.get("execute_script")
> +
> + command = ["build", "-D", "MAX_SOCKET=" + config["MAX_SOCKET"]]
> +
> + if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
> + ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ")
> + ext_build_flags = [x.strip() for x in ext_build_flags]
> + ext_build_flags = [x for x in ext_build_flags if x != ""]
> + command.extend(ext_build_flags)
> +
> + aml_offsets_split =
> os.path.split(os.path.normpath(config["AML_OFFSETS_PATH"]))
> + command.append("-p")
> + command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) +
> '.dsc')
> + command.append("-m")
> + command.append(os.path.join(aml_offsets_split[0],
> aml_offsets_split[1], aml_offsets_split[1] + '.inf'))
> + command.append("-y")
> + command.append(os.path.join(config["WORKSPACE"],
> "PreBuildReport.txt"))
> + command.append("--log=" + os.path.join(config["WORKSPACE"],
> + "PreBuild.log"))
> +
> + _, _, _, code = execute_script(command, config)
> + if code != 0:
> + print(" ".join(command))
> + print("Error re-generating PlatformOffset header files")
> + sys.exit(1)
> +
> + # Build AmlGenOffset command to consume the *.offset.h and produce
> AmlOffsetTable.c for StaticSkuDataDxe use.
> +
> + # Get destination path and filename from config
> + relative_file_path =
> os.path.normpath(config["STRIPPED_AML_OFFSETS_FILE_PATH"]) # get
> path relative to Platform/Intel
> + out_file_path = os.path.join(config["WORKSPACE_PLATFORM"],
> relative_file_path) # full path to output file
> + out_file_dir = os.path.dirname(out_file_path) #
> remove filename
> +
> + out_file_root_ext = os.path.splitext(os.path.basename(out_file_path))
> # root and extension of output file
> +
> + # Get relative path for the generated offset.h file
> + relative_dsdt_file_path =
> os.path.normpath(config["DSDT_TABLE_FILE_PATH"]) # path relative to
> Platform/Intel
> + dsdt_file_root_ext =
> os.path.splitext(os.path.basename(relative_dsdt_file_path)) # root and
> extension of generated offset.h file
> +
> + # Generate output directory if it doesn't exist
> + if not os.path.exists(out_file_dir):
> + os.mkdir(out_file_dir)
> +
> + command = ["python",
> + os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset",
> "AmlGenOffset.py"),
> + "-d", "--aml_filter", config["AML_FILTER"],
> + "-o", out_file_path,
> + os.path.join(config["BUILD_X64"], aml_offsets_split[0],
> + aml_offsets_split[1], aml_offsets_split[1], "OUTPUT",
> + os.path.dirname(relative_dsdt_file_path), dsdt_file_root_ext[0] +
> + ".offset.h")]
> +
> + # execute the command
> + _, _, _, code = execute_script(command, config)
> + if code != 0:
> + print(" ".join(command))
> + print("Error re-generating PlatformOffset header files")
> + sys.exit(1)
> +
> + print("GenOffset done")
> +
> +
> return None
>
> def _merge_files(files, ofile):
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
> b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
> index 1676c08813..4cc9496153 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg
> @@ -34,3 +34,18 @@ FSP_BINARY_BUILD = FALSE FSP_TEST_RELEASE =
> FALSE SECURE_BOOT_ENABLE = FALSE BIOS_INFO_GUID = 4A4CA1C6-871C-
> 45BB-8801-6910A7AA5807
> +
> +#
> +# AML offset table generation configuration options # All paths should
> +use / and be relative to edk2-platforms/Platform/Intel #
> +# AML_FILTER - AML filter is used to strip out unused AML offset
> data
> +# AML_OFFSETS_PATH - Path to INF file that builds AML offsets C
> source file
> +# The directory name, DSC file name, INF file name, and BASE_NAME must
> match identically
> +# DSDT_TABLE_FILE_PATH - Path to DSDT ASL file for the board
> +# STRIPPED_AML_OFFSETS_FILE_PATH - Target AML offset data file
> +consumed by UBA driver # AML_FILTER = \"PSYS\" .\.DRVT\"
> +.\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 .\.CCT[0-9A-Z]\"
> +.\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .\.FXBS\"
> +.\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL }; AML_OFFSETS_PATH =
> +WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets
> +DSDT_TABLE_FILE_PATH =
> +WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm
> .asl
> +STRIPPED_AML_OFFSETS_FILE_PATH =
> +WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options Oram, Isaac W
@ 2022-02-09 3:21 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:21 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 6/8]
> WhitleyOpenBoardPkg/Build: Enable includable build options
>
> Separate the [BuildOptions] sections of the DSC to facilitate multiple DSC
> builds for prebuilding.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
> Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc | 151
> ++++++++++++++++++++
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 147 +---------
> ---------
> 2 files changed, 152 insertions(+), 146 deletions(-)
>
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
> new file mode 100644
> index 0000000000..d806521abf
> --- /dev/null
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
> @@ -0,0 +1,151 @@
> +## @file
> +# Includable build options
> +#
> +# @copyright
> +# Copyright (C) 2008 Intel Corporation.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent ##
> +
> +[BuildOptions.Common.EDKII]
> +# Append build options for EDK and EDKII drivers (= is Append, == is
> +Replace) !if $(CRB_FLAG_ENABLE) == TRUE
> + DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG !else
> + DEFINE CRB_EDKII_BUILD_OPTIONS =
> +!endif
> +
> +!if $(DEBUG_FLAGS_ENABLE) == TRUE
> + DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D
> +PLATFORM_VARIABLE_ATTRIBUTES=0x3 !else
> + DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D
> +PLATFORM_VARIABLE_ATTRIBUTES=0x3 !endif
> +
> +!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
> + DEFINE SPARING_SCRATCHPAD_OPTION = -D
> SPARING_SCRATCHPAD_SUPPORT
> +!else
> + DEFINE SPARING_SCRATCHPAD_OPTIONS =
> +!endif
> +
> +!if $(SCRATCHPAD_DEBUG) == TRUE
> + DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG !else
> + DEFINE SCRATCHPAD_DEBUG_OPTION =
> +!endif
> +
> +!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
> + DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1 !else
> + DEFINE PCH_BUILD_OPTION =
> +!endif
> +
> +!if $(SERVER_BIOS_ENABLE) == TRUE
> + DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1 !else
> + DEFINE SERVER_BUILD_OPTION =
> +!endif
> +
> +DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
> +
> +DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
> +
> +DEFINE IE_PATH = -D IE_PATH="Ie/v1"
> +
> +DEFINE NVDIMM_OPTIONS =
> +
> +!if $(CPUTARGET) == "ICX"
> + DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
> !elseif
> +$(CPUTARGET) == "CPX"
> + DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -
> D
> +A0_HOST -D B0_HOST !endif
> +
> +DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D
> MAX_SOCKET=$(MAX_SOCKET) -D
> +MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
> +
> +DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
> +
> +!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
> + DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
> !else
> + DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
> !endif
> +
> +DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D
> MAX_DRAM_CLUSTERS=1
> +
> +DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
> +
> +DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
> +
> +#
> +# MAX_KTI_PORTS needs to be updated based on the silicon type # !if
> +$(CPUTARGET) == "CPX"
> + DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6 !else
> + DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3 !endif
> +
> +DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D
> MAX_LOGIC_IIO_STACK=8
> +
> +DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH)
> +$(SERVER_BUILD_OPTION)
> +
> +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(CRB_EDKII_BUILD_OPTIONS)
> +$(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS)
> +$(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS)
> +$(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS)
> +$(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS)
> +$(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION)
> +$(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT
> +$(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D
> +DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS)
> $(FSP_BUILD_OPTIONS)
> +
> +DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
> +
> +!if $(LINUX_GCC_BUILD) == TRUE
> + DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD !else
> + DEFINE EDK2_LINUX_BUILD_OPTIONS =
> +!endif
> +
> +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> +$(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS)
> +$(IE_OPTIONS)
> +
> +DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
> +
> +DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D
> ESPI_ENABLE
> +
> +DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> +$(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS)
> +$(ASPEED_ENABLE_BUILD_OPTIONS)
> +
> + MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> /wd4819
> + GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> + *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +#
> +# Enable source level debugging for RELEASE build # !if $(TARGET) ==
> +"RELEASE"
> + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
> + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
> + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
> +
> + MSFT:*_*_*_ASM_FLAGS =
> $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
> + MSFT:*_*_*_CC_FLAGS =
> $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
> + MSFT:*_*_*_DLINK_FLAGS =
> $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
> + GCC:*_*_*_ASM_FLAGS =
> $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
> + GCC:*_*_*_CC_FLAGS =
> $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
> + GCC:*_*_*_DLINK_FLAGS =
> $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
> +!endif
> +
> +#
> +# Override the VFR compile flags to speed the build time #
> +
> +*_*_*_VFR_FLAGS == -n
> +
> +#
> +# add to the build options for DXE/SMM drivers to remove the log message:
> +# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
> +#
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER,
> BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +
> +[BuildOptions]
> + GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers
> +-Wno-unused-variable -Wno-unused-but-set-variable
> +-Wno-incompatible-pointer-types -mabi=ms
> + GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
> + GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
> + MSFT:*_*_*_CC_FLAGS = /FAsc
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> index 9c2b8a1048..e78a104004 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> @@ -867,149 +867,4 @@
> # module style (EDK or EDKII) specified in [Components] section.
> #
>
> ##########################################################
> #########################################
> -[BuildOptions.Common.EDKII]
> -# Append build options for EDK and EDKII drivers (= is Append, == is
> Replace) -!if $(CRB_FLAG_ENABLE) == TRUE
> - DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG -!else
> - DEFINE CRB_EDKII_BUILD_OPTIONS =
> -!endif
> -
> -!if $(DEBUG_FLAGS_ENABLE) == TRUE
> - DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D
> PLATFORM_VARIABLE_ATTRIBUTES=0x3 -!else
> - DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D
> PLATFORM_VARIABLE_ATTRIBUTES=0x3 -!endif
> -
> -!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
> - DEFINE SPARING_SCRATCHPAD_OPTION = -D
> SPARING_SCRATCHPAD_SUPPORT -!else
> - DEFINE SPARING_SCRATCHPAD_OPTIONS =
> -!endif
> -
> -!if $(SCRATCHPAD_DEBUG) == TRUE
> - DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG -!else
> - DEFINE SCRATCHPAD_DEBUG_OPTION =
> -!endif
> -
> -!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
> - DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1 -!else
> - DEFINE PCH_BUILD_OPTION =
> -!endif
> -
> -!if $(SERVER_BIOS_ENABLE) == TRUE
> - DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1 -!else
> - DEFINE SERVER_BUILD_OPTION =
> -!endif
> -
> -DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
> -
> -DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
> -
> -DEFINE IE_PATH = -D IE_PATH="Ie/v1"
> -
> -DEFINE NVDIMM_OPTIONS =
> -
> -!if $(CPUTARGET) == "ICX"
> - DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST -
> !elseif $(CPUTARGET) == "CPX"
> - DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D
> A0_HOST -D B0_HOST -!endif
> -
> -DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D
> MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D
> MAX_THREAD=$(MAX_THREAD)
> -
> -DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
> -
> -!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
> - DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2 -
> !else
> - DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3 -
> !endif
> -
> -DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D
> MAX_DRAM_CLUSTERS=1
> -
> -DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
> -
> -DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
> -
> -#
> -# MAX_KTI_PORTS needs to be updated based on the silicon type -# -!if
> $(CPUTARGET) == "CPX"
> - DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6 -!else
> - DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3 -!endif
> -
> -DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D
> MAX_LOGIC_IIO_STACK=8
> -
> -DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH)
> $(SERVER_BUILD_OPTION)
> -
> -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS)
> $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS)
> $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS)
> $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS)
> $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS)
> $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION)
> $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT
> $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D
> DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS)
> $(FSP_BUILD_OPTIONS)
> -
> -DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
> -
> -!if $(LINUX_GCC_BUILD) == TRUE
> - DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD -!else
> - DEFINE EDK2_LINUX_BUILD_OPTIONS =
> -!endif
> -
> -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS)
> $(IE_OPTIONS)
> -
> -DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
> -
> -DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D
> ESPI_ENABLE
> -
> -DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS)
> $(ASPEED_ENABLE_BUILD_OPTIONS)
> -
> - MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> /wd4819
> - GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> - *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> - *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> - *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> - *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> - *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> -
> -
> -#
> -# Enable source level debugging for RELEASE build -# -!if $(TARGET) ==
> "RELEASE"
> - DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
> - DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
> - DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
> -
> - MSFT:*_*_*_ASM_FLAGS =
> $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
> - MSFT:*_*_*_CC_FLAGS =
> $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
> - MSFT:*_*_*_DLINK_FLAGS =
> $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
> - GCC:*_*_*_ASM_FLAGS =
> $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
> - GCC:*_*_*_CC_FLAGS =
> $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
> - GCC:*_*_*_DLINK_FLAGS =
> $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
> -!endif
> -
> -#
> -# Override ASL Compiler parameters in tools_def.template.
> -#
> - *_*_*_ASL_FLAGS == -vr -we -oi
> -#
> -# Override the VFR compile flags to speed the build time -#
> -
> -*_*_*_VFR_FLAGS == -n
> -
> -#
> -# add to the build options for DXE/SMM drivers to remove the log message:
> -# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
> -#
> -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER,
> BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> - MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> -
> -[BuildOptions]
> - GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -
> Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-
> pointer-types -mabi=ms
> - GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
> - GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
> - MSFT:*_*_*_CC_FLAGS = /FAsc
> +!include $(RP_PKG)/Include/Dsc/BuildOptions.dsc
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Oram, Isaac W
@ 2022-02-09 3:21 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2022-02-09 3:21 UTC (permalink / raw)
To: Oram, Isaac W, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> -----Original Message-----
> From: Oram, Isaac W <isaac.w.oram@intel.com>
> Sent: Monday, February 7, 2022 11:03 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>
> Subject: [edk2-devel][edk2-platforms][PATCH V1 5/8]
> WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table
>
> DSDT for WilsonCityRvp
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
> ---
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables
> 10nm.inf | 48 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AML
> UPD.asl | 20 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosP
> arameterRegion.asi | 346 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Com
> monPlatform10nm.asi | 205 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cpu
> MemHp.asi | 730 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT
> .asl | 61 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRP
> Platform10nm.asl | 19 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga
> Bus00.asi | 158 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga
> Bus01.asi | 158 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga
> Bus02.asi | 157 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpga
> Bus03.asi | 157 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.
> asi | 137 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci
> eEdpcGpe.asi | 16 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci
> eEdpcNotify10nm.asi | 183 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci
> eEdpcOst.asi | 16 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPci
> eHotPlugGpeHandler10nm.asl | 1322 +++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRo
> otBridge.asi | 328 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRo
> otBridgeIcx.asi | 270 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Moth
> er.asi | 164 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nvdi
> mmGpe.asi | 25 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.as
> i | 66 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC00
> 10nm.asi | 427 ++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC06
> 10nmEjd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC12
> 10nmEjd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC18
> 10nmEjd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchA
> pic.asi | 18 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieH
> p.asi | 669 +++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieH
> pDev.asi | 53 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieN
> onHpDev.asi | 45 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf
> orm.asl | 91 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf
> ormGpe10nm.asi | 191 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platf
> ormPciTree10nm_EPRP.asi | 5388 ++++++++++++++++++++
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1E
> jd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2E
> jd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3E
> jd.asi | 10 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.a
> si | 219 +
>
> Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Unco
> re.asi | 163 +
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> | 1 +
> Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> | 1 +
> 39 files changed, 11912 insertions(+)
>
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl
> es10nm.inf
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl
> es10nm.inf
> new file mode 100644
> index 0000000000..5480040545
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTabl
> es10nm.inf
> @@ -0,0 +1,48 @@
> +## @file
> +#
> +# @copyright
> +# Copyright 2009 - 2022 Intel Corporation. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PlatformAcpiTable
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Fadt/Fadt62.aslc
> + Facs/Facs62.aslc
> + Dsdt/EPRPPlatform10nm.asl
> + Mcfg/Mcfg.aslc
> + Hpet/Hpet.aslc
> + NFIT/Nfit.aslc
> + PCAT/Pcat.aslc
> +
> + SPCR/Spcr.aslc
> + Msct/Msct.aslc
> + Wddt/Wddt1.0.aslc
> + Bdat/Bdat.aslc
> +
> + Migt/Migt.aslc
> + DBG2/DBG2.aslc
> + Spmi/Spmi.aslc
> + Pmtt/Pmtt10nm.aslc
> + Hmat/Hmat.aslc
> +
> + Wsmt/Wsmt.aslc
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + WhitleySiliconPkg/CpRcPkg.dec
> + WhitleySiliconPkg/SiliconPkg.dec
> + WhitleyOpenBoardPkg/PlatformPkg.dec
> +
> +[FixedPcd]
> + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
> + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount
> + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount
> + gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AM
> LUPD.asl
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/A
> MLUPD.asl
> new file mode 100644
> index 0000000000..3b46dd84df
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/A
> MLUPD.asl
> @@ -0,0 +1,20 @@
> +/** @file
> + ACPI DSDT table
> +
> + @copyright
> + Copyright 2011 - 2014 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +/////////////////////////////////////////////////////////////////////////////
> //////
> +//Values are set like this to have ASL compiler reserve enough space for
> objects
> +/////////////////////////////////////////////////////////////////////////////
> //////
> +//
> +// Available Sleep states
> +//
> +Name(SS1,0)
> +Name(SS2,0)
> +Name(SS3,1)
> +Name(SS4,1)
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio
> sParameterRegion.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio
> sParameterRegion.asi
> new file mode 100644
> index 0000000000..4e49adc10c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Bio
> sParameterRegion.asi
> @@ -0,0 +1,346 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // BIOS parameters region left in memory for ASL by POST code, defined as
> BIOS_ACPI_PARAM in GlobalNvsArea.h.
> + //
> + OperationRegion (PSYS, SystemMemory, 0x30584946, 0x800) // (FIX0 -
> Patched by ACPI Platform Driver during POST)
> + Field (PSYS, ByteAcc, NoLock, Preserve) {
> + // IOAPIC Start
> + PLAT , 32, // Platform ID
> +
> + Offset (0x04), //
> + APCE , 1, // PCH IOAPIC Enable
> + AP00 , 1, // PC00 IOAPIC Enable S0
> + AP01 , 1, // PC01 IOAPIC Enable
> + AP02 , 1, // PC02 IOAPIC Enable
> + AP03 , 1, // PC03 IOAPIC Enable
> + AP04 , 1, // PC04 IOAPIC Enable
> + AP05 , 1, // PC05 IOAPIC Enable
> + AP06 , 1, // PC06 IOAPIC Enable S1
> + AP07 , 1, // PC07 IOAPIC Enable
> + AP08 , 1, // PC08 IOAPIC Enable
> + AP09 , 1, // PC09 IOAPIC Enable
> + AP10 , 1, // PC10 IOAPIC Enable
> + AP11 , 1, // PC11 IOAPIC Enable
> + AP12 , 1, // PC12 IOAPIC Enable S2
> + AP13 , 1, // PC13 IOAPIC Enable
> + AP14 , 1, // PC14 IOAPIC Enable
> + AP15 , 1, // PC15 IOAPIC Enable
> + AP16 , 1, // PC16 IOAPIC Enable
> + AP17 , 1, // PC17 IOAPIC Enable
> + AP18 , 1, // PC18 IOAPIC Enable S3
> + AP19 , 1, // PC19 IOAPIC Enable
> + AP20 , 1, // PC20 IOAPIC Enable
> + AP21 , 1, // PC21 IOAPIC Enable
> + AP22 , 1, // PC22 IOAPIC Enable
> + AP23 , 1, // PC23 IOAPIC Enable
> + AP24 , 1, // PC24 IOAPIC Enable S4
> + AP25 , 1, // PC25 IOAPIC Enable
> + AP26 , 1, // PC26 IOAPIC Enable
> + AP27 , 1, // PC27 IOAPIC Enable
> + AP28 , 1, // PC28 IOAPIC Enable
> + AP29 , 1, // PC29 IOAPIC Enable
> + AP30 , 1, // PC30 IOAPIC Enable S5
> + AP31 , 1, // PC31 IOAPIC Enable
> + AP32 , 1, // PC32 IOAPIC Enable
> + AP33 , 1, // PC33 IOAPIC Enable
> + AP34 , 1, // PC34 IOAPIC Enable
> + AP35 , 1, // PC35 IOAPIC Enable
> + AP36 , 1, // PC36 IOAPIC Enable S6
> + AP37 , 1, // PC37 IOAPIC Enable
> + AP38 , 1, // PC38 IOAPIC Enable
> + AP39 , 1, // PC39 IOAPIC Enable
> + AP40 , 1, // PC40 IOAPIC Enable
> + AP41 , 1, // PC41 IOAPIC Enable
> + AP42 , 1, // PC42 IOAPIC Enable S7
> + AP43 , 1, // PC43 IOAPIC Enable
> + AP44 , 1, // PC44 IOAPIC Enable
> + AP45 , 1, // PC45 IOAPIC Enable
> + AP46 , 1, // PC46 IOAPIC Enable
> + AP47 , 1, // PC47 IOAPIC Enable
> + RESA , 15,
> +
> + Offset (0x0C),
> + SKOV , 1, // Override ApicId socket field
> + P119 , 1, // PCH IOAPIC 24_119 enabled
> + CPX4 , 1, // 1 = CPX4, 0 = CPX6
> + RES0 , 5, // Unused
> + // IOAPIC End
> +
> + // Power Managment Start
> + Offset (0x0D),
> + TPME , 1, // TPM Enable
> + CSEN , 1, // C State Enable
> + C3EN , 1, // OS C3 Report Enbale
> + C6EN , 1, // C6 Enable
> + C7EN , 1, // C7 Enable
> + MWOS , 1, // MWAIT support Enable
> + PSEN , 1, // P State Enable
> + EMCA , 1, // EMCA Enable
> + Offset (0x0E),
> + HWAL , 2, // PSD HW_ALL Enable
> + KPRS , 1, // KB present Flag
> + MPRS , 1, // Mouse present Flag
> + TSEN , 1, // T State Enable Flag
> + FGTS , 1, // Fine grained T state Flag
> + OSCX , 1, // OS C States
> + RESX , 1, // Unused
> + // Power Management End
> +
> + // RAS Start
> + Offset (0x0F),
> + CPHP , 8, // Bit field for determining CPU hotplug event is happening,
> Update every time CPU Hotpug event is registered as valid
> + // Bit0 CPU0 O*L Request
> + // Bit1 CPU1 O*L Request
> + // Bit2 CPU2 O*L Request
> + // Bit3 CPU3 O*L Request
> + // Bit4 CPU4 O*L Request
> + // Bit5 CPU5 O*L Request
> + // Bit6 CPU6 O*L Request
> + // Bit7 CPU7 O*L Request
> + IIOP , 8, // Bit field for determining IIO hotplug event is happening,
> Update every time IIO Hotpug event is registered as valid
> + // Bit0 IIO1 O*L Request
> + // Bit1 IIO2 O*L Request
> + // Bit2 IIO3 O*L Request
> + // Bit3-7 Reserved
> + SPB0 , 16, // Stack Present Bitmask in socket0, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB1 , 16, // Stack Present Bitmask in socket1, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB2 , 16, // Stack Present Bitmask in socket2, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB3 , 16, // Stack Present Bitmask in socket3, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB4 , 16, // Stack Present Bitmask in socket4, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB5 , 16, // Stack Present Bitmask in socket5, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB6 , 16, // Stack Present Bitmask in socket6, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + SPB7 , 16, // Stack Present Bitmask in socket7, what stacks are present
> for STA method (Patched by ACPI Platform Driver during POST)
> + PRBM , 32, // Processor Bit mask, what sockets are present for STA
> method, Update every time hotplug event happen and at boot time
> (Patched by ACPI Platform Driver during POST)
> + CTHC , 8, // CPU Core Thread Count
> + P0ID , 32, // Processor 0 APIC ID base
> + P1ID , 32, // Processor 1 APIC ID base
> + P2ID , 32, // Processor 2 APIC ID base
> + P3ID , 32, // Processor 3 APIC ID base
> + P4ID , 32, // Processor 4 APIC ID base
> + P5ID , 32, // Processor 5 APIC ID base
> + P6ID , 32, // Processor 6 APIC ID base
> + P7ID , 32, // Processor 7 APIC ID base
> + P0BM , 64, // Processor 0 Bit mask, what cores (0-63) are present for
> STA method
> + P1BM , 64, // Processor 1 Bit mask, what cores (0-63) are present for
> STA method
> + P2BM , 64, // Processor 2 Bit mask, what cores (0-63) are present for
> STA method
> + P3BM , 64, // Processor 3 Bit mask, what cores (0-63) are present for
> STA method
> + P4BM , 64, // Processor 4 Bit mask, what cores (0-63) are present for
> STA method
> + P5BM , 64, // Processor 5 Bit mask, what cores (0-63) are present for
> STA method
> + P6BM , 64, // Processor 6 Bit mask, what cores (0-63) are present for
> STA method
> + P7BM , 64, // Processor 7 Bit mask, what cores (0-63) are present for
> STA method
> + P0BH , 64, // Processor 0 Bit mask, what cores (64-127) are present for
> STA method
> + P1BH , 64, // Processor 1 Bit mask, what cores (64-127) are present for
> STA method
> + P2BH , 64, // Processor 2 Bit mask, what cores (64-127) are present for
> STA method
> + P3BH , 64, // Processor 3 Bit mask, what cores (64-127) are present for
> STA method
> + P4BH , 64, // Processor 4 Bit mask, what cores (64-127) are present for
> STA method
> + P5BH , 64, // Processor 5 Bit mask, what cores (64-127) are present for
> STA method
> + P6BH , 64, // Processor 6 Bit mask, what cores (64-127) are present for
> STA method
> + P7BH , 64, // Processor 7 Bit mask, what cores (64-127) are present for
> STA method
> + CFMM , 32, // MMCFG Base
> + TSSZ , 32, // TSEG Size.
> + SMI0 , 32, // Parameter0 used for faked SMI request
> + SMI1 , 32, // Parameter1 used for faked SMI request
> + SMI2 , 32, // Parameter2 used for faked SMI request
> + SMI3 , 32, // Parameter3 used for faked SMI request
> + SCI0 , 32, // Parameter0 used for faked SCI request
> + SCI1 , 32, // Parameter1 used for faked SCI request
> + SCI2 , 32, // Parameter2 used for faked SCI request
> + SCI3 , 32, // Parameter3 used for faked SCI request
> + MADD , 64, // Migration ActionRegion GAS address. (Migration support
> written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15
> are invalid.)
> + CUU0 , 128, // CPU0 UUID
> + CUU1 , 128, // CPU1 UUID
> + CUU2 , 128, // CPU2 UUID
> + CUU3 , 128, // CPU3 UUID
> + CUU4 , 128, // CPU4 UUID
> + CUU5 , 128, // CPU5 UUID
> + CUU6 , 128, // CPU6 UUID
> + CUU7 , 128, // CPU7 UUID
> + CPSP , 8, // CPU spare bitmap. 1 == IsSpare.
> + ME00 , 128, // MEM0 UUID
> + ME01 , 128, // MEM1 UUID
> + ME10 , 128, // MEM2 UUID
> + ME11 , 128, // MEM3 UUID
> + ME20 , 128, // MEM4 UUID
> + ME21 , 128, // MEM5 UUID
> + ME30 , 128, // MEM6 UUID
> + ME31 , 128, // MEM7 UUID
> + ME40 , 128, // MEM8 UUID
> + ME41 , 128, // MEM9 UUID
> + ME50 , 128, // MEM10 UUID
> + ME51 , 128, // MEM11 UUID
> + ME60 , 128, // MEM12 UUID
> + ME61 , 128, // MEM13 UUID
> + ME70 , 128, // MEM14 UUID
> + ME71 , 128, // MEM15 UUID
> + LDIR , 64, // L1 Directory Address
> + PRID , 32, // Processor ID
> + AHPE , 8, // ACPI PCIe hot plug enable.
> + WHEN , 8,
> + WSCI , 8,
> + SERR , 8, // Propogate SERR
> + PERR , 8, // Propogate PERR
> + // RAS End
> +
> + // VTD Start
> + DHRD , 192, // DHRD
> + ATSR , 192, // ATSR
> + RHSA , 192, // RHSA
> + // VTD End
> +
> + // SR-IOV WA Start
> + WSIC , 8,
> + WSIS , 16,
> + WSIB , 8,
> + WSID , 8,
> + WSIF , 8,
> + WSTS , 8,
> + WHEA , 8,
> + // SR-IOV WA End
> +
> + // BIOS Guard Start
> + BGMA , 64, // BIOS Guard Memory Address
> + BGMS , 8, // BIOS Guard Memory Size
> + BGIO , 16, // BIOS Guard IO Trap Address
> + CNBS , 8, // CPU SKU number bit shift
> + // BIOS Guard End
> +
> + // USB3 Start
> + XHMD , 8, // copy of setup item PchUsb30Mode
> + SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1)
> + SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2)
> + // USB3 End
> +
> + // HWPM Start
> + HWEN , 2, // HWPM State Enable option from setup
> + RES2 , 1, // Reserved bit
> + HWPI , 1, // HWP Interrupt
> + RES1 , 4, // Reserved bits
> + // HWPM End
> +
> + // SGX Start
> + EPCS , 8, // EPC Status
> + ELN0 , 64, // EPC0 Length
> + ELN1 , 64, // EPC1 Length
> + ELN2 , 64, // EPC2 Length
> + ELN3 , 64, // EPC3 Length
> + ELN4 , 64, // EPC4 Length
> + ELN5 , 64, // EPC5 Length
> + ELN6 , 64, // EPC6 Length
> + ELN7 , 64, // EPC7 Length
> + EBA0 , 64, // EPC0 Base Address
> + EBA1 , 64, // EPC1 Base Address
> + EBA2 , 64, // EPC2 Base Address
> + EBA3 , 64, // EPC3 Base Address
> + EBA4 , 64, // EPC4 Base Address
> + EBA5 , 64, // EPC5 Base Address
> + EBA6 , 64, // EPC6 Base Address
> + EBA7 , 64, // EPC7 Base Address
> + // SGX End
> +
> + // PCIe Multi-Seg Start
> + // Stack bus base numbers for up to 14 stacks in up to 8 socket. Name is
> 'BB<skt><stk>', where <skt> and <stk> are hex.
> + BB00, 8, BB01, 8, BB02, 8, BB03, 8, BB04, 8, BB05, 8, BB06, 8, BB07, 8, BB08,
> 8, BB09, 8, BB0A, 8, BB0B, 8, BB0C, 8, BB0D, 8,
> + BB10, 8, BB11, 8, BB12, 8, BB13, 8, BB14, 8, BB15, 8, BB16, 8, BB17, 8, BB18,
> 8, BB19, 8, BB1A, 8, BB1B, 8, BB1C, 8, BB1D, 8,
> + BB20, 8, BB21, 8, BB22, 8, BB23, 8, BB24, 8, BB25, 8, BB26, 8, BB27, 8, BB28,
> 8, BB29, 8, BB2A, 8, BB2B, 8, BB2C, 8, BB2D, 8,
> + BB30, 8, BB31, 8, BB32, 8, BB33, 8, BB34, 8, BB35, 8, BB36, 8, BB37, 8, BB38,
> 8, BB39, 8, BB3A, 8, BB3B, 8, BB3C, 8, BB3D, 8,
> + BB40, 8, BB41, 8, BB42, 8, BB43, 8, BB44, 8, BB45, 8, BB46, 8, BB47, 8, BB48,
> 8, BB49, 8, BB4A, 8, BB4B, 8, BB4C, 8, BB4D, 8,
> + BB50, 8, BB51, 8, BB52, 8, BB53, 8, BB54, 8, BB55, 8, BB56, 8, BB57, 8, BB58,
> 8, BB59, 8, BB5A, 8, BB5B, 8, BB5C, 8, BB5D, 8,
> + BB60, 8, BB61, 8, BB62, 8, BB63, 8, BB64, 8, BB65, 8, BB66, 8, BB67, 8, BB68,
> 8, BB69, 8, BB6A, 8, BB6B, 8, BB6C, 8, BB6D, 8,
> + BB70, 8, BB71, 8, BB72, 8, BB73, 8, BB74, 8, BB75, 8, BB76, 8, BB77, 8, BB78,
> 8, BB79, 8, BB7A, 8, BB7B, 8, BB7C, 8, BB7D, 8,
> +
> + SGEN , 8, // PCIe_MultiSeg_Support enable/disable
> + SG00 , 8, // PCI segment ID for socket 0
> + SG01 , 8, // PCI segment ID for socket 1
> + SG02 , 8, // PCI segment ID for socket 2
> + SG03 , 8, // PCI segment ID for socket 3
> + SG04 , 8, // PCI segment ID for socket 4
> + SG05 , 8, // PCI segment ID for socket 5
> + SG06 , 8, // PCI segment ID for socket 6
> + SG07 , 8, // PCI segment ID for socket 7
> + // PCIe Multi-Seg End
> +
> + // Sub-NUMA Cluster support
> + CLOD , 8, // 0 - SNC disabled, 2 - SNC enabled with 2 clusters, 4 - SNC
> enabled with 4 clusters
> +
> + // XTU Start
> + XTUB , 32,
> + XTUS , 32,
> + XMBA , 32,
> + DDRF , 8,
> + RT3S , 8,
> + RTP0 , 8,
> + RTP3 , 8,
> + // XTU End
> +
> + // FPGA Root Port Bus
> + FBB0 , 8, // FPGA Bus Base for Socket 0
> + FBB1 , 8, // FPGA Bus Base for Socket 1
> + FBB2 , 8, // FPGA Bus Base for Socket 2
> + FBB3 , 8, // FPGA Bus Base for Socket 3
> + FBB4 , 8, // FPGA Bus Base for Socket 4
> + FBB5 , 8, // FPGA Bus Base for Socket 5
> + FBB6 , 8, // FPGA Bus Base for Socket 6
> + FBB7 , 8, // FPGA Bus Base for Socket 7
> +
> + FBL0 , 8, // FPGA Bus limit for Socket 0
> + FBL1 , 8, // FPGA Bus limit for Socket 1
> + FBL2 , 8, // FPGA Bus limit for Socket 2
> + FBL3 , 8, // FPGA Bus limit for Socket 3
> + FBL4 , 8, // FPGA Bus limit for Socket 4
> + FBL5 , 8, // FPGA Bus limit for Socket 5
> + FBL6 , 8, // FPGA Bus limit for Socket 6
> + FBL7 , 8, // FPGA Bus limit for Socket 7
> +
> + // FPGA present bit
> + P0FB , 8, // FPGA present in Socket 0
> + P1FB , 8, // FPGA present in Socket 1
> + P2FB , 8, // FPGA present in Socket 2
> + P3FB , 8, // FPGA present in Socket 3
> + P4FB , 8, // FPGA present in Socket 4
> + P5FB , 8, // FPGA present in Socket 5
> + P6FB , 8, // FPGA present in Socket 6
> + P7FB , 8, // FPGA present in Socket 7
> +
> + // FPGA Resource Allocation
> + FMB0 , 32,
> + FMB1 , 32,
> + FMB2 , 32,
> + FMB3 , 32,
> + FMB4 , 32,
> + FMB5 , 32,
> + FMB6 , 32,
> + FMB7 , 32,
> +
> + FML0 , 32,
> + FML1 , 32,
> + FML2 , 32,
> + FML3 , 32,
> + FML4 , 32,
> + FML5 , 32,
> + FML6 , 32,
> + FML7 , 32,
> +
> + // FPGA KTI present bitmap
> + FKPB , 32,
> + // FPGA Bus for KTI
> + FKB0 , 8, // FPGA Bus Base for Socket 0 KTI Link
> + FKB1 , 8, // FPGA Bus Base for Socket 1 KTI Link
> + FKB2 , 8, // FPGA Bus Base for Socket 2 KTI Link
> + FKB3 , 8, // FPGA Bus Base for Socket 3 KTI Link
> + FKB4 , 8, // FPGA Bus Base for Socket 4 KTI Link
> + FKB5 , 8, // FPGA Bus Base for Socket 5 KTI Link
> + FKB6 , 8, // FPGA Bus Base for Socket 6 KTI Link
> + FKB7 , 8, // FPGA Bus Base for Socket 7 KTI Link
> +
> + PMBA , 16, // ACPI IO Base Address
> + DBGM , 8, // Debug Mode Indicator
> + IRPC , 8, // IIO PCIe root port PCIe Capability offset
> + ATSC , 8, // Flag to indicate if TSC is linked to ART
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co
> mmonPlatform10nm.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co
> mmonPlatform10nm.asi
> new file mode 100644
> index 0000000000..28a997b102
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Co
> mmonPlatform10nm.asi
> @@ -0,0 +1,205 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "MaxSocket.h"
> +
> + //
> + // External declarations
> + // HECI-1/HECI-2 are in 10nmServerPlatformPkg\Me\Sps\Acpi\SpsNm.asl
> + //
> + External(\_SB.PC00.HEC2.HPTS, MethodObj)
> + External(\_SB.PC00.HEC2.HWAK, MethodObj)
> +
> + External(\_SB.OSPC, MethodObj)
> + //
> + // System Sleep States
> + //
> + Name (\_S0,Package (){0,0,0,0})
> + Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in
> Setup
> + Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in
> Setup
> + Name (\_S5,Package (){7,0,0,0})
> +
> + //
> + // Native OS hot plug support, 0->ACPI, 1->OS
> + //
> + Name (\OSHF, 0)
> +
> + Name (\HWPS, 0) // CPC capability from platform _OSC
> +
> + //
> + // OS flag
> + //
> + #include "Os.asi"
> +
> + //
> + // for determing PIC mode
> + //
> + Name (\PICM,Zero)
> + Method (\_PIC, 1, NotSerialized) {
> + Store(Arg0,\PICM)
> + }
> +
> + OperationRegion (DBG0, SystemIO, 0x80, 2)
> + Field (DBG0, ByteAcc,NoLock,Preserve) {
> + IO80, 8,
> + IO81, 8
> + }
> +
> + //
> + // Access CMOS range
> + //
> + OperationRegion (ACMS, SystemIO, 0x72, 2)
> + Field ( ACMS, ByteAcc, NoLock, Preserve) {
> + INDX, 8,
> + DATA, 8
> + }
> +
> +
> + //
> + // BIOS parameter BIOS_ACPI_PARAM
> + //
> + #include "BiosParameterRegion.asi"
> +
> + //
> + // SWGPE_CTRL
> + //
> + OperationRegion (GPCT, SystemIO, Add (PMBA, 0x42), 1)
> + Field (GPCT, ByteAcc, NoLock, Preserve) {
> + , 1,
> + SGPC , 1,
> + }
> +
> + //
> + // GPE0 Enable
> + //
> + OperationRegion (GPE0, SystemIO, Add (PMBA, 0x9C), 4)
> + Field (GPE0, ByteAcc,NoLock,Preserve) {
> + ,1,
> + GPEH,1,
> + ,7,
> + PCIE,1,
> + ,1,
> + PMEE,1,
> + ,1,
> + PMB0,1,
> + ,18,
> + }
> +
> + //
> + // GPE0 Status
> + //
> + OperationRegion (GPES, SystemIO, Add (PMBA, 0x8C), 4)
> + Field (GPES, ByteAcc,NoLock,Preserve) {
> + ,1,
> + GPSH,1,
> + SGPS,1,
> + ,6,
> + PEES,1,
> + ,1,
> + PMES,1,
> + ,1,
> + PMEB,1,
> + ,18,
> + }
> +
> + //
> + // System sleep down
> + //
> + Method (_PTS, 1, NotSerialized)
> + {
> + Store (0x72, IO80) // Sync with EfiPostCode.h
> +
> + //
> + // Clear wake event status.
> + //
> + Store(1,PMES)
> + Store(1,PMEB)
> +
> + //
> + // Enable SCI and wake event sources.
> + //
> + Store(1,GPEH)
> + Store(1,PCIE)
> + Store(1,PMEE)
> + Store(1,PMB0)
> +
> + //
> + // If HECI-2 exist call its prepare-to-sleep handler.
> + // The handler checks whether HECI-2 is enabled.
> + //
> + If (CondRefOf(\_SB.PC00.HEC2.HPTS))
> + {
> + \_SB.PC00.HEC2.HPTS()
> + }
> +
> + /// WA for S3 on XHCI
> + \_SB.PC00.XHCI.XHCS()
> + }
> +
> +
> + //
> + // System Wake up
> + //
> + Method (_WAK, 1, Serialized)
> + {
> + Store (0x73, IO80) // Sync with EfiPostCode.h
> +
> + //
> + // If HECI-2 exist call its wake-up handler.
> + // The handler checks whether HECI-2 is enabled.
> + //
> + If (CondRefOf(\_SB.PC00.HEC2.HWAK))
> + {
> + \_SB.PC00.HEC2.HWAK()
> + }
> +
> + //
> + // If waking from S3
> + //
> + If (LEqual(Arg0, 3)) {
> + }
> +
> + Return(Package(){0, 0})
> + }
> +
> + Scope(\_SB) {
> +
> + // Information on CPU and Memory for hotplug SKUs
> + #include "CpuMemHp.asi"
> +
> + OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
> + Field (IOB2, ByteAcc, NoLock, Preserve) {
> + SMIC, 8, // SW-SMI ctrl port
> + SMIS, 8, // SW-SMI status port
> + }
> +
> + Method(_OSC , 4) {
> + Store(Arg3,Local0)
> + CreateDWordField(Local0,4,CPBF)
> + If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) {
> + //Save Platform OSC HWPM capabilities
> + If(LEqual(And(CPBF, 0x00000040), 0x00000040)) {
> + Store(1,HWPS)
> + }
> + }
> + If (CondRefOf (\_SB.OSPC)) {
> + Return (\_SB.OSPC(Arg0, Arg1, Arg2, Arg3))
> + }
> + Return (Local0)
> + }
> + //
> + // SGX
> + //
> + #include "Sgx.asi"
> + //
> + // Common Hot Plug for PCxx devices
> + //
> + #include "IioRootBridgeIcx.asi"
> + } // end _SB scope
> +
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp
> uMemHp.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp
> uMemHp.asi
> new file mode 100644
> index 0000000000..a0824a30c0
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Cp
> uMemHp.asi
> @@ -0,0 +1,730 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "MaxSocket.h"
> +
> +#define HECI_CMD_CPUHOTPLUG 1
> +#define HECI_CMD_CPUHOTREMOVE 2
> +
> +#define SIZE_LAPIC_STRUC 8
> +#define LAPIC_TYPE 0
> +
> +#define SIZE_X2LAPIC_STRUC 16
> +#define X2LAPIC_TYPE 9
> +
> +#define MAK_STR(x) #x
> +
> +//
> +// This macro creates method that calculates
> +// number of active threads for its socket
> +//
> +#define CPU_THREADS_NUM(socket) \
> + Method(THNU, 0) { \
> + Store(0, Local0) \
> + Store(P##socket##BM, Local1) \
> + While (Local1) { \
> + Add(Local0, And(Local1, 1), Local0) \
> + ShiftRight(Local1, 1, Local1) \
> + } \
> + return (Or(ShiftLeft(socket, 8), Local0)) \
> + }
> +
> +//
> +//set DevName ProcId field and IO to C##thread
> +//
> +#define CPU_THREAD_DEV(socket, thread) \
> + Device(C##thread) { \
> + Name(_HID, "ACPI0007") \
> + Method (_UID) { \
> + Return (\_SB.CUID(0x0##socket, 0x##thread)) \
> + } \
> + Method(_PXM) { \
> + if (LEqual (CLOD, 0)) { \
> + Return(0x0##socket) \
> + } else { \
> + Store(DerefOf(Index(\_SB.APT##socket, 0x##thread)), Local0) \
> + Store(CNBS, Local1) \
> + Subtract(Local1, 1, Local1) \
> + ShiftRight(Local0, Local1, Local0) \
> + And(Local0, 1, Local0) \
> + Store(0x##socket, Local1) \
> + Multiply(Local1, 2, Local1) \
> + if(LEqual(Local0, 1)) { \
> + Add(Local1, 1, Local1) \
> + } \
> + Return(Local1) \
> + } \
> + } \
> + Method(_STA) { \
> + if(LEqual(\_SB.CSTA(0x0##socket, 0x##thread), 0x00)) { \
> + Return(0x00) \
> + } else { \
> + If (LGreaterEqual (\_SB.OSYS, 12)) { \
> + Return(0x0F) \
> + } Else { \
> + Return(0x0B) \
> + } \
> + } \
> + } \
> + Method(_MAT) { \
> + if(SKOV) { \
> + Return(\_SB.X2AP(0x0##socket, 0x##thread)) \
> + } else { \
> + Return(\_SB.LAPC(0x0##socket, 0x##thread)) \
> + } \
> + } \
> + }
> +
> +#define CPU_SOCKET_DEV(socket) \
> + Device(\_SB.SCK##socket) { \
> + Name (_HID, "ACPI0004") \
> + Name (_UID, MAK_STR(CPUSCK##socket)) \
> + Name (LSTA, 0xff) \
> + Method(_STA) { \
> + Store(MAK_STR(CPUSCK##socket), CUU##socket) \
> + Store(\_SB.PSTA(0x0##socket), Local0) \
> + And(Local0, 0x03, Local1) \
> + If (LAnd(LNotEqual(LSTA, 0xff), LNotEqual(Local1, LSTA))) { \
> + If (LEqual(Local1, 0x03)) { \
> + /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTPLUG, socket, THNU)
> TODO: Obsolete with _PUR?*/\
> + } Else { \
> + /*\_SB.PC00.HEC2.HPNF(HECI_CMD_CPUHOTREMOVE, socket, THNU)
> TODO: Obsolete with _PUR?*/\
> + } \
> + } \
> + Store(Local1, LSTA) \
> + return(Local0) \
> + } \
> + \
> + CPU_THREADS_NUM(socket) \
> + CPU_THREAD_DEV (socket, 000) \
> + CPU_THREAD_DEV (socket, 001) \
> + CPU_THREAD_DEV (socket, 002) \
> + CPU_THREAD_DEV (socket, 003) \
> + CPU_THREAD_DEV (socket, 004) \
> + CPU_THREAD_DEV (socket, 005) \
> + CPU_THREAD_DEV (socket, 006) \
> + CPU_THREAD_DEV (socket, 007) \
> + CPU_THREAD_DEV (socket, 008) \
> + CPU_THREAD_DEV (socket, 009) \
> + CPU_THREAD_DEV (socket, 00A) \
> + CPU_THREAD_DEV (socket, 00B) \
> + CPU_THREAD_DEV (socket, 00C) \
> + CPU_THREAD_DEV (socket, 00D) \
> + CPU_THREAD_DEV (socket, 00E) \
> + CPU_THREAD_DEV (socket, 00F) \
> + CPU_THREAD_DEV (socket, 010) \
> + CPU_THREAD_DEV (socket, 011) \
> + CPU_THREAD_DEV (socket, 012) \
> + CPU_THREAD_DEV (socket, 013) \
> + CPU_THREAD_DEV (socket, 014) \
> + CPU_THREAD_DEV (socket, 015) \
> + CPU_THREAD_DEV (socket, 016) \
> + CPU_THREAD_DEV (socket, 017) \
> + CPU_THREAD_DEV (socket, 018) \
> + CPU_THREAD_DEV (socket, 019) \
> + CPU_THREAD_DEV (socket, 01A) \
> + CPU_THREAD_DEV (socket, 01B) \
> + CPU_THREAD_DEV (socket, 01C) \
> + CPU_THREAD_DEV (socket, 01D) \
> + CPU_THREAD_DEV (socket, 01E) \
> + CPU_THREAD_DEV (socket, 01F) \
> + CPU_THREAD_DEV (socket, 020) \
> + CPU_THREAD_DEV (socket, 021) \
> + CPU_THREAD_DEV (socket, 022) \
> + CPU_THREAD_DEV (socket, 023) \
> + CPU_THREAD_DEV (socket, 024) \
> + CPU_THREAD_DEV (socket, 025) \
> + CPU_THREAD_DEV (socket, 026) \
> + CPU_THREAD_DEV (socket, 027) \
> + CPU_THREAD_DEV (socket, 028) \
> + CPU_THREAD_DEV (socket, 029) \
> + CPU_THREAD_DEV (socket, 02A) \
> + CPU_THREAD_DEV (socket, 02B) \
> + CPU_THREAD_DEV (socket, 02C) \
> + CPU_THREAD_DEV (socket, 02D) \
> + CPU_THREAD_DEV (socket, 02E) \
> + CPU_THREAD_DEV (socket, 02F) \
> + CPU_THREAD_DEV (socket, 030) \
> + CPU_THREAD_DEV (socket, 031) \
> + CPU_THREAD_DEV (socket, 032) \
> + CPU_THREAD_DEV (socket, 033) \
> + CPU_THREAD_DEV (socket, 034) \
> + CPU_THREAD_DEV (socket, 035) \
> + CPU_THREAD_DEV (socket, 036) \
> + CPU_THREAD_DEV (socket, 037) \
> + CPU_THREAD_DEV (socket, 038) \
> + CPU_THREAD_DEV (socket, 039) \
> + CPU_THREAD_DEV (socket, 03A) \
> + CPU_THREAD_DEV (socket, 03B) \
> + CPU_THREAD_DEV (socket, 03C) \
> + CPU_THREAD_DEV (socket, 03D) \
> + CPU_THREAD_DEV (socket, 03E) \
> + CPU_THREAD_DEV (socket, 03F) \
> + CPU_THREAD_DEV (socket, 040) \
> + CPU_THREAD_DEV (socket, 041) \
> + CPU_THREAD_DEV (socket, 042) \
> + CPU_THREAD_DEV (socket, 043) \
> + CPU_THREAD_DEV (socket, 044) \
> + CPU_THREAD_DEV (socket, 045) \
> + CPU_THREAD_DEV (socket, 046) \
> + CPU_THREAD_DEV (socket, 047) \
> + CPU_THREAD_DEV (socket, 048) \
> + CPU_THREAD_DEV (socket, 049) \
> + CPU_THREAD_DEV (socket, 04A) \
> + CPU_THREAD_DEV (socket, 04B) \
> + CPU_THREAD_DEV (socket, 04C) \
> + CPU_THREAD_DEV (socket, 04D) \
> + CPU_THREAD_DEV (socket, 04E) \
> + CPU_THREAD_DEV (socket, 04F) \
> + CPU_THREAD_DEV (socket, 050) \
> + CPU_THREAD_DEV (socket, 051) \
> + CPU_THREAD_DEV (socket, 052) \
> + CPU_THREAD_DEV (socket, 053) \
> + CPU_THREAD_DEV (socket, 054) \
> + CPU_THREAD_DEV (socket, 055) \
> + CPU_THREAD_DEV (socket, 056) \
> + CPU_THREAD_DEV (socket, 057) \
> + CPU_THREAD_DEV (socket, 058) \
> + CPU_THREAD_DEV (socket, 059) \
> + CPU_THREAD_DEV (socket, 05A) \
> + CPU_THREAD_DEV (socket, 05B) \
> + CPU_THREAD_DEV (socket, 05C) \
> + CPU_THREAD_DEV (socket, 05D) \
> + CPU_THREAD_DEV (socket, 05E) \
> + CPU_THREAD_DEV (socket, 05F) \
> + CPU_THREAD_DEV (socket, 060) \
> + CPU_THREAD_DEV (socket, 061) \
> + CPU_THREAD_DEV (socket, 062) \
> + CPU_THREAD_DEV (socket, 063) \
> + CPU_THREAD_DEV (socket, 064) \
> + CPU_THREAD_DEV (socket, 065) \
> + CPU_THREAD_DEV (socket, 066) \
> + CPU_THREAD_DEV (socket, 067) \
> + CPU_THREAD_DEV (socket, 068) \
> + CPU_THREAD_DEV (socket, 069) \
> + CPU_THREAD_DEV (socket, 06A) \
> + CPU_THREAD_DEV (socket, 06B) \
> + CPU_THREAD_DEV (socket, 06C) \
> + CPU_THREAD_DEV (socket, 06D) \
> + CPU_THREAD_DEV (socket, 06E) \
> + CPU_THREAD_DEV (socket, 06F) \
> + CPU_THREAD_DEV (socket, 070) \
> + CPU_THREAD_DEV (socket, 071) \
> + CPU_THREAD_DEV (socket, 072) \
> + CPU_THREAD_DEV (socket, 073) \
> + CPU_THREAD_DEV (socket, 074) \
> + CPU_THREAD_DEV (socket, 075) \
> + CPU_THREAD_DEV (socket, 076) \
> + CPU_THREAD_DEV (socket, 077) \
> + CPU_THREAD_DEV (socket, 078) \
> + CPU_THREAD_DEV (socket, 079) \
> + CPU_THREAD_DEV (socket, 07A) \
> + CPU_THREAD_DEV (socket, 07B) \
> + CPU_THREAD_DEV (socket, 07C) \
> + CPU_THREAD_DEV (socket, 07D) \
> + CPU_THREAD_DEV (socket, 07E) \
> + CPU_THREAD_DEV (socket, 07F) \
> + }
> +
> + Scope(\_SB) {
> +
> + //----------------------------------------------------------------
> + // Method PSTA()
> + // Return package state
> + //
> + // Inputs: Arg0 = socket number for which to return the _STA code.
> + //----------------------------------------------------------------
> + Method(PSTA, 1){ // Socket Status
> + ShiftRight(PRBM, Arg0, Local6)
> + And(Local6, 0x1, Local6)
> + if(LEqual(Local6, 0x0)) {
> + Return(0x00)
> + } else {
> + Return(0x0F)
> + }
> + } // End Method PSTA
> +
> + //----------------------------------------------------------------
> + // APIC ID Map
> + // Extened APIC ID buffer to support MAX 64 core
> + //----------------------------------------------------------------
> + Name (APT0, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT1, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT2, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT3, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT4, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT5, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT6, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + Name (APT7, Buffer (128) {
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> +
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
> + })
> +
> + //----------------------------------------------------------------
> + // Method TPID()
> + // Convert the socket and thread index to the actual APIC ID
> + //
> + // Inputs: Arg0 = socket index
> + // Arg1 = thread index
> + //----------------------------------------------------------------
> + Method (TPID, 2, NotSerialized) {
> + Store (0x00, Local0)
> + If (LEqual (Arg0, 0x00))
> + {
> + Store (P0ID, Local0)
> + Add (Local0, DerefOf(Index(APT0, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x01))
> + {
> + Store (P1ID, Local0)
> + Add (Local0, DerefOf(Index(APT1, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x02))
> + {
> + Store (P2ID, Local0)
> + Add (Local0, DerefOf(Index(APT2, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x03))
> + {
> + Store (P3ID, Local0)
> + Add (Local0, DerefOf(Index(APT3, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x04))
> + {
> + Store (P4ID, Local0)
> + Add (Local0, DerefOf(Index(APT4, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x05))
> + {
> + Store (P5ID, Local0)
> + Add (Local0, DerefOf(Index(APT5, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x06))
> + {
> + Store (P6ID, Local0)
> + Add (Local0, DerefOf(Index(APT6, Arg1)), Local0)
> + }
> +
> + If (LEqual (Arg0, 0x07))
> + {
> + Store (P7ID, Local0)
> + Add (Local0, DerefOf(Index(APT7, Arg1)), Local0)
> + }
> +
> + Return (Local0)
> + }
> +
> + //----------------------------------------------------------------
> + // Method CSTA()
> + // Get current processor state
> + // Inputs: Arg0 = Socket Number where core belongs
> + // Arg1 = Thread number for which to return the _STA code
> + // (Bit0 - Core Id, BIT1- Thread Id)
> + //----------------------------------------------------------------
> + Method(CSTA, 2){ // Core Status
> + Store(0, Local0)
> + Store(0, Local2) //for Core#
> +
> + //Get ApicId per thread Index from APT#
> + if (LEqual(Arg0, 0x0)) {
> + if(LEqual(P0BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT0, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P0BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x1)) {
> + if(LEqual(P1BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT1, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P1BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x2)) {
> + if(LEqual(P2BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT2, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P2BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x3)) {
> + if(LEqual(P3BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT3, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P3BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x4)) {
> + if(LEqual(P4BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT4, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P4BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x5)) {
> + if(LEqual(P5BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT5, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P5BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x6)) {
> + if(LEqual(P6BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT6, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P6BM, Local2, Local0)
> + }
> + if (LEqual(Arg0, 0x7)) {
> + if(LEqual(P7BM, 0x0)) {
> + Return(0x00)
> + }
> +
> + Add (Local2, DerefOf(Index(APT7, Arg1)), Local2)
> + if (LEqual(Local2, 0xFF)) {
> + Return(0x00)
> + }
> + //Processor Bit mask is changed for core# only
> + ShiftRight(Local2, 1, Local2)
> + ShiftRight(P7BM, Local2, Local0)
> + }
> +
> + And(Local0, 0x1, Local0)
> + if(LEqual(Local0, 0x0)) {
> + Return(0x00)
> + } else {
> + Return(0x01)
> + }
> + } // End Method CSTA
> +
> + //----------------------------------------------------------------
> + // Method CUID()
> + // Return MADT ACPI Processor UID, AcpiProcessorId and _UID
> + // Should match with AcpiProcessorId in C code
> + //
> + // Inputs: Arg0 = Socket ID
> + // Inputs: Arg1 = Thread ID
> + // Return _UID
> + //----------------------------------------------------------------+
> + Method (CUID, 2) {
> + Store(ShiftLeft(1, CNBS), Local1)
> + Multiply(Arg0, local1, local1)
> + Add(local1, Arg1, local1)
> +
> + Return (Local1)
> + }
> +
> + //----------------------------------------------------------------
> + // Method LAPC()
> + // Return the _MAT APIC data structure
> + //
> + // Inputs: Arg0 = Socket ID
> + // Inputs: Arg1 = Thread ID
> + // APID = TPID(Arg0, Arg1)
> + // PUID = Socket ID << CNBS + Thread ID
> + //----------------------------------------------------------------+
> + Method(LAPC, 2,Serialized) {
> +
> + Name(APIC, Buffer(SIZE_LAPIC_STRUC) {} ) // initialize a buffer with
> CRST size
> +
> + CreateByteField (APIC, 0x00, TYPE) // Type
> + CreateByteField (APIC, 0x01, LLEN) // Length
> + CreateByteField (APIC, 0x02, PUID) // ACPI Processor ID
> + CreateByteField (APIC, 0x03, APID) // APIC ID
> + CreateDwordField(APIC, 0x04, FLAG) // Flags
> +
> + Store(LAPIC_TYPE, TYPE)
> + Store(SIZE_LAPIC_STRUC, LLEN)
> +
> + // Update APIC ID
> + Store (\_SB.TPID(Arg0, Arg1), APID)
> +
> + // Update Flag
> + if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) {
> + Store(0x00, FLAG)
> + Store(0xFF, PUID)
> + Store(0xFF, APID)
> + } else {
> + Store(ShiftLeft(1, CNBS), Local1)
> + Multiply(Arg0, local1, local1)
> + Add(local1, Arg1, local1)
> + Store(local1, PUID)
> +
> + //set Enable flag
> + Store(0x01, FLAG)
> + }
> +
> + // calculate PROCID based on APICID using same algorithm in
> AcpiPlatformHook.c
> +
> + Return(APIC)
> + }
> +
> + Method(X2AP, 2,Serialized) {
> +
> + Name(APIC, Buffer(SIZE_X2LAPIC_STRUC) {} ) // initialize a buffer with
> CRST siz
> +
> + CreateByteField (APIC, 0x00, TYPE) // Type
> + CreateByteField (APIC, 0x01, LLEN) // Length
> + CreateWordField (APIC, 0x02, RSVD) // Reserved 2 bytes
> + CreateDwordField(APIC, 0x04, APID) // APIC ID
> + CreateDwordField(APIC, 0x08, FLAG) // Flags
> + CreateDwordField(APIC, 0x0C, PUID) // ACPI Processor UID
> +
> + Store(X2LAPIC_TYPE, TYPE)
> + Store(SIZE_X2LAPIC_STRUC, LLEN)
> + Store(0, RSVD)
> +
> + // Update APIC ID
> + Store (\_SB.TPID(Arg0, Arg1), APID)
> +
> + // Update Flag
> + if(LEqual(\_SB.CSTA(Arg0, Arg1), 0x00)) {
> + Store(0x00, FLAG)
> + Store(0xFFFFFFFF, APID)
> + } else {
> + //ProcId = socket# * MAX_THREADS_PER_SOCKET + thread#
> + Store(ShiftLeft(1, CNBS), Local1)
> + Multiply(Arg0, local1, local1)
> + Add(local1, Arg1, local1)
> + Store(local1, PUID)
> +
> + //set Enable flag
> + Store(0x01, FLAG)
> +
> + }
> +
> + Return(APIC)
> +
> + }
> +
> + CPU_SOCKET_DEV(0)
> +
> +#if MAX_SOCKET > 1
> + CPU_SOCKET_DEV(1)
> +#endif
> +
> +#if MAX_SOCKET > 2
> + CPU_SOCKET_DEV(2)
> +#endif
> +
> +#if MAX_SOCKET > 3
> + CPU_SOCKET_DEV(3)
> +#endif
> +
> +#if MAX_SOCKET > 4
> + CPU_SOCKET_DEV(4)
> +#endif
> +
> +#if MAX_SOCKET > 5
> + CPU_SOCKET_DEV(5)
> +#endif
> +
> +#if MAX_SOCKET > 6
> + CPU_SOCKET_DEV(6)
> +#endif
> +
> +#if MAX_SOCKET > 7
> + CPU_SOCKET_DEV(7)
> +#endif
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS
> DT.asl
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS
> DT.asl
> new file mode 100644
> index 0000000000..b3f96f8ddb
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DS
> DT.asl
> @@ -0,0 +1,61 @@
> +/** @file
> + ACPI DSDT table
> +
> + @copyright
> + Copyright 2011 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// @NOTE: This should be read from hardware to reflect
> +// real PCI exress base. Currently we do not have such
> +// capability so hardcode is used instead.
> +//
> +#define PCI_EXPRESS_BASE 0x80000000
> +
> +Scope(\_SB.PC00) {
> +
> + //
> + // PCI-specific method's GUID
> + //
> + Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
> + //
> + // PCI's _DSM - an attempt at modular _DSM implementation
> + // When writing your own _DSM function that needs to include PCI-
> specific methods, do this:
> + //
> + // Method(_YOUR_DSM,4){
> + // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
> + // ...continue your _DSM by checking different GUIDs...
> + // else { return(0) }
> + // }
> + //
> + Method(PCID, 4, Serialized) {
> + If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
> + If(LGreaterEqual(Arg1,3)) { // revision at least 3
> + If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function
> 0: list of supported functions
> + If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding
> Power-On Reset Delay Duplication on Sx Resume
> + If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones})
> } // function 9: Specifying Device Readiness Durations
> + }
> + }
> + return (Buffer(1){0})
> + }
> +
> + Method(PCIC,1,Serialized) {
> + If(LEqual(ECR1,1)) {
> + If(LEqual(Arg0, PCIG)) {
> + return (1)
> + }
> + }
> + return (0)
> + }
> +
> + //
> + // Get the PCI express base address.
> + // Currently hardcoded.
> + //
> + Method (GPCB) {
> + Return (PCI_EXPRESS_BASE)
> + }
> +}
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP
> RPPlatform10nm.asl
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP
> RPPlatform10nm.asl
> new file mode 100644
> index 0000000000..386fbdac59
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EP
> RPPlatform10nm.asl
> @@ -0,0 +1,19 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +DefinitionBlock ("EPRPPlatform10nm.asl","DSDT",2,"INTEL","EPRP10NM",3)
> +{
> + #include "CommonPlatform10nm.asi"
> + #include "PlatformPciTree10nm_EPRP.asi"
> + #include "AMLUPD.asl"
> + #include "DSDT.asl"
> + #include "Pch.asl" //This is in another package (PchPkg)
> + #include "Platform.asl"
> + #include "PlatformGpe10nm.asi"
> + #include "IioPcieEdpcNotify10nm.asi"
> +} // end of DSDT
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg
> aBus00.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus00.asi
> new file mode 100644
> index 0000000000..235e60650c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus00.asi
> @@ -0,0 +1,158 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> +
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * ASPM
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not
> met?
> + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> + //And (CTRL, 0x1C, CTRL)
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + Store (0xEE, IO80)
> + Return(Arg3)
> + }
> + }
> +
> + Method(_STA){
> + // Check if Virtual FPGA is present
> + if(LEqual(P0FB, 0x1)) {
> + // Virtual FPGA present and logically online
> + Return(0x0F)
> + }
> + // Virtual FPGA logically offline
> + Return(0x00)
> +
> + } // End Method STA
> +
> + Name (RBUF, ResourceTemplate () {
> + WORDBusNumber( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity
> + 0x0000, // Min
> + 0x0000, // Max
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1
> + ,
> + ,
> + FBUS
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX7 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FPGM // DescriptorName populated so iASL outputs offset for
> it in a .h file
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIXZ -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIXZ // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + })
> +
> + Method(_CRS, 0x0, NotSerialized) {
> + ///
> + /// Patch 32b memory
> + ///
> + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
> + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
> + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
> + Store(FMB0, FMN1)
> + Store(FML0, FMX1)
> + Subtract (FMX1, FMN1, FLN1)
> + Add (FLN1, 1, FLN1)
> +
> + ///
> + /// Patch _BBN
> + ///
> + If(LGreater(FBL0, FBB0)) {
> + CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
> + CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
> + CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
> + Store(FBB0, BMIN)
> + Store(FBL0, BMAX)
> + Subtract (BMAX, BMIN, BLEN)
> + Add (BLEN, 1, BLEN)
> + }
> + Return (RBUF)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg
> aBus01.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus01.asi
> new file mode 100644
> index 0000000000..cecf469c9d
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus01.asi
> @@ -0,0 +1,158 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> +
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * ASPM
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not
> met?
> + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> + //And (CTRL, 0x1C, CTRL)
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + Store (0xEE, IO80)
> + Return(Arg3)
> + }
> + }
> +
> + Method(_STA){
> + // Check if Virtual FPGA is present
> + if(LEqual(P1FB, 0x1)) {
> + // Virtual FPGA present and logically online
> + Return(0x0F)
> + }
> + // Virtual FPGA logically offline
> + Return(0x00)
> +
> + } // End Method STA
> +
> + Name (RBUF, ResourceTemplate () {
> + WORDBusNumber( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity
> + 0x0000, // Min
> + 0x0000, // Max
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1
> + ,
> + ,
> + FBUS
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX7 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FPGM // DescriptorName populated so iASL outputs offset for
> it in a .h file
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIXZ -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIXZ // DescriptorName populated so iASL outputs offset for it
> in a .h file
> +
> + )
> + })
> +
> + Method(_CRS, 0x0, NotSerialized) {
> + ///
> + /// Patch 32b memory
> + ///
> + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
> + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
> + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
> + Store(FMB1, FMN1)
> + Store(FML1, FMX1)
> + Subtract (FMX1, FMN1, FLN1)
> + Add (FLN1, 1, FLN1)
> +
> + ///
> + /// Patch _BBN
> + ///
> + If(LGreater(FBL1, FBB1)) {
> + CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
> + CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
> + CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
> + Store(FBB1, BMIN)
> + Store(FBL1, BMAX)
> + Subtract (BMAX, BMIN, BLEN)
> + Add (BLEN, 1, BLEN)
> + }
> + Return (RBUF)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg
> aBus02.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus02.asi
> new file mode 100644
> index 0000000000..e4731a63c1
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus02.asi
> @@ -0,0 +1,157 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> +
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * ASPM
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not
> met?
> + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> + //And (CTRL, 0x1C, CTRL)
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + Store (0xEE, IO80)
> + Return(Arg3)
> + }
> + }
> +
> + Method(_STA){
> + // Check if Virtual FPGA is present
> + if(LEqual(P2FB, 0x1)) {
> + // Virtual FPGA present and logically online
> + Return(0x0F)
> + }
> + // Virtual FPGA logically offline
> + Return(0x00)
> +
> + } // End Method STA
> +
> + Name (RBUF, ResourceTemplate () {
> + WORDBusNumber( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity
> + 0x0000, // Min
> + 0x0000, // Max
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1
> + ,
> + ,
> + FBUS
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX7 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FPGM // DescriptorName populated so iASL outputs offset for
> it in a .h file
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIXZ -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIXZ // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> + })
> +
> + Method(_CRS, 0x0, NotSerialized) {
> + ///
> + /// Patch 32b memory
> + ///
> + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
> + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
> + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
> + Store(FMB2, FMN1)
> + Store(FML2, FMX1)
> + Subtract (FMX1, FMN1, FLN1)
> + Add (FLN1, 1, FLN1)
> +
> + ///
> + /// Patch _BBN
> + ///
> + If(LGreater(FBL2, FBB2)) {
> + CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
> + CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
> + CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
> + Store(FBB2, BMIN)
> + Store(FBL2, BMAX)
> + Subtract (BMAX, BMIN, BLEN)
> + Add (BLEN, 1, BLEN)
> + }
> + Return (RBUF)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fpg
> aBus03.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus03.asi
> new file mode 100644
> index 0000000000..51be7989ac
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Fp
> gaBus03.asi
> @@ -0,0 +1,157 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2016 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> +
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * ASPM
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not
> met?
> + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> + //And (CTRL, 0x1C, CTRL)
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + Store (0xEE, IO80)
> + Return(Arg3)
> + }
> + }
> +
> + Method(_STA){
> + // Check if Virtual FPGA is present
> + if(LEqual(P3FB, 0x1)) {
> + // Virtual FPGA present and logically online
> + Return(0x0F)
> + }
> + // Virtual FPGA logically offline
> + Return(0x00)
> +
> + } // End Method STA
> +
> + Name (RBUF, ResourceTemplate () {
> + WORDBusNumber( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity
> + 0x0000, // Min
> + 0x0000, // Max
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1
> + ,
> + ,
> + FBUS
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX7 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX7 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX7 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FPGM // DescriptorName populated so iASL outputs offset for
> it in a .h file
> + )
> +
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIXZ - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIXZ - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIXZ - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIXZ -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIXZ // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> + })
> +
> + Method(_CRS, 0x0, NotSerialized) {
> + ///
> + /// Patch 32b memory
> + ///
> + CreateDwordField(^RBUF, ^FPGM._MIN, FMN1)
> + CreateDwordField(^RBUF, ^FPGM._MAX, FMX1)
> + CreateDwordField(^RBUF, ^FPGM._LEN, FLN1)
> + Store(FMB3, FMN1)
> + Store(FML3, FMX1)
> + Subtract (FMX1, FMN1, FLN1)
> + Add (FLN1, 1, FLN1)
> +
> + ///
> + /// Patch _BBN
> + ///
> + If(LGreater(FBL3, FBB3)) {
> + CreateWordField(^RBUF, ^FBUS._MIN, BMIN)
> + CreateWordField(^RBUF, ^FBUS._MAX, BMAX)
> + CreateWordField(^RBUF, ^FBUS._LEN, BLEN)
> + Store(FBB3, BMIN)
> + Store(FBL3, BMAX)
> + Subtract (BMAX, BMIN, BLEN)
> + Add (BLEN, 1, BLEN)
> + }
> + Return (RBUF)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp
> e.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp
> e.asi
> new file mode 100644
> index 0000000000..d695b13df9
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gp
> e.asi
> @@ -0,0 +1,137 @@
> +/** @file
> + ACPI DSDT table
> +
> +@copyright
> + Copyright 2011 - 2018 Intel Corporation.
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // General Purpose Events. This Scope handles the Run-time and
> + // Wake-time SCIs. The specific method called will be determined by
> + // the _Lxx value, where xx equals the bit location in the General
> + // Purpose Event register(s).
> +
> +
> + //
> + // If the Root Port is enabled, run PCI_EXP_STS handler
> + //
> + If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP01.HPME()
> + Notify(\_SB.PC00.RP01, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP02.HPME()
> + Notify(\_SB.PC00.RP02, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP03.HPME()
> + Notify(\_SB.PC00.RP03, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP04.HPME()
> + Notify(\_SB.PC00.RP04, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP05.HPME()
> + Notify(\_SB.PC00.RP05, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP06.HPME()
> + Notify(\_SB.PC00.RP06, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP07.HPME()
> + Notify(\_SB.PC00.RP07, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP08.HPME()
> + Notify(\_SB.PC00.RP08, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP09.HPME()
> + Notify(\_SB.PC00.RP09, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP10.HPME()
> + Notify(\_SB.PC00.RP10, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP11.HPME()
> + Notify(\_SB.PC00.RP11, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP12.HPME()
> + Notify(\_SB.PC00.RP12, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP13.HPME()
> + Notify(\_SB.PC00.RP13, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP14.HPME()
> + Notify(\_SB.PC00.RP14, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP15.HPME()
> + Notify(\_SB.PC00.RP15, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP16.HPME()
> + Notify(\_SB.PC00.RP16, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP17.HPME()
> + Notify(\_SB.PC00.RP17, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP18.HPME()
> + Notify(\_SB.PC00.RP18, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP19.HPME()
> + Notify(\_SB.PC00.RP19, 0x02)
> + }
> +
> + If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF))
> + {
> + \_SB.PC00.RP20.HPME()
> + Notify(\_SB.PC00.RP20, 0x02)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcGpe.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcGpe.asi
> new file mode 100644
> index 0000000000..7180f6d607
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcGpe.asi
> @@ -0,0 +1,16 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> + External(\_SB.EDGH, MethodObj)
> +
> + //
> + // Handle eDPC SWGPE event
> + //
> + If (CondRefOf (\_SB.EDGH))
> + {
> + \_SB.EDGH ()
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcNotify10nm.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcNotify10nm.asi
> new file mode 100644
> index 0000000000..78759e32f3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcNotify10nm.asi
> @@ -0,0 +1,183 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +External(\_SB.EDTM, MethodObj)
> +External (\_SB.EDNT, FieldUnitObj)
> +External (\_SB.EDVD, FieldUnitObj)
> +
> +#define PCIE_EDPC_NOTIFY(stack, port) \
> + store (\_SB.stack._SEG, Local0) \
> + store (\_SB.stack._BBN, Local1) \
> + store (\_SB.stack.port._ADR, Local2) \
> + And (Local2, 0xffff, Local3) \
> + ShiftRight (Local2, 16, Local4) \
> + If (\_SB.EDTM(Local0, Local1, Local4, Local3)) { \
> + If (\_SB.EDNT) { \
> + /* \
> + we are going to notify this device, set the valid flag to
> EDPC_INFO_NOTIFIED \
> + */ \
> + store (2, \_SB.EDVD) \
> + Notify(\_SB.stack.port, 0xf) /*Error Eject*/ \
> + } else { \
> + /* \
> + we are going to notify this device, set the valid flag to
> EDPC_INFO_NOTIFIED \
> + */ \
> + store (2, \_SB.EDVD) \
> + Notify(\_SB.stack.port, 0) /*Bus Check*/ \
> + } \
> + }
> +
> +Scope (\_SB) {
> + //
> + // eDPC Notify Method
> + //
> + Method (EDNM, 0) {
> + // PC01 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC01, BR1A)
> + PCIE_EDPC_NOTIFY(PC01, BR1B)
> + PCIE_EDPC_NOTIFY(PC01, BR1C)
> + PCIE_EDPC_NOTIFY(PC01, BR1D)
> +
> + // PC02 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC02, BR2A)
> + PCIE_EDPC_NOTIFY(PC02, BR2B)
> + PCIE_EDPC_NOTIFY(PC02, BR2C)
> + PCIE_EDPC_NOTIFY(PC02, BR2D)
> +
> + // PC03 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC03, BR3A)
> + PCIE_EDPC_NOTIFY(PC03, BR3B)
> + PCIE_EDPC_NOTIFY(PC03, BR3C)
> + PCIE_EDPC_NOTIFY(PC03, BR3D)
> +
> + // PC04 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC04, BR4A)
> + PCIE_EDPC_NOTIFY(PC04, BR4B)
> + PCIE_EDPC_NOTIFY(PC04, BR4C)
> + PCIE_EDPC_NOTIFY(PC04, BR4D)
> +
> + // PC05 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC05, BR5A)
> + PCIE_EDPC_NOTIFY(PC05, BR5B)
> + PCIE_EDPC_NOTIFY(PC05, BR5C)
> + PCIE_EDPC_NOTIFY(PC05, BR5D)
> +
> + #if MAX_SOCKET > 1
> + // PC07 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC07, QR1A)
> + PCIE_EDPC_NOTIFY(PC07, QR1B)
> + PCIE_EDPC_NOTIFY(PC07, QR1C)
> + PCIE_EDPC_NOTIFY(PC07, QR1D)
> +
> + // PC08 Port 2A PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC08, QR2A)
> + PCIE_EDPC_NOTIFY(PC08, QR2B)
> + PCIE_EDPC_NOTIFY(PC08, QR2C)
> + PCIE_EDPC_NOTIFY(PC08, QR2D)
> +
> + // PC09 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC09, QR3A)
> + PCIE_EDPC_NOTIFY(PC09, QR3B)
> + PCIE_EDPC_NOTIFY(PC09, QR3C)
> + PCIE_EDPC_NOTIFY(PC09, QR3D)
> +
> + // PC08 Port 2A PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC10, QR4A)
> + PCIE_EDPC_NOTIFY(PC10, QR4B)
> + PCIE_EDPC_NOTIFY(PC10, QR4C)
> + PCIE_EDPC_NOTIFY(PC10, QR4D)
> +
> + // PC09 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC11, QR5A)
> + PCIE_EDPC_NOTIFY(PC11, QR5B)
> + PCIE_EDPC_NOTIFY(PC11, QR5C)
> + PCIE_EDPC_NOTIFY(PC11, QR5D)
> + #endif
> + #if MAX_SOCKET > 2
> + // PC13 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC13, RR1A)
> + PCIE_EDPC_NOTIFY(PC13, RR1B)
> + PCIE_EDPC_NOTIFY(PC13, RR1C)
> + PCIE_EDPC_NOTIFY(PC13, RR1D)
> +
> + // PC14 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC14, RR2A)
> + PCIE_EDPC_NOTIFY(PC14, RR2B)
> + PCIE_EDPC_NOTIFY(PC14, RR2C)
> + PCIE_EDPC_NOTIFY(PC14, RR2D)
> +
> + // PC15 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC15, RR3A)
> + PCIE_EDPC_NOTIFY(PC15, RR3B)
> + PCIE_EDPC_NOTIFY(PC15, RR3C)
> + PCIE_EDPC_NOTIFY(PC15, RR3D)
> +
> + // PC16 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC16, RR4A)
> + PCIE_EDPC_NOTIFY(PC16, RR4B)
> + PCIE_EDPC_NOTIFY(PC16, RR4C)
> + PCIE_EDPC_NOTIFY(PC16, RR4D)
> +
> + // PC17 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC17, RR5A)
> + PCIE_EDPC_NOTIFY(PC17, RR5B)
> + PCIE_EDPC_NOTIFY(PC17, RR5C)
> + PCIE_EDPC_NOTIFY(PC17, RR5D)
> + #endif
> + #if MAX_SOCKET > 3
> + // PC19 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC19, SR1A)
> + PCIE_EDPC_NOTIFY(PC19, SR1B)
> + PCIE_EDPC_NOTIFY(PC19, SR1C)
> + PCIE_EDPC_NOTIFY(PC19, SR1D)
> +
> + // PC20 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC20, SR2A)
> + PCIE_EDPC_NOTIFY(PC20, SR2B)
> + PCIE_EDPC_NOTIFY(PC20, SR2C)
> + PCIE_EDPC_NOTIFY(PC20, SR2D)
> +
> + // PC21 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC21, SR3A)
> + PCIE_EDPC_NOTIFY(PC21, SR3B)
> + PCIE_EDPC_NOTIFY(PC21, SR3C)
> + PCIE_EDPC_NOTIFY(PC21, SR3D)
> +
> + // PC21 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC22, SR4A)
> + PCIE_EDPC_NOTIFY(PC22, SR4B)
> + PCIE_EDPC_NOTIFY(PC22, SR4C)
> + PCIE_EDPC_NOTIFY(PC22, SR4D)
> +
> + // PC22 PCI-Ex eDPC
> + // If this is the eDPC event trigger, notify error eject or bus check
> + PCIE_EDPC_NOTIFY(PC23, SR5A)
> + PCIE_EDPC_NOTIFY(PC23, SR5B)
> + PCIE_EDPC_NOTIFY(PC23, SR5C)
> + PCIE_EDPC_NOTIFY(PC23, SR5D)
> + #endif
> + } //endof the method EDGH
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcOst.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcOst.asi
> new file mode 100644
> index 0000000000..13c76067c3
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieEdpcOst.asi
> @@ -0,0 +1,16 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> + External(\_SB.EDOS, MethodObj)
> +
> + //
> + // Handle eDPC _OST
> + //
> + If (CondRefOf (\_SB.EDOS))
> + {
> + \_SB.EDOS (Arg0, Arg1, Arg2)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieHotPlugGpeHandler10nm.asl
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieHotPlugGpeHandler10nm.asl
> new file mode 100644
> index 0000000000..09ff73e148
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> PcieHotPlugGpeHandler10nm.asl
> @@ -0,0 +1,1322 @@
> +/** @file
> +
> + @copyright
> + Copyright 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // Delay introduced as initial delay after entering ACPI hotplug method
> + //
> + Sleep (200)
> + Store (0x01, IO80)
> + Sleep (10)
> + Store (0,Local1)
> +
> + // PC00 Port 1A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) {
> + Store(\_SB.PC01.BR1A.PMEH(1), Local0)
> + } else {
> + Store (\_SB.PC01.BR1A.HPEH(1), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(1, Local1)
> + Notify(\_SB.PC01.BR1A, Local0)
> + }
> +
> + // PC00 Port 1B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) {
> + Store(\_SB.PC01.BR1B.PMEH(2), Local0)
> + } else {
> + Store (\_SB.PC01.BR1B.HPEH(2), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(2, Local1)
> + Notify(\_SB.PC01.BR1B, Local0)
> + }
> +
> + // PC00 Port 1C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) {
> + Store(\_SB.PC01.BR1C.PMEH(3), Local0)
> + } else {
> + Store (\_SB.PC01.BR1C.HPEH(3), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(3, Local1)
> + Notify(\_SB.PC01.BR1C, Local0)
> + }
> +
> + // PC00 Port 1D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) {
> + Store(\_SB.PC01.BR1D.PMEH(4), Local0)
> + } else {
> + Store (\_SB.PC01.BR1D.HPEH(4), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(4, Local1)
> + Notify(\_SB.PC01.BR1D, Local0)
> + }
> +
> +
> + // PC01 Port 2A PCI-Ex Hot Plug
> + If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) {
> + Store(\_SB.PC02.BR2A.PMEH(5), Local0)
> + } else {
> + Store (\_SB.PC02.BR2A.HPEH(5), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(5, Local1)
> + Notify(\_SB.PC02.BR2A, Local0)
> + }
> +
> + // PC01 Port 2B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) {
> + Store(\_SB.PC02.BR2B.PMEH(6), Local0)
> + } else {
> + Store (\_SB.PC02.BR2B.HPEH(6), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(6, Local1)
> + Notify(\_SB.PC02.BR2B, Local0)
> + }
> +
> + // PC01 Port 2C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) {
> + Store(\_SB.PC02.BR2C.PMEH(7), Local0)
> + } else {
> + Store (\_SB.PC02.BR2C.HPEH(7), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(7, Local1)
> + Notify(\_SB.PC02.BR2C, Local0)
> + }
> +
> + // PC01 Port 2D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) {
> + Store(\_SB.PC02.BR2D.PMEH(8), Local0)
> + } else {
> + Store (\_SB.PC02.BR2D.HPEH(8), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(8, Local1)
> + Notify(\_SB.PC02.BR2D, Local0)
> + }
> +
> + // PC01 Port 3A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) {
> + Store(\_SB.PC03.BR3A.PMEH(9), Local0)
> + } else {
> + Store (\_SB.PC03.BR3A.HPEH(9), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(9, Local1)
> + Notify(\_SB.PC03.BR3A, Local0)
> + }
> +
> + // PC01 Port 3B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC03.BR3B.PMEP,1) ) {
> + Store(\_SB.PC03.BR3B.PMEH(10), Local0)
> + } else {
> + Store (\_SB.PC03.BR3B.HPEH(10), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(10, Local1)
> + Notify(\_SB.PC03.BR3B, Local0)
> + }
> +
> + // PC01 Port 3C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) {
> + Store(\_SB.PC03.BR3C.PMEH(11), Local0)
> + } else {
> + Store (\_SB.PC03.BR3C.HPEH(11), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(11, Local1)
> + Notify(\_SB.PC03.BR3C, Local0)
> + }
> +
> + // PC01 Port 3D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) {
> + Store(\_SB.PC03.BR3D.PMEH(12), Local0)
> + } else {
> + Store (\_SB.PC03.BR3D.HPEH(12), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(12, Local1)
> + Notify(\_SB.PC03.BR3D, Local0)
> + }
> +
> + // PC02 Port 4A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC04.BR4A.PMEP,1) ) {
> + Store(\_SB.PC04.BR4A.PMEH(13), Local0)
> + } else {
> + Store (\_SB.PC04.BR4A.HPEH(13), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(13, Local1)
> + Notify(\_SB.PC04.BR4A, Local0)
> + }
> +
> + // PC02 Port 4B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC04.BR4B.PMEP,1) ) {
> + Store(\_SB.PC04.BR4B.PMEH(14), Local0)
> + } else {
> + Store (\_SB.PC04.BR4B.HPEH(14), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(14, Local1)
> + Notify(\_SB.PC04.BR4B, Local0)
> + }
> +
> + // PC02 Port 4C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC04.BR4C.PMEP,1) ) {
> + Store(\_SB.PC04.BR4C.PMEH(15), Local0)
> + } else {
> + Store (\_SB.PC04.BR4C.HPEH(15), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(15, Local1)
> + Notify(\_SB.PC04.BR4C, Local0)
> + }
> +
> + // PC02 Port 4D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC04.BR4D.PMEP,1) ) {
> + Store(\_SB.PC04.BR4D.PMEH(16), Local0)
> + } else {
> + Store (\_SB.PC04.BR4D.HPEH(16), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(16, Local1)
> + Notify(\_SB.PC04.BR4D, Local0)
> + }
> +
> + // PC02 Port 5A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC05.BR5A.PMEP,1) ) {
> + Store(\_SB.PC05.BR5A.PMEH(17), Local0)
> + } else {
> + Store (\_SB.PC05.BR5A.HPEH(17), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(17, Local1)
> + Notify(\_SB.PC05.BR5A, Local0)
> + }
> +
> + // PC02 Port 5B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC05.BR5B.PMEP,1) ) {
> + Store(\_SB.PC05.BR5B.PMEH(18), Local0)
> + } else {
> + Store (\_SB.PC05.BR5B.HPEH(18), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(18, Local1)
> + Notify(\_SB.PC05.BR5B, Local0)
> + }
> +
> + // PC02 Port 5C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC05.BR5C.PMEP,1) ) {
> + Store(\_SB.PC05.BR5C.PMEH(19), Local0)
> + } else {
> + Store (\_SB.PC05.BR5C.HPEH(19), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(19, Local1)
> + Notify(\_SB.PC05.BR5C, Local0)
> + }
> +
> + // PC02 Port 5D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC05.BR5D.PMEP,1) ) {
> + Store(\_SB.PC05.BR5D.PMEH(20), Local0)
> + } else {
> + Store (\_SB.PC05.BR5D.HPEH(20), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(20, Local1)
> + Notify(\_SB.PC05.BR5D, Local0)
> + }
> +
> +#if MAX_SOCKET > 1
> +
> +
> + // PC06 Port 1A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) {
> + Store(\_SB.PC07.QR1A.PMEH(1), Local0)
> + } else {
> + Store (\_SB.PC07.QR1A.HPEH(1), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(1, Local1)
> + Notify(\_SB.PC07.QR1A, Local0)
> + }
> +
> + // PC06 Port 1B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) {
> + Store(\_SB.PC07.QR1B.PMEH(2), Local0)
> + } else {
> + Store (\_SB.PC07.QR1B.HPEH(2), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(2, Local1)
> + Notify(\_SB.PC07.QR1B, Local0)
> + }
> +
> + // PC06 Port 1C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) {
> + Store(\_SB.PC07.QR1C.PMEH(3), Local0)
> + } else {
> + Store (\_SB.PC07.QR1C.HPEH(3), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(3, Local1)
> + Notify(\_SB.PC07.QR1C, Local0)
> + }
> +
> + // PC06 Port 1D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) {
> + Store(\_SB.PC07.QR1D.PMEH(4), Local0)
> + } else {
> + Store (\_SB.PC07.QR1D.HPEH(4), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(4, Local1)
> + Notify(\_SB.PC07.QR1D, Local0)
> + }
> +
> + // PC04 Port 2A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) {
> + Store(\_SB.PC08.QR2A.PMEH(5), Local0)
> + } else {
> + Store (\_SB.PC08.QR2A.HPEH(5), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(5, Local1)
> + Notify(\_SB.PC08.QR2A, Local0)
> + }
> +
> + // PC04 Port 2B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) {
> + Store(\_SB.PC08.QR2B.PMEH(6), Local0)
> + } else {
> + Store (\_SB.PC08.QR2B.HPEH(6), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(6, Local1)
> + Notify(\_SB.PC08.QR2B, Local0)
> + }
> +
> + // PC04 Port 2C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) {
> + Store(\_SB.PC08.QR2C.PMEH(7), Local0)
> + } else {
> + Store (\_SB.PC08.QR2C.HPEH(7), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(7, Local1)
> + Notify(\_SB.PC08.QR2C, Local0)
> + }
> +
> + // PC04 Port 2D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) {
> + Store(\_SB.PC08.QR2D.PMEH(8), Local0)
> + } else {
> + Store (\_SB.PC08.QR2D.HPEH(8), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(8, Local1)
> + Notify(\_SB.PC08.QR2D, Local0)
> + }
> +
> + // PC04 Port 3A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) {
> + Store(\_SB.PC09.QR3A.PMEH(9), Local0)
> + } else {
> + Store (\_SB.PC09.QR3A.HPEH(9), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(9, Local1)
> + Notify(\_SB.PC09.QR3A, Local0)
> + }
> +
> + // PC04 Port 3B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) {
> + Store(\_SB.PC09.QR3B.PMEH(10), Local0)
> + } else {
> + Store (\_SB.PC09.QR3B.HPEH(10), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(10, Local1)
> + Notify(\_SB.PC09.QR3B, Local0)
> + }
> +
> + // PC04 Port 3C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) {
> + Store(\_SB.PC09.QR3C.PMEH(11), Local0)
> + } else {
> + Store (\_SB.PC09.QR3C.HPEH(11), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(11, Local1)
> + Notify(\_SB.PC09.QR3C, Local0)
> + }
> +
> + // PC04 Port 3D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) {
> + Store(\_SB.PC09.QR3D.PMEH(12), Local0)
> + } else {
> + Store (\_SB.PC09.QR3D.HPEH(12), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(12, Local1)
> + Notify(\_SB.PC09.QR3D, Local0)
> + }
> +
> + // PC10 Port 4A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC10.QR4A.PMEP,1) ) {
> + Store(\_SB.PC10.QR4A.PMEH(13), Local0)
> + } else {
> + Store (\_SB.PC10.QR4A.HPEH(13), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(13, Local1)
> + Notify(\_SB.PC10.QR4A, Local0)
> + }
> +
> + // PC10 Port 4B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC10.QR4B.PMEP,1) ) {
> + Store(\_SB.PC10.QR4B.PMEH(14), Local0)
> + } else {
> + Store (\_SB.PC10.QR4B.HPEH(14), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(14, Local1)
> + Notify(\_SB.PC10.QR4B, Local0)
> + }
> +
> + // PC10 Port 4C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC10.QR4C.PMEP,1) ) {
> + Store(\_SB.PC10.QR4C.PMEH(15), Local0)
> + } else {
> + Store (\_SB.PC10.QR4C.HPEH(15), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(15, Local1)
> + Notify(\_SB.PC10.QR4C, Local0)
> + }
> +
> + // PC10 Port 4D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC10.QR4D.PMEP,1) ) {
> + Store(\_SB.PC10.QR4D.PMEH(16), Local0)
> + } else {
> + Store (\_SB.PC10.QR4D.HPEH(16), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(16, Local1)
> + Notify(\_SB.PC10.QR4D, Local0)
> + }
> +
> + // PC10 Port 5A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC11.QR5A.PMEP,1) ) {
> + Store(\_SB.PC11.QR5A.PMEH(17), Local0)
> + } else {
> + Store (\_SB.PC11.QR5A.HPEH(17), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(17, Local1)
> + Notify(\_SB.PC11.QR5A, Local0)
> + }
> +
> + // PC10 Port 5B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC11.QR5B.PMEP,1) ) {
> + Store(\_SB.PC11.QR5B.PMEH(18), Local0)
> + } else {
> + Store (\_SB.PC11.QR5B.HPEH(18), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(18, Local1)
> + Notify(\_SB.PC11.QR5B, Local0)
> + }
> +
> + // PC10 Port 5C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC11.QR5C.PMEP,1) ) {
> + Store(\_SB.PC11.QR5C.PMEH(19), Local0)
> + } else {
> + Store (\_SB.PC11.QR5C.HPEH(19), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(19, Local1)
> + Notify(\_SB.PC11.QR5C, Local0)
> + }
> +
> + // PC10 Port 5D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC11.QR5D.PMEP,1) ) {
> + Store(\_SB.PC11.QR5D.PMEH(20), Local0)
> + } else {
> + Store (\_SB.PC11.QR5D.HPEH(20), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(20, Local1)
> + Notify(\_SB.PC11.QR5D, Local0)
> + }
> +#endif
> +#if MAX_SOCKET > 2
> +
> + // PC06 Port 1A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) {
> + Store(\_SB.PC13.RR1A.PMEH(1), Local0)
> + } else {
> + Store (\_SB.PC13.RR1A.HPEH(1), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(1, Local1)
> + Notify(\_SB.PC13.RR1A, Local0)
> + }
> +
> + // PC06 Port 1B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) {
> + Store(\_SB.PC13.RR1B.PMEH(2), Local0)
> + } else {
> + Store (\_SB.PC13.RR1B.HPEH(2), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(2, Local1)
> + Notify(\_SB.PC13.RR1B, Local0)
> + }
> +
> + // PC06 Port 1C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) {
> + Store(\_SB.PC13.RR1C.PMEH(3), Local0)
> + } else {
> + Store (\_SB.PC13.RR1C.HPEH(3), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(3, Local1)
> + Notify(\_SB.PC13.RR1C, Local0)
> + }
> +
> + // PC06 Port 1D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) {
> + Store(\_SB.PC13.RR1D.PMEH(4), Local0)
> + } else {
> + Store (\_SB.PC13.RR1D.HPEH(4), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(4, Local1)
> + Notify(\_SB.PC13.RR1D, Local0)
> + }
> +
> + // PC07 Port 2A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) {
> + Store(\_SB.PC14.RR2A.PMEH(5), Local0)
> + } else {
> + Store (\_SB.PC14.RR2A.HPEH(5), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(5, Local1)
> + Notify(\_SB.PC14.RR2A, Local0)
> + }
> +
> + // PC07 Port 2B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) {
> + Store(\_SB.PC14.RR2B.PMEH(6), Local0)
> + } else {
> + Store (\_SB.PC14.RR2B.HPEH(6), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(6, Local1)
> + Notify(\_SB.PC14.RR2B, Local0)
> + }
> +
> + // PC07 Port 2C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) {
> + Store(\_SB.PC14.RR2C.PMEH(7), Local0)
> + } else {
> + Store (\_SB.PC14.RR2C.HPEH(7), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(7, Local1)
> + Notify(\_SB.PC14.RR2C, Local0)
> + }
> +
> + // PC07 Port 2D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) {
> + Store(\_SB.PC14.RR2D.PMEH(8), Local0)
> + } else {
> + Store (\_SB.PC14.RR2D.HPEH(8), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(8, Local1)
> + Notify(\_SB.PC14.RR2D, Local0)
> + }
> +
> + // PC07 Port 3A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) {
> + Store(\_SB.PC15.RR3A.PMEH(9), Local0)
> + } else {
> + Store (\_SB.PC15.RR3A.HPEH(9), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(9, Local1)
> + Notify(\_SB.PC15.RR3A, Local0)
> + }
> +
> + // PC07 Port 3B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) {
> + Store(\_SB.PC15.RR3B.PMEH(10), Local0)
> + } else {
> + Store (\_SB.PC15.RR3B.HPEH(10), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(10, Local1)
> + Notify(\_SB.PC15.RR3B, Local0)
> + }
> +
> + // PC07 Port 3C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) {
> + Store(\_SB.PC15.RR3C.PMEH(11), Local0)
> + } else {
> + Store (\_SB.PC15.RR3C.HPEH(11), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(11, Local1)
> + Notify(\_SB.PC15.RR3C, Local0)
> + }
> +
> + // PC07 Port 3D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) {
> + Store(\_SB.PC15.RR3D.PMEH(12), Local0)
> + } else {
> + Store (\_SB.PC15.RR3D.HPEH(12), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(12, Local1)
> + Notify(\_SB.PC15.RR3D, Local0)
> + }
> +
> + // PC08 Port 4A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC16.RR4A.PMEP,1) ) {
> + Store(\_SB.PC16.RR4A.PMEH(13), Local0)
> + } else {
> + Store (\_SB.PC16.RR4A.HPEH(13), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(13, Local1)
> + Notify(\_SB.PC16.RR4A, Local0)
> + }
> +
> + // PC08 Port 4B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC16.RR4B.PMEP,1) ) {
> + Store(\_SB.PC16.RR4B.PMEH(14), Local0)
> + } else {
> + Store (\_SB.PC16.RR4B.HPEH(14), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(14, Local1)
> + Notify(\_SB.PC16.RR4B, Local0)
> + }
> +
> + // PC08 Port 4C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC16.RR4C.PMEP,1) ) {
> + Store(\_SB.PC16.RR4C.PMEH(15), Local0)
> + } else {
> + Store (\_SB.PC16.RR4C.HPEH(15), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(15, Local1)
> + Notify(\_SB.PC16.RR4C, Local0)
> + }
> +
> + // PC08 Port 4D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC16.RR4D.PMEP,1) ) {
> + Store(\_SB.PC16.RR4D.PMEH(16), Local0)
> + } else {
> + Store (\_SB.PC16.RR4D.HPEH(16), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(16, Local1)
> + Notify(\_SB.PC16.RR4D, Local0)
> + }
> +
> + // PC08 Port 5A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC17.RR5A.PMEP,1) ) {
> + Store(\_SB.PC17.RR5A.PMEH(17), Local0)
> + } else {
> + Store (\_SB.PC17.RR5A.HPEH(17), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(17, Local1)
> + Notify(\_SB.PC17.RR5A, Local0)
> + }
> +
> + // PC08 Port 5B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC17.RR5B.PMEP,1) ) {
> + Store(\_SB.PC17.RR5B.PMEH(18), Local0)
> + } else {
> + Store (\_SB.PC17.RR5B.HPEH(18), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(18, Local1)
> + Notify(\_SB.PC17.RR5B, Local0)
> + }
> +
> + // PC08 Port 5C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC17.RR5C.PMEP,1) ) {
> + Store(\_SB.PC17.RR5C.PMEH(19), Local0)
> + } else {
> + Store (\_SB.PC17.RR5C.HPEH(19), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(19, Local1)
> + Notify(\_SB.PC17.RR5C, Local0)
> + }
> +
> + // PC08 Port 5D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC17.RR5D.PMEP,1) ) {
> + Store(\_SB.PC17.RR5D.PMEH(20), Local0)
> + } else {
> + Store (\_SB.PC17.RR5D.HPEH(20), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(20, Local1)
> + Notify(\_SB.PC17.RR5D, Local0)
> + }
> +#endif
> +#if MAX_SOCKET > 3
> +
> +
> + // PC09 Port 1A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) {
> + Store(\_SB.PC19.SR1A.PMEH(1), Local0)
> + } else {
> + Store (\_SB.PC19.SR1A.HPEH(1), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(1, Local1)
> + Notify(\_SB.PC19.SR1A, Local0)
> + }
> +
> + // PC09 Port 1B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) {
> + Store(\_SB.PC19.SR1B.PMEH(2), Local0)
> + } else {
> + Store (\_SB.PC19.SR1B.HPEH(2), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(2, Local1)
> + Notify(\_SB.PC19.SR1B, Local0)
> + }
> +
> + // PC09 Port 1C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) {
> + Store(\_SB.PC19.SR1C.PMEH(3), Local0)
> + } else {
> + Store (\_SB.PC19.SR1C.HPEH(3), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(3, Local1)
> + Notify(\_SB.PC19.SR1C, Local0)
> + }
> +
> + // PC09 Port 1D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) {
> + Store(\_SB.PC19.SR1D.PMEH(4), Local0)
> + } else {
> + Store (\_SB.PC19.SR1D.HPEH(4), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(4, Local1)
> + Notify(\_SB.PC19.SR1D, Local0)
> + }
> +
> + // PC10 Port 2A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) {
> + Store(\_SB.PC20.SR2A.PMEH(5), Local0)
> + } else {
> + Store (\_SB.PC20.SR2A.HPEH(5), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(5, Local1)
> + Notify(\_SB.PC20.SR2A, Local0)
> + }
> +
> + // PC10 Port 2B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) {
> + Store(\_SB.PC20.SR2B.PMEH(6), Local0)
> + } else {
> + Store (\_SB.PC20.SR2B.HPEH(6), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(6, Local1)
> + Notify(\_SB.PC20.SR2B, Local0)
> + }
> +
> + // PC10 Port 2C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) {
> + Store(\_SB.PC20.SR2C.PMEH(7), Local0)
> + } else {
> + Store (\_SB.PC20.SR2C.HPEH(7), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(7, Local1)
> + Notify(\_SB.PC20.SR2C, Local0)
> + }
> +
> + // PC10 Port 2D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) {
> + Store(\_SB.PC20.SR2D.PMEH(8), Local0)
> + } else {
> + Store (\_SB.PC20.SR2D.HPEH(8), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(8, Local1)
> + Notify(\_SB.PC20.SR2D, Local0)
> + }
> +
> + // PC10 Port 3A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) {
> + Store(\_SB.PC21.SR3A.PMEH(9), Local0)
> + } else {
> + Store (\_SB.PC21.SR3A.HPEH(9), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(9, Local1)
> + Notify(\_SB.PC21.SR3A, Local0)
> + }
> +
> + // PC10 Port 3B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) {
> + Store(\_SB.PC21.SR3B.PMEH(10), Local0)
> + } else {
> + Store (\_SB.PC21.SR3B.HPEH(10), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(10, Local1)
> + Notify(\_SB.PC21.SR3B, Local0)
> + }
> +
> + // PC10 Port 3C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) {
> + Store(\_SB.PC21.SR3C.PMEH(11), Local0)
> + } else {
> + Store (\_SB.PC21.SR3C.HPEH(11), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(11, Local1)
> + Notify(\_SB.PC21.SR3C, Local0)
> + }
> +
> + // PC10 Port 3D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) {
> + Store(\_SB.PC21.SR3D.PMEH(12), Local0)
> + } else {
> + Store (\_SB.PC21.SR3D.HPEH(12), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(12, Local1)
> + Notify(\_SB.PC21.SR3D, Local0)
> + }
> +
> + // PC11 Port 4A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC22.SR4A.PMEP,1) ) {
> + Store(\_SB.PC22.SR4A.PMEH(13), Local0)
> + } else {
> + Store (\_SB.PC22.SR4A.HPEH(13), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(13, Local1)
> + Notify(\_SB.PC22.SR4A, Local0)
> + }
> +
> + // PC11 Port 4B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC22.SR4B.PMEP,1) ) {
> + Store(\_SB.PC22.SR4B.PMEH(14), Local0)
> + } else {
> + Store (\_SB.PC22.SR4B.HPEH(14), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(14, Local1)
> + Notify(\_SB.PC22.SR4B, Local0)
> + }
> +
> + // PC11 Port 4C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC22.SR4C.PMEP,1) ) {
> + Store(\_SB.PC22.SR4C.PMEH(15), Local0)
> + } else {
> + Store (\_SB.PC22.SR4C.HPEH(15), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(15, Local1)
> + Notify(\_SB.PC22.SR4C, Local0)
> + }
> +
> + // PC11 Port 4D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC22.SR4D.PMEP,1) ) {
> + Store(\_SB.PC22.SR4D.PMEH(16), Local0)
> + } else {
> + Store (\_SB.PC22.SR4D.HPEH(16), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(16, Local1)
> + Notify(\_SB.PC22.SR4D, Local0)
> + }
> +
> + // PC11 Port 5A PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC23.SR5A.PMEP,1) ) {
> + Store(\_SB.PC23.SR5A.PMEH(17), Local0)
> + } else {
> + Store (\_SB.PC23.SR5A.HPEH(17), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(17, Local1)
> + Notify(\_SB.PC23.SR5A, Local0)
> + }
> +
> + // PC11 Port 5B PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC23.SR5B.PMEP,1) ) {
> + Store(\_SB.PC23.SR5B.PMEH(18), Local0)
> + } else {
> + Store (\_SB.PC23.SR5B.HPEH(18), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(18, Local1)
> + Notify(\_SB.PC23.SR5B, Local0)
> + }
> +
> + // PC11 Port 5C PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC23.SR5C.PMEP,1) ) {
> + Store(\_SB.PC23.SR5C.PMEH(19), Local0)
> + } else {
> + Store (\_SB.PC23.SR5C.HPEH(19), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(19, Local1)
> + Notify(\_SB.PC23.SR5C, Local0)
> + }
> +
> + // PC11 Port 5D PCI-Ex Hot Plug
> + // If PM_PME event clear INTs and AttnBtnPressed
> + If( LEqual(\_SB.PC23.SR5D.PMEP,1) ) {
> + Store(\_SB.PC23.SR5D.PMEH(20), Local0)
> + } else {
> + Store (\_SB.PC23.SR5D.HPEH(20), Local0)
> + }
> + If(Lnot(LEqual(Local0,0xFF))) {
> + Store(20, Local1)
> + Notify(\_SB.PC23.SR5D, Local0)
> + }
> +#endif
> +
> + //If a hotplug event was serviced check if this was generated by PM_PME
> + If (Lnot (LEqual(Local0, 0))) {
> + //Clear the status bit 16 of PMEStatus
> + //Clear the PME Pending bit 17 of PMEStatus
> + If( LEqual(Local1, 1)) {
> + Store(1, \_SB.PC01.BR1A.PMES)
> + Store(1, \_SB.PC01.BR1A.PMEP)
> + }
> + If( LEqual(Local1, 2)) {
> + Store(1, \_SB.PC01.BR1B.PMES)
> + Store(1, \_SB.PC01.BR1B.PMEP)
> + }
> + If( LEqual(Local1, 3)) {
> + Store(1, \_SB.PC01.BR1C.PMES)
> + Store(1, \_SB.PC01.BR1C.PMEP)
> + }
> + If( LEqual(Local1, 4)) {
> + Store(1, \_SB.PC01.BR1D.PMES)
> + Store(1, \_SB.PC01.BR1D.PMEP)
> + }
> +
> + If( LEqual(Local1, 5)) {
> + Store(1, \_SB.PC02.BR2A.PMES)
> + Store(1, \_SB.PC02.BR2A.PMEP)
> + }
> + If( LEqual(Local1, 6)) {
> + Store(1, \_SB.PC02.BR2B.PMES)
> + Store(1, \_SB.PC02.BR2B.PMEP)
> + }
> + If( LEqual(Local1, 7)) {
> + Store(1, \_SB.PC02.BR2C.PMES)
> + Store(1, \_SB.PC02.BR2C.PMEP)
> + }
> + If( LEqual(Local1, 8)) {
> + Store(1, \_SB.PC02.BR2D.PMES)
> + Store(1, \_SB.PC02.BR2D.PMEP)
> + }
> + If( LEqual(Local1, 9)) {
> + Store(1, \_SB.PC03.BR3A.PMES)
> + Store(1, \_SB.PC03.BR3A.PMEP)
> + }
> + If( LEqual(Local1, 10)) {
> + Store(1, \_SB.PC03.BR3B.PMES)
> + Store(1, \_SB.PC03.BR3B.PMEP)
> + }
> + If( LEqual(Local1, 11)) {
> + Store(1, \_SB.PC03.BR3C.PMES)
> + Store(1, \_SB.PC03.BR3C.PMEP)
> + }
> + If( LEqual(Local1, 12)) {
> + Store(1, \_SB.PC03.BR3D.PMES)
> + Store(1, \_SB.PC03.BR3D.PMEP)
> + }
> + If( LEqual(Local1, 13)) {
> + Store(1, \_SB.PC04.BR4A.PMES)
> + Store(1, \_SB.PC04.BR4A.PMEP)
> + }
> + If( LEqual(Local1, 14)) {
> + Store(1, \_SB.PC04.BR4B.PMES)
> + Store(1, \_SB.PC04.BR4B.PMEP)
> + }
> + If( LEqual(Local1, 15)) {
> + Store(1, \_SB.PC04.BR4C.PMES)
> + Store(1, \_SB.PC04.BR4C.PMEP)
> + }
> + If( LEqual(Local1, 16)) {
> + Store(1, \_SB.PC04.BR4D.PMES)
> + Store(1, \_SB.PC04.BR4D.PMEP)
> + }
> + If( LEqual(Local1, 17)) {
> + Store(1, \_SB.PC05.BR5A.PMES)
> + Store(1, \_SB.PC05.BR5A.PMEP)
> + }
> + If( LEqual(Local1, 18)) {
> + Store(1, \_SB.PC05.BR5B.PMES)
> + Store(1, \_SB.PC05.BR5B.PMEP)
> + }
> + If( LEqual(Local1, 19)) {
> + Store(1, \_SB.PC05.BR5C.PMES)
> + Store(1, \_SB.PC05.BR5C.PMEP)
> + }
> + If( LEqual(Local1, 20)) {
> + Store(1, \_SB.PC05.BR5D.PMES)
> + Store(1, \_SB.PC05.BR5D.PMEP)
> + }
> +
> +#if MAX_SOCKET > 1
> + If( LEqual(Local1, 1)) {
> + Store(1, \_SB.PC07.QR1A.PMES)
> + Store(1, \_SB.PC07.QR1A.PMEP)
> + }
> + If( LEqual(Local1, 2)) {
> + Store(1, \_SB.PC07.QR1B.PMES)
> + Store(1, \_SB.PC07.QR1B.PMEP)
> + }
> + If( LEqual(Local1, 3)) {
> + Store(1, \_SB.PC07.QR1C.PMES)
> + Store(1, \_SB.PC07.QR1C.PMEP)
> + }
> + If( LEqual(Local1, 4)) {
> + Store(1, \_SB.PC07.QR1D.PMES)
> + Store(1, \_SB.PC07.QR1D.PMEP)
> + }
> + If( LEqual(Local1, 5)) {
> + Store(1, \_SB.PC08.QR2A.PMES)
> + Store(1, \_SB.PC08.QR2A.PMEP)
> + }
> + If( LEqual(Local1, 6)) {
> + Store(1, \_SB.PC08.QR2B.PMES)
> + Store(1, \_SB.PC08.QR2B.PMEP)
> + }
> + If( LEqual(Local1, 7)) {
> + Store(1, \_SB.PC08.QR2C.PMES)
> + Store(1, \_SB.PC08.QR2C.PMEP)
> + }
> + If( LEqual(Local1, 8)) {
> + Store(1, \_SB.PC08.QR2D.PMES)
> + Store(1, \_SB.PC08.QR2D.PMEP)
> + }
> + If( LEqual(Local1, 9)) {
> + Store(1, \_SB.PC09.QR3A.PMES)
> + Store(1, \_SB.PC09.QR3A.PMEP)
> + }
> + If( LEqual(Local1, 10)) {
> + Store(1, \_SB.PC09.QR3B.PMES)
> + Store(1, \_SB.PC09.QR3B.PMEP)
> + }
> + If( LEqual(Local1, 11)) {
> + Store(1, \_SB.PC09.QR3C.PMES)
> + Store(1, \_SB.PC09.QR3C.PMEP)
> + }
> + If( LEqual(Local1, 12)) {
> + Store(1, \_SB.PC09.QR3D.PMES)
> + Store(1, \_SB.PC09.QR3D.PMEP)
> + }
> + If( LEqual(Local1, 13)) {
> + Store(1, \_SB.PC10.QR4A.PMES)
> + Store(1, \_SB.PC10.QR4A.PMEP)
> + }
> + If( LEqual(Local1, 14)) {
> + Store(1, \_SB.PC10.QR4B.PMES)
> + Store(1, \_SB.PC10.QR4B.PMEP)
> + }
> + If( LEqual(Local1, 15)) {
> + Store(1, \_SB.PC10.QR4C.PMES)
> + Store(1, \_SB.PC10.QR4C.PMEP)
> + }
> + If( LEqual(Local1, 16)) {
> + Store(1, \_SB.PC10.QR4D.PMES)
> + Store(1, \_SB.PC10.QR4D.PMEP)
> + }
> + If( LEqual(Local1, 17)) {
> + Store(1, \_SB.PC11.QR5A.PMES)
> + Store(1, \_SB.PC11.QR5A.PMEP)
> + }
> + If( LEqual(Local1, 18)) {
> + Store(1, \_SB.PC11.QR5B.PMES)
> + Store(1, \_SB.PC11.QR5B.PMEP)
> + }
> + If( LEqual(Local1, 19)) {
> + Store(1, \_SB.PC11.QR5C.PMES)
> + Store(1, \_SB.PC11.QR5C.PMEP)
> + }
> + If( LEqual(Local1, 20)) {
> + Store(1, \_SB.PC11.QR5D.PMES)
> + Store(1, \_SB.PC11.QR5D.PMEP)
> + }
> +#endif
> +#if MAX_SOCKET > 2
> +
> + If( LEqual(Local1, 1)) {
> + Store(1, \_SB.PC13.RR1A.PMES)
> + Store(1, \_SB.PC13.RR1A.PMEP)
> + }
> + If( LEqual(Local1, 2)) {
> + Store(1, \_SB.PC13.RR1B.PMES)
> + Store(1, \_SB.PC13.RR1B.PMEP)
> + }
> + If( LEqual(Local1, 3)) {
> + Store(1, \_SB.PC13.RR1C.PMES)
> + Store(1, \_SB.PC13.RR1C.PMEP)
> + }
> + If( LEqual(Local1, 4)) {
> + Store(1, \_SB.PC13.RR1D.PMES)
> + Store(1, \_SB.PC13.RR1D.PMEP)
> + }
> + If( LEqual(Local1, 5)) {
> + Store(1, \_SB.PC14.RR2A.PMES)
> + Store(1, \_SB.PC14.RR2A.PMEP)
> + }
> + If( LEqual(Local1, 6)) {
> + Store(1, \_SB.PC14.RR2B.PMES)
> + Store(1, \_SB.PC14.RR2B.PMEP)
> + }
> + If( LEqual(Local1, 7)) {
> + Store(1, \_SB.PC14.RR2C.PMES)
> + Store(1, \_SB.PC14.RR2C.PMEP)
> + }
> + If( LEqual(Local1, 8)) {
> + Store(1, \_SB.PC14.RR2D.PMES)
> + Store(1, \_SB.PC14.RR2D.PMEP)
> + }
> + If( LEqual(Local1, 9)) {
> + Store(1, \_SB.PC15.RR3A.PMES)
> + Store(1, \_SB.PC15.RR3A.PMEP)
> + }
> + If( LEqual(Local1, 10)) {
> + Store(1, \_SB.PC15.RR3B.PMES)
> + Store(1, \_SB.PC15.RR3B.PMEP)
> + }
> + If( LEqual(Local1, 11)) {
> + Store(1, \_SB.PC15.RR3C.PMES)
> + Store(1, \_SB.PC15.RR3C.PMEP)
> + }
> + If( LEqual(Local1, 12)) {
> + Store(1, \_SB.PC15.RR3D.PMES)
> + Store(1, \_SB.PC15.RR3D.PMEP)
> + }
> + If( LEqual(Local1, 13)) {
> + Store(1, \_SB.PC16.RR4A.PMES)
> + Store(1, \_SB.PC16.RR4A.PMEP)
> + }
> + If( LEqual(Local1, 14)) {
> + Store(1, \_SB.PC16.RR4B.PMES)
> + Store(1, \_SB.PC16.RR4B.PMEP)
> + }
> + If( LEqual(Local1, 15)) {
> + Store(1, \_SB.PC16.RR4C.PMES)
> + Store(1, \_SB.PC16.RR4C.PMEP)
> + }
> + If( LEqual(Local1, 16)) {
> + Store(1, \_SB.PC16.RR4D.PMES)
> + Store(1, \_SB.PC16.RR4D.PMEP)
> + }
> + If( LEqual(Local1, 17)) {
> + Store(1, \_SB.PC17.RR5A.PMES)
> + Store(1, \_SB.PC17.RR5A.PMEP)
> + }
> + If( LEqual(Local1, 18)) {
> + Store(1, \_SB.PC17.RR5B.PMES)
> + Store(1, \_SB.PC17.RR5B.PMEP)
> + }
> + If( LEqual(Local1, 19)) {
> + Store(1, \_SB.PC17.RR5C.PMES)
> + Store(1, \_SB.PC17.RR5C.PMEP)
> + }
> + If( LEqual(Local1, 20)) {
> + Store(1, \_SB.PC17.RR5D.PMES)
> + Store(1, \_SB.PC17.RR5D.PMEP)
> + }
> +#endif
> +#if MAX_SOCKET > 3
> +
> + If( LEqual(Local1, 1)) {
> + Store(1, \_SB.PC19.SR1A.PMES)
> + Store(1, \_SB.PC19.SR1A.PMEP)
> + }
> + If( LEqual(Local1, 2)) {
> + Store(1, \_SB.PC19.SR1B.PMES)
> + Store(1, \_SB.PC19.SR1B.PMEP)
> + }
> + If( LEqual(Local1, 3)) {
> + Store(1, \_SB.PC19.SR1C.PMES)
> + Store(1, \_SB.PC19.SR1C.PMEP)
> + }
> + If( LEqual(Local1, 4)) {
> + Store(1, \_SB.PC19.SR1D.PMES)
> + Store(1, \_SB.PC19.SR1D.PMEP)
> + }
> + If( LEqual(Local1, 5)) {
> + Store(1, \_SB.PC20.SR2A.PMES)
> + Store(1, \_SB.PC20.SR2A.PMEP)
> + }
> + If( LEqual(Local1, 6)) {
> + Store(1, \_SB.PC20.SR2B.PMES)
> + Store(1, \_SB.PC20.SR2B.PMEP)
> + }
> + If( LEqual(Local1, 7)) {
> + Store(1, \_SB.PC20.SR2C.PMES)
> + Store(1, \_SB.PC20.SR2C.PMEP)
> + }
> + If( LEqual(Local1, 8)) {
> + Store(1, \_SB.PC20.SR2D.PMES)
> + Store(1, \_SB.PC20.SR2D.PMEP)
> + }
> + If( LEqual(Local1, 9)) {
> + Store(1, \_SB.PC21.SR3A.PMES)
> + Store(1, \_SB.PC21.SR3A.PMEP)
> + }
> + If( LEqual(Local1, 10)) {
> + Store(1, \_SB.PC21.SR3B.PMES)
> + Store(1, \_SB.PC21.SR3B.PMEP)
> + }
> + If( LEqual(Local1, 11)) {
> + Store(1, \_SB.PC21.SR3C.PMES)
> + Store(1, \_SB.PC21.SR3C.PMEP)
> + }
> + If( LEqual(Local1, 12)) {
> + Store(1, \_SB.PC21.SR3D.PMES)
> + Store(1, \_SB.PC21.SR3D.PMEP)
> + }
> + If( LEqual(Local1, 13)) {
> + Store(1, \_SB.PC22.SR4A.PMES)
> + Store(1, \_SB.PC22.SR4A.PMEP)
> + }
> + If( LEqual(Local1, 14)) {
> + Store(1, \_SB.PC22.SR4B.PMES)
> + Store(1, \_SB.PC22.SR4B.PMEP)
> + }
> + If( LEqual(Local1, 15)) {
> + Store(1, \_SB.PC22.SR4C.PMES)
> + Store(1, \_SB.PC22.SR4C.PMEP)
> + }
> + If( LEqual(Local1, 16)) {
> + Store(1, \_SB.PC22.SR4D.PMES)
> + Store(1, \_SB.PC22.SR4D.PMEP)
> + }
> + If( LEqual(Local1, 17)) {
> + Store(1, \_SB.PC23.SR5A.PMES)
> + Store(1, \_SB.PC23.SR5A.PMEP)
> + }
> + If( LEqual(Local1, 18)) {
> + Store(1, \_SB.PC23.SR5B.PMES)
> + Store(1, \_SB.PC23.SR5B.PMEP)
> + }
> + If( LEqual(Local1, 19)) {
> + Store(1, \_SB.PC23.SR5C.PMES)
> + Store(1, \_SB.PC23.SR5C.PMEP)
> + }
> + If( LEqual(Local1, 20)) {
> + Store(1, \_SB.PC23.SR5D.PMES)
> + Store(1, \_SB.PC23.SR5D.PMEP)
> + }
> +#endif
> + Store(0x01,PEES) //Clear bit 9 of Status
> + Store(0x00,PMEE) //Clear bit 9 of GPE0_EN
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridge.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridge.asi
> new file mode 100644
> index 0000000000..3126e29de7
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridge.asi
> @@ -0,0 +1,328 @@
> +/** @file
> +
> + @copyright
> + Copyright 2008 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + External (DBGM, FieldUnitObj)
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + //
> + // _BBN is ACPI method called by OS to read PCI base bus number for IIO
> stack.
> + //
> + Method(_BBN, 0, NotSerialized)
> + {
> + Return(CONCATENATE3(BB, SOCKET, STACK))
> + }
> +
> + //
> + // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA
> Node) where IIO stack belongs to.
> + // Without SNC (Sub-NUMA Cluster) proximity domain is socket. If two
> SNC domains are enabled report
> + // PCI stacks 0..2 in the first SNC domain of a socket, and upper stacks in
> the second SNC domain in this socket.
> + // If four SNC domains are enabled report stacks 0,1 in first domain; stack 2
> in second; 3,4 in third;
> + // and upper stacks in the fourth SNC domain in this socket.
> + //
> + Method(_PXM, 0, NotSerialized)
> + {
> + Store(SOCKET, Local0)
> + Switch (ToInteger(CLOD)) { // CLOD contains the number of SNC domains
> per socekt
> + Case (2) {
> + Multiply(Local0, CLOD, Local0)
> +#if STACK > 2
> + Add(Local0, 1, Local0)
> +#endif
> + }
> + Case (4) {
> + Multiply(Local0, CLOD, Local0)
> +#if STACK > 3
> + Add(Local0, 3, Local0)
> +#elif STACK > 2
> + Add(Local0, 2, Local0)
> +#elif STACK > 0
> + Add(Local0, 1, Local0)
> +#endif
> + }
> + }
> + Return(Local0)
> + }
> +
> + //
> + // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
> + //
> + Method(_SEG, 0, NotSerialized)
> + {
> + Return(CONCATENATE2(SG0, SOCKET))
> + }
> +
> + //
> + // _STA is ACPI method called by OS to read status of ACPI device, IIO stack
> in this case.
> + //
> + Method(_STA, 0, NotSerialized)
> + { //
> + // Check in processor present bitmap (PRBM) if processor is present, then
> + // in stack present bitmap of given processor (SPBx) if stack is present.
> + //
> + ShiftLeft(1, SOCKET, Local0)
> + If (And(PRBM, Local0)) {
> +
> + ShiftLeft(1, CONCATENATE2(0x,STACK), Local1)
> + if (And(CONCATENATE2(SPB, SOCKET), Local1)) {
> + Return(0x0F)
> + }
> + }
> + Return(0x00)
> + }
> +
> + Method(_OSC, 4)
> + {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> +
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,4,CDW2)
> +
> + //
> + // Fill 3rd capability DWORD only if the count is greater than 2.
> + //
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x10), 0x10))) { // Conditions not
> met?
> + And(CTRL, Not(1), CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system), Mask bit 1
> + //
> + And(CTRL, Not(2), CTRL)
> +
> +
> + //
> + // Select Native PCIe AER/eDPC handling from OS or Firmware First
> model
> + //
> + If (CondRefOf (\_SB.OSNC))
> + {
> + //in case OS has AER capability.
> + If (LEqual ( And(CTRL, 8), 8)) {
> +
> + //in case OS support multiple segment.
> + If (And (SUPP, 8)) {
> + If (CondRefof (^_SEG))
> + {
> + Store (^_SEG, Local0)
> + } Else {
> + Store (0, Local0)
> + }
> + } Else {
> + Store (0, Local0)
> + }
> +
> + Store (^_BBN, Local1)
> +
> + // if BIOS allows OS take. Do nothing.
> + If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) {
> +
> + } Else {
> + And (CTRL, Not(0x88), CTRL)
> + }
> + } Else {
> + And (CTRL, Not(0x88), CTRL)
> + }
> + } Else {
> + //
> + //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, eDPC is
> bit7
> + //
> + And (CTRL, Not(0x88), CTRL)
> + }
> +
> + If (Not(And(CDW1,1))) { // Query Flag Clear?
> + //
> + // Disable GPEs for Features granted native control
> + //
> + If (And(CTRL, 0x01)) { // Native Hot plug control granted?
> + \_SB.OSCM (_UID)
> + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
> + }
> + }
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + if(LEqual(DBGM, 0x01)){
> + Store (0xEE, IO80)
> + }
> + Return(Arg3)
> + }
> + } // End _OSC
> +
> + Name(RBRS, ResourceTemplate() {
> + //RESOURCE_CHUNK1_OFF
> + WORDBusNumber( //Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI
> Platform Driver during POST)
> + ,
> + ,
> + FIX1 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //: Off board video card not detected in device manager when it is
> connected to CPU
> + //RESOURCE_CHUNK5_OFF
> + DWORDMEMORY( // descriptor for video RAM on video card
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode,
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is Fixed
> + Cacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform
> Driver during POST)
> + ,
> + ,
> + FIX5 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //RESOURCE_CHUNK2_OFF
> + WORDIO( //Consumed-and-produced resource (all I/O above
> CFF)
> + ResourceProducer, // bit 0 of general flags is 0
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode,
> + EntireRange,
> + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI
> Platform Driver during POST)
> + ,
> + ,
> + FIX2 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //Off board video card not detected in device manager when it is
> connected to CPU
> + //Descriptor for IO space of the video card.
> + WORDIO( // Consumed-and-produced resource (all I/O below
> CF8)
> + ResourceProducer, // bit 0 of general flags is 0
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode,
> + EntireRange,
> + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0000, // Range Length
> + ,
> + ,
> + FIX6 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //Off board video card not detected in device manager when it is
> connected to CPU
> + //Descriptor for IO space of the video card.
> + WORDIO( // Consumed-and-produced resource (all I/O below
> CF8)
> + ResourceProducer, // bit 0 of general flags is 0
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode,
> + EntireRange,
> + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0000, // Range Length
> + ,
> + ,
> + FIX7 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //
> + // PCI RESOURCE_32bit
> + //
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX3 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIX3 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //
> + // PCI RESOURCE_64bit
> + //
> + QWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform
> Driver during POST)
> + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 -
> Patched by ACPI Platform Driver during POST)
> + 0x00000000000, // Translation
> + 0x00000000000, // Range Length (calculated dynamically) (FIX4 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIX4 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> + }) // end of PRXX Buffer
> +
> + // Current resource template return
> + Method(_CRS, 0x0, NotSerialized)
> + {
> + Return(RBRS)
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridgeIcx.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridgeIcx.asi
> new file mode 100644
> index 0000000000..1dc42a9ca8
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Iio
> RootBridgeIcx.asi
> @@ -0,0 +1,270 @@
> +/** @file
> +
> + @copyright
> + Copyright 2008 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "MaxSocket.h"
> +
> + Method(OSCM, 1) {
> +
> + if (LEqual(Arg0, 1)) { // PC01
> + \_SB.PC01.BR1A.OSHP ()
> + \_SB.PC01.BR1B.OSHP ()
> + \_SB.PC01.BR1C.OSHP ()
> + \_SB.PC01.BR1D.OSHP ()
> + }
> + if (LEqual(Arg0, 2)) { // PC01
> + \_SB.PC02.BR2A.OSHP ()
> + \_SB.PC02.BR2B.OSHP ()
> + \_SB.PC02.BR2C.OSHP ()
> + \_SB.PC02.BR2D.OSHP ()
> + }
> + if (LEqual(Arg0, 3)) { // PC02
> + \_SB.PC03.BR3A.OSHP ()
> + \_SB.PC03.BR3B.OSHP ()
> + \_SB.PC03.BR3C.OSHP ()
> + \_SB.PC03.BR3D.OSHP ()
> + }
> + if (LEqual(Arg0, 4)) { // PC02
> + \_SB.PC04.BR4A.OSHP ()
> + \_SB.PC04.BR4B.OSHP ()
> + \_SB.PC04.BR4C.OSHP ()
> + \_SB.PC04.BR4D.OSHP ()
> + }
> + if (LEqual(Arg0, 5)) { // PC01
> + \_SB.PC05.BR5A.OSHP ()
> + \_SB.PC05.BR5B.OSHP ()
> + \_SB.PC05.BR5C.OSHP ()
> + \_SB.PC05.BR5D.OSHP ()
> + }
> +
> +#if MAX_SOCKET > 1
> + if (LEqual(Arg0, 7)) { // PC07
> + \_SB.PC07.QR1A.OSHP ()
> + \_SB.PC07.QR1B.OSHP ()
> + \_SB.PC07.QR1C.OSHP ()
> + \_SB.PC07.QR1D.OSHP ()
> + }
> + if (LEqual(Arg0, 8)) { // PC08
> + \_SB.PC08.QR2A.OSHP ()
> + \_SB.PC08.QR2B.OSHP ()
> + \_SB.PC08.QR2C.OSHP ()
> + \_SB.PC08.QR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 9)) { // PC09
> + \_SB.PC09.QR3A.OSHP ()
> + \_SB.PC09.QR3B.OSHP ()
> + \_SB.PC09.QR3C.OSHP ()
> + \_SB.PC09.QR3D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 10)) { // PC10
> +
> + \_SB.PC10.QR4A.OSHP ()
> + \_SB.PC10.QR4B.OSHP ()
> + \_SB.PC10.QR4C.OSHP ()
> + \_SB.PC10.QR4D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 11)) { // PC11
> + \_SB.PC11.QR5A.OSHP ()
> + \_SB.PC11.QR5B.OSHP ()
> + \_SB.PC11.QR5C.OSHP ()
> + \_SB.PC11.QR5D.OSHP ()
> + }
> +
> +#endif
> +
> +#if MAX_SOCKET > 2
> + if (LEqual(Arg0, 13)) { // PC13
> + \_SB.PC13.RR1A.OSHP ()
> + \_SB.PC13.RR1B.OSHP ()
> + \_SB.PC13.RR1C.OSHP ()
> + \_SB.PC13.RR1D.OSHP ()
> + }
> + if (LEqual(Arg0, 14)) { // PC14
> + \_SB.PC14.RR2A.OSHP ()
> + \_SB.PC14.RR2B.OSHP ()
> + \_SB.PC14.RR2C.OSHP ()
> + \_SB.PC14.RR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 15)) { // PC15
> + \_SB.PC15.RR3A.OSHP ()
> + \_SB.PC15.RR3B.OSHP ()
> + \_SB.PC15.RR3C.OSHP ()
> + \_SB.PC15.RR3D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 16)) { // PC16
> +
> + \_SB.PC16.RR4A.OSHP ()
> + \_SB.PC16.RR4B.OSHP ()
> + \_SB.PC16.RR4C.OSHP ()
> + \_SB.PC16.RR4D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 17)) { // PC17
> + \_SB.PC17.RR5A.OSHP ()
> + \_SB.PC17.RR5B.OSHP ()
> + \_SB.PC17.RR5C.OSHP ()
> + \_SB.PC17.RR5D.OSHP ()
> + }
> +
> +#endif
> +
> +
> +#if MAX_SOCKET > 3
> + if (LEqual(Arg0, 19)) { // PC19
> + \_SB.PC19.SR1A.OSHP ()
> + \_SB.PC19.SR1B.OSHP ()
> + \_SB.PC19.SR1C.OSHP ()
> + \_SB.PC19.SR1D.OSHP ()
> + }
> + if (LEqual(Arg0, 20)) { // PC20
> + \_SB.PC20.SR2A.OSHP ()
> + \_SB.PC20.SR2B.OSHP ()
> + \_SB.PC20.SR2C.OSHP ()
> + \_SB.PC20.SR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 21)) { // PC21
> + \_SB.PC21.SR3A.OSHP ()
> + \_SB.PC21.SR3B.OSHP ()
> + \_SB.PC21.SR3C.OSHP ()
> + \_SB.PC21.SR3D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 22)) { // PC22
> +
> + \_SB.PC22.SR4A.OSHP ()
> + \_SB.PC22.SR4B.OSHP ()
> + \_SB.PC22.SR4C.OSHP ()
> + \_SB.PC22.SR4D.OSHP ()
> +
> + }
> + if (LEqual(Arg0, 23)) { // PC23
> + \_SB.PC23.SR5A.OSHP ()
> + \_SB.PC23.SR5B.OSHP ()
> + \_SB.PC23.SR5C.OSHP ()
> + \_SB.PC23.SR5D.OSHP ()
> + }
> +
> +#endif
> +#if MAX_SOCKET > 4
> + if (LEqual(Arg0,25)) { // PC12
> + \_SB.PC25.CR1A.OSHP ()
> + \_SB.PC25.CR1B.OSHP ()
> + \_SB.PC25.CR1C.OSHP ()
> + \_SB.PC25.CR1D.OSHP ()
> + }
> + if (LEqual(Arg0,26)) { // PC13
> + \_SB.PC26.CR2A.OSHP ()
> + \_SB.PC26.CR2B.OSHP ()
> + \_SB.PC26.CR2C.OSHP ()
> + \_SB.PC26.CR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0,27)) { // PC12
> + \_SB.PC27.CR3A.OSHP ()
> + \_SB.PC27.CR3B.OSHP ()
> + \_SB.PC27.CR3C.OSHP ()
> + \_SB.PC27.CR3D.OSHP ()
> + }
> + if (LEqual(Arg0,28)) { // PC13
> + \_SB.PC28.CR4A.OSHP ()
> + \_SB.PC28.CR4B.OSHP ()
> + \_SB.PC28.CR4C.OSHP ()
> + \_SB.PC28.CR4D.OSHP ()
> + }
> + if (LEqual(Arg0,29)) { // PC14
> + \_SB.PC29.CR5A.OSHP ()
> + \_SB.PC29.CR5B.OSHP ()
> + \_SB.PC29.CR5C.OSHP ()
> + \_SB.PC29.CR5D.OSHP ()
> + }
> +#endif
> +#if MAX_SOCKET > 5
> + if (LEqual(Arg0,31)) { // PC15
> + \_SB.PC31.TR1A.OSHP ()
> + \_SB.PC31.TR1B.OSHP ()
> + \_SB.PC31.TR1C.OSHP ()
> + \_SB.PC31.TR1D.OSHP ()
> + }
> + if (LEqual(Arg0,32)) { // PC16
> + \_SB.PC32.TR2A.OSHP ()
> + \_SB.PC32.TR2B.OSHP ()
> + \_SB.PC32.TR2C.OSHP ()
> + \_SB.PC32.TR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0,33)) { // PC15
> + \_SB.PC33.TR3A.OSHP ()
> + \_SB.PC33.TR3B.OSHP ()
> + \_SB.PC33.TR3C.OSHP ()
> + \_SB.PC33.TR3D.OSHP ()
> + }
> + if (LEqual(Arg0,34)) { // PC16
> + \_SB.PC34.TR4A.OSHP ()
> + \_SB.PC34.TR4B.OSHP ()
> + \_SB.PC34.TR4C.OSHP ()
> + \_SB.PC34.TR4D.OSHP ()
> + }
> + if (LEqual(Arg0,35)) { // PC17
> + \_SB.PC35.TR5A.OSHP ()
> + \_SB.PC35.TR5B.OSHP ()
> + \_SB.PC35.TR5C.OSHP ()
> + \_SB.PC35.TR5D.OSHP ()
> + }
> +#endif
> +#if MAX_SOCKET > 6
> + if (LEqual(Arg0,37)) { // PC37
> + \_SB.PC37.UR1A.OSHP ()
> + \_SB.PC37.UR1B.OSHP ()
> + \_SB.PC37.UR1C.OSHP ()
> + \_SB.PC37.UR1D.OSHP ()
> + }
> + if (LEqual(Arg0,38)) { // PC38
> + \_SB.PC38.UR2A.OSHP ()
> + \_SB.PC38.UR2B.OSHP ()
> + \_SB.PC38.UR2C.OSHP ()
> + \_SB.PC38.UR2D.OSHP ()
> +
> + }
> + if (LEqual(Arg0,39)) { // PC39
> + \_SB.PC39.UR3A.OSHP ()
> + \_SB.PC39.UR3B.OSHP ()
> + \_SB.PC39.UR3C.OSHP ()
> + \_SB.PC39.UR3D.OSHP ()
> + }
> + if (LEqual(Arg0,40)) { // PC40
> + \_SB.PC40.UR4A.OSHP ()
> + \_SB.PC40.UR4B.OSHP ()
> + \_SB.PC40.UR4C.OSHP ()
> + \_SB.PC40.UR4D.OSHP ()
> + }
> + if (LEqual(Arg0,41)) { // PC41
> +
> + \_SB.PC41.UR5A.OSHP ()
> + \_SB.PC41.UR5B.OSHP ()
> + \_SB.PC41.UR5C.OSHP ()
> + \_SB.PC41.UR5D.OSHP ()
> + }
> +#endif
> +#if MAX_SOCKET > 7
> + if (LEqual(Arg0,43)) { // PC43
> + \_SB.PC43.VR1A.OSHP ()
> + \_SB.PC43.VR1B.OSHP ()
> + \_SB.PC43.VR1C.OSHP ()
> + \_SB.PC43.VR1D.OSHP ()
> + }
> + if (LEqual(Arg0,44)) { // PC44
> + }
> + if (LEqual(Arg0,45)) { // PC45
> + }
> +#endif
> + } // end of OSCM
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo
> ther.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo
> ther.asi
> new file mode 100644
> index 0000000000..90dbfabcbe
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mo
> ther.asi
> @@ -0,0 +1,164 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Device (DMAC) {
> + Name (_HID, EISAID("PNP0200"))
> + Name (_CRS,ResourceTemplate() {
> + IO(Decode16, 0x0, 0x0, 0, 0x10)
> + IO(Decode16, 0x81, 0x81, 0, 0x3)
> + IO(Decode16, 0x87, 0x87, 0, 0x1)
> + IO(Decode16, 0x89, 0x89, 0, 0x3)
> + IO(Decode16, 0x8f, 0x8f, 0, 0x1)
> + IO(Decode16, 0xc0, 0xc0, 0, 0x20)
> + DMA(Compatibility,NotBusMaster,Transfer8) {4}
> + })
> +}
> +
> +Device (RTC) {
> + Name (_HID,EISAID("PNP0B00"))
> + Name (_CRS,ResourceTemplate() {
> + IO(Decode16,0x70,0x70,0x01,0x02)
> + IO(Decode16,0x72,0x72,0x01,0x02)
> + IO(Decode16,0x74,0x74,0x01,0x04)
> + IRQNoFlags(){8}
> + })
> +}
> +
> +Device (PIC) {
> + Name (_HID,EISAID("PNP0000"))
> + Name (_CRS,ResourceTemplate() {
> + IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases
> + IO(Decode16,0xA0,0xA0,0x01,0x1E)
> + IO(Decode16,0x4D0,0x4D0,0x01,0x02)
> + })
> +}
> +
> +Device (FPU) {
> + Name (_HID,EISAID("PNP0C04"))
> + Name (_CRS,ResourceTemplate() {
> + IO(Decode16,0xF0,0xF0,0x01,0x1)
> + IRQNoFlags(){13}
> + })
> +}
> +
> +Device(TMR)
> +{
> + Name(_HID,EISAID("PNP0100"))
> +
> + Name(_CRS,ResourceTemplate() {
> + IO(Decode16,0x40,0x40,0x01,0x04)
> + IO(Decode16,0x50,0x50,0x01,0x04) // alias
> + IRQNoFlags(){0}
> + })
> +}
> +
> +Device (SPKR) {
> + Name (_HID,EISAID("PNP0800"))
> + Name (_CRS,ResourceTemplate() {
> + IO(Decode16,0x61,0x61,0x01,0x01)
> + })
> +}
> +
> +//
> +// all "PNP0C02" devices- pieces that don't fit anywhere else
> +//
> +Device(XTRA) {
> + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
> + Name(_CRS,
> + ResourceTemplate() {
> + IO(Decode16,0x500,0x500,0x01,0xFF) // ACPI base
> + IO(Decode16,0x400,0x400,0x01,0x20) // PM IO, ICH5
> +
> + //
> + // Resource conflict with COM Port
> + //
> + //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime registers,
> National SIO
> + IO(Decode16,0x10,0x10,0x01,0x10)
> + IO(Decode16,0x80,0x80,0x01,0x01)
> + IO(Decode16,0x84,0x84,0x01,0x03)
> + IO(Decode16,0x88,0x88,0x01,0x01)
> + IO(Decode16,0x8c,0x8c,0x01,0x03)
> + IO(Decode16,0x90,0x90,0x01,0x10)
> + //
> + // Pilot Mail Box decode range
> + //
> + IO(Decode16,0x600,0x600,0x01,0x20)
> + //
> + // BMC KCS decode range
> + //
> + IO(Decode16,0xCA0,0xCA0,0x01,0x2)
> + IO(Decode16,0xCA4,0xCA4,0x01,0x3)
> +
> + //IO Descriptor added for range 2F8-2FF for S501706
> + //IO(Decode16,0x2F8,0x2F8,0x01,0x08)
> + //IO(Decode16,0x60,0x60,0x01,0x01)
> + //IO(Decode16,0x64,0x64,0x01,0x01)
> +
> + //
> + // FLASH range
> + //
> + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO
> spec
> +
> + }
> + )
> +}
> +
> +//
> +// High Performance Event Timer (HPET)
> +//
> +Device (HPET) {
> + Name (_HID, EisaId ("PNP0103"))
> +
> + Method (_STA, 0, NotSerialized) {
> + If (\HPTE) {
> + Return (0x0F)
> + } Else {
> + Return (0x00)
> + }
> + }
> +
> + Name (CRS0, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
> + })
> +
> + Name (CRS1, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400)
> + })
> +
> + Name (CRS2, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400)
> + })
> +
> + Name (CRS3, ResourceTemplate () {
> + Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400)
> + })
> +
> + //
> + // Owning control method can't be re-entrant, so _CRS must be Serialized
> + //
> + Method (_CRS, 0, Serialized) {
> + Switch (ToInteger(\HPTB)) {
> + Case (0xFED00000) {
> + Return (CRS0)
> + }
> +
> + Case (0xFED01000) {
> + Return (CRS1)
> + }
> +
> + Case (0xFED02000) {
> + Return (CRS2)
> + }
> +
> + Case (0xFED03000) {
> + Return (CRS3)
> + }
> + }
> + Return (CRS0)
> + }
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv
> dimmGpe.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv
> dimmGpe.asi
> new file mode 100644
> index 0000000000..f0c44e67c1
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Nv
> dimmGpe.asi
> @@ -0,0 +1,25 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Method (NNPR, 0) // NTPR == NoTify PRe
> +{
> + External (\_SB.NVDR.NTPR, MethodObj)
> + Store(Package () {}, Local0)
> + if (CondRefOf (\_SB.NVDR.NTPR)) {
> + Store (\_SB.NVDR.NTPR (), Local0) // Local0 == Opaque Package
> + }
> + Return (Local0)
> +}
> +
> +Method (NNDO, 1) // Nvdimm Notify DO
> +{
> + External (\_SB.NVDR.NTDO, MethodObj)
> + if (CondRefOf (\_SB.NVDR.NTDO)) {
> + \_SB.NVDR.NTDO (Arg0)
> + }
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.
> asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.
> asi
> new file mode 100644
> index 0000000000..e2d5fcc78f
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.
> asi
> @@ -0,0 +1,66 @@
> +/** @file
> +
> + @copyright
> + Copyright 2017-2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Scope (\_SB) {
> +
> + Name (XCNT, 0)
> + Name (OSYS, 0) // Global variable for type of OS.
> +
> + Method (_INI) {
> +
> + If (CondRefOf (_OSI)) {
> + If (\_OSI ("Windows 2012")) {
> + Store (13, OSYS) // Windows Server 2012 & Windows 8
> + }
> +
> + If (\_OSI ("Windows 2013")) {
> + Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1
> + }
> +
> + If (\_OSI ("Windows 2015")) {
> + Store (15, OSYS) // Windows 10
> + }
> + //
> + // Check Linux also
> + //
> +
> + If (\_OSI ("FreeBSD")) {
> + Store (2, OSYS)
> + }
> +
> + If (\_OSI ("HP-UX")) {
> + Store (3, OSYS)
> + }
> +
> + If (\_OSI ("OpenVMS")) {
> + Store (4, OSYS)
> + }
> +
> + //
> + // Running WinSvr2012, Win8, or later?
> + //
> + If (LGreaterEqual (\_SB.OSYS, 13)) {
> + //
> + // It is Svr2012 or Win8
> + // Call xHCI device to switch USB ports over
> + // unless it has been done already
> + //
> + If (LEqual (XCNT, 0)) {
> + if(LEqual(DBGM, 0x01)){
> + Store (0x84, IO80)
> + }
> + Increment (XCNT)
> + }
> + } Else {
> + if(LEqual(DBGM, 0x01)){
> + Store (\_SB.OSYS, IO80)
> + }
> + }
> + }
> + } // End Method (_INI)
> +} // End Scope (_SB)
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0010nm.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0010nm.asi
> new file mode 100644
> index 0000000000..9f24076ef5
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0010nm.asi
> @@ -0,0 +1,427 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> + External (DBGM, FieldUnitObj)
> +
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + //
> + // _BBN is ACPI method called by OS to read PCI base bus number for IIO
> stack.
> + //
> + Method(_BBN, 0, NotSerialized)
> + {
> + Return(BB00)
> + }
> +
> + //
> + // _PXM is ACPI method called by OS to read Proximity Domain of IIO
> stack.
> + //
> + Method(_PXM, 0, NotSerialized)
> + {
> + Return(0)
> + }
> +
> + //
> + // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
> + //
> + Method(_SEG, 0, NotSerialized)
> + {
> + Return(SG00)
> + }
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,4,CDW2)
> +
> + //
> + // Fill 3rd capability DWORD only if the count is greater than 2.
> + //
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> +
> + //
> + // Select Native PCIe AER/eDPC handling from OS or Firmware First
> model
> + //
> + If (CondRefOf (\_SB.OSNC))
> + {
> + //in case OS has AER capability.
> + If (LEqual ( And(CTRL, 8), 8)) {
> +
> + //in case OS support multiple segment.
> + If (And (SUPP, 8)) {
> + If (CondRefof (^_SEG))
> + {
> + Store (^_SEG, Local0)
> + } Else {
> + Store (0, Local0)
> + }
> + } Else {
> + Store (0, Local0)
> + }
> +
> + Store (^_BBN, Local1)
> +
> + // if BIOS allows OS take. Do nothing.
> + If (\_SB.OSNC(Local0, Local1, SUPP, CTRL)) {
> +
> + } Else {
> + And (CTRL, Not(0x88), CTRL)
> + }
> + } Else {
> + And (CTRL, Not(0x88), CTRL)
> + }
> + } Else {
> + //
> + //Disable Native PCIe AER/eDPC handling from OS, AER is bit3, eDPC is
> bit7
> + //
> + And (CTRL, Not(0x88), CTRL)
> + }
> +
> + If (Not(And(CDW1,1))) { // Query Flag Clear?
> + //
> + // Disable GPEs for Features granted native control
> + //
> + If (And(CTRL, 0x01)) { // Native Hot plug control granted?
> + if(LEqual(DBGM, 0x01)){
> + Store (0xE3, IO80)
> + }
> + \_SB.PC01.BR1A.OSHP ()
> + \_SB.PC01.BR1B.OSHP ()
> + \_SB.PC01.BR1C.OSHP ()
> + \_SB.PC01.BR1D.OSHP ()
> +
> + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
> + }
> + }
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + if(LEqual(DBGM, 0x01)){
> + Store (0xEE, IO80)
> + }
> + Return(Arg3)
> + }
> + } // End _OSC
> +
> +#include "PchApic.asi"
> +
> +
> +#define RESOURCE_CHUNK1_OFF 0
> +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
> +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
> +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
> +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
> +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
> +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
> +
> +#define PciResourceStart Local0
> +#define PciResourceLen Local1
> +
> + Name(P0RS, ResourceTemplate() {
> + //RESOURCE_CHUNK1_OFF
> + WORDBusNumber( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI
> Platform Driver during POST)
> + ,
> + ,
> + FIX1 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //RESOURCE_CHUNK2_OFF
> + IO( // Consumed resource (CF8-CFF)
> + Decode16,
> + 0x0cf8,
> + 0xcf8,
> + 1,
> + 8
> + )
> +
> + //RESOURCE_CHUNK3_OFF
> + WORDIO( // Consumed-and-produced resource (all I/O below
> CF8)
> + ResourceProducer, // bit 0 of general flags is 0
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode,
> + EntireRange,
> + 0x0000, // Granularity
> + 0x0000, // Min
> + 0x0cf7, // Max
> + 0x0000, // Translation
> + 0x0cf8 // Range Length
> + )
> +
> + //RESOURCE_CHUNK4_OFF
> + WORDIO( // Consumed-and-produced resource (all I/O above
> CFF)
> + ResourceProducer, // bit 0 of general flags is 0
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode,
> + EntireRange,
> + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Translation
> + 0x0001, // Range Length (FIX2 - Patched by ACPI Platform Driver
> during POST)
> + ,
> + ,
> + FIX2 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //RESOURCE_CHUNK5_OFF
> + DWORDMEMORY( // descriptor for video RAM on video card
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode,
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is Fixed
> + Cacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform
> Driver during POST)
> + ,
> + ,
> + FIX5 // Descriptor Name
> + )
> +
> + //RESOURCE_CHUNK6_OFF
> + DWORDMEMORY( // descriptor for Shadow RAM
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode,
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is Fixed
> + Cacheable,
> + ReadWrite,
> + 0x00000000, // Granularity
> + 0x00000000, // Min (calculated dynamically)
> + 0x00000000, // Max (calculated dynamically)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically)
> + ,
> + ,
> + SRAM // DescriptorName populated so iASL doesn't flag 0 value
> fields and no tag as error
> + )
> +/*
> + //RESOURCE_TPM
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity
> + 0xFED40000, // Min (calculated dynamically)
> + 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
> + 0x00000000, // Translation
> + 0x000C0000 // Range Length (calculated dynamically)
> + )
> +*/
> +
> DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCac
> heable,
> + ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000)
> +
> + //
> + // PCI RESOURCE_32bit
> + //
> + DWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver
> during POST)
> + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched
> by ACPI Platform Driver during POST)
> + 0x00000000, // Translation
> + 0x00000000, // Range Length (calculated dynamically) (FIX3 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIX3 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> +
> + //
> + // PCI RESOURCE_64bit
> + //
> + QWORDMemory( // Consumed-and-produced resource(all of
> memory space)
> + ResourceProducer, // bit 0 of general flags is 0
> + PosDecode, // positive Decode
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + NonCacheable,
> + ReadWrite,
> + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform
> Driver during POST)
> + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by
> ACPI Platform Driver during POST)
> + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 -
> Patched by ACPI Platform Driver during POST)
> + 0x00000000000, // Translation
> + 0x00000000000, // Range Length (calculated dynamically) (FIX4 -
> Patched by ACPI Platform Driver during POST)
> + ,
> + ,
> + FIX4 // DescriptorName populated so iASL outputs offset for it
> in a .h file
> + )
> + }) // end of P0RS Buffer
> +
> + OperationRegion(TMEM, PCI_Config, 0x00, 0x100)
> + Field(TMEM, ByteAcc, NoLock, Preserve) {
> + Offset(0x40),
> + , 4,
> + BSEG, 4,
> + PAMS, 48,
> + Offset(0x52),
> + DIM0, 4,
> + DIM1, 4,
> + , 8,
> + DIM2, 4,
> + }
> +
> + Name(MTBL, Package(0x10) {
> + 0x0,
> + 0x20,
> + 0x20,
> + 0x30,
> + 0x40,
> + 0x40,
> + 0x60,
> + 0x80,
> + 0x80,
> + 0x80,
> + 0x80,
> + 0xc0,
> + 0x100,
> + 0x100,
> + 0x100,
> + 0x200
> + })
> +
> + Name(ERNG, Package(0xd) {
> + 0xc0000,
> + 0xc4000,
> + 0xc8000,
> + 0xcc000,
> + 0xd0000,
> + 0xd4000,
> + 0xd8000,
> + 0xdc000,
> + 0xe0000,
> + 0xe4000,
> + 0xe8000,
> + 0xec000,
> + 0xf0000
> + })
> +
> + Name(PAMB, Buffer(0x7) {
> + })
> +
> + Method(EROM, 0x0, NotSerialized) {
> + CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard-
> coded address
> + CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference
> hard-coded address
> + CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard-
> coded address
> + CreateByteField(PAMB, 0x6, BREG)
> + Store(PAMS, PAMB)
> + Store(BSEG, BREG)
> + Store(0x0, RMIN)
> + Store(0x0, RMAX)
> + Store(0x0, RLEN)
> + Store(0x0, Local0)
> + While(LLess(Local0, 0xd))
> + {
> + ShiftRight(Local0, 0x1, Local1)
> + Store(DerefOf(Index(PAMB, Local1, )), Local2)
> + If(And(Local0, 0x1, ))
> + {
> + ShiftRight(Local2, 0x4, Local2)
> + }
> + And(Local2, 0x3, Local2)
> + If(RMIN)
> + {
> + If(Local2)
> + {
> + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
> + If(LEqual(RMAX, 0xf3fff))
> + {
> + Store(0xfffff, RMAX)
> + }
> + Subtract(RMAX, RMIN, RLEN)
> + Increment(RLEN)
> + }
> + Else
> + {
> + Store(0xc, Local0)
> + }
> + }
> + Else
> + {
> + If(Local2)
> + {
> + Store(DerefOf(Index(ERNG, Local0, )), RMIN)
> + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
> + If(LEqual(RMAX, 0xf3fff))
> + {
> + Store(0xfffff, RMAX)
> + }
> + Subtract(RMAX, RMIN, RLEN)
> + Increment(RLEN)
> + }
> + Else
> + {
> + }
> + }
> + Increment(Local0)
> + }
> + }
> +
> + // Current resource template return
> + Method(_CRS, 0x0, NotSerialized) {
> + EROM()
> + Return(P0RS)
> + }
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0610nmEjd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0610nmEjd.asi
> new file mode 100644
> index 0000000000..966cd82640
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 0610nmEjd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 0610 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if PC06 is removed.
> + Name(_EJD,"\\_SB.PC06") // Dependent on PC18
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1210nmEjd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1210nmEjd.asi
> new file mode 100644
> index 0000000000..6c210da62d
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1210nmEjd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if PC12 is removed.
> + Name(_EJD,"\\_SB.PC12") // Dependent on PC18
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1810nmEjd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1810nmEjd.asi
> new file mode 100644
> index 0000000000..7b6aa91cd5
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC
> 1810nmEjd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2018 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if PC18 is removed.
> + Name(_EJD,"\\_SB.PC18") // Dependent on PC18
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pch
> Apic.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pc
> hApic.asi
> new file mode 100644
> index 0000000000..e76063647e
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pc
> hApic.asi
> @@ -0,0 +1,18 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2012 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Device(APIC) {
> + Name (_HID,EISAID("PNP0003")) // APIC resources
> + Name (_CRS, ResourceTemplate() {
> + //
> + // APIC range(0xFEC0_0000 to 0xFECF_FFFF)
> + //
> + Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC
> + }
> + )
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHp.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHp.asi
> new file mode 100644
> index 0000000000..64484e5402
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHp.asi
> @@ -0,0 +1,669 @@
> +/** @file
> +
> + @copyright
> + Copyright 2007 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + External (DBGM, FieldUnitObj)
> +
> + Method (_INI, 0, NotSerialized)
> + {
> + }
> +
> + Name(_HPP, Package(){0x08, 0x40, SERR, PERR})
> +
> + //
> + // begin hotplug code
> + //
> + Name(SHPC, 0x40) // Slot Hot-plug Capable
> +
> + Name(SPDS, 0x040) // Slot Presence Detect State
> +
> + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
> + Name(CCOM, 0x010) // Command Complete
> + Name(SPDC, 0x08) // Slot Presence Detect Changes
> + Name(MRLC, 0x04) // Slot MRL Changed
> + Name(SPFD, 0x02) // Slot Power Fault Detected
> + Name(SABP, 0x01) // Slot Attention Button Pressed
> +
> + Name(SPOF, 0x10) // Slot Power Off
> + Name(SPON, 0x0F) // Slot Power On Mask
> +
> + Name(ALMK, 0x1C) // Slot Atten. LED Mask
> + Name(ALON, 0x01) // Slot Atten. LED On
> + Name(ALBL, 0x02) // Slot Atten LED Blink
> + Name(ALOF, 0x03) // Slot Atten LED Off
> +
> + Name(PLMK, 0x13) // Slot Pwr. LED Mask
> + Name(PLON, 0x04) // Slot Pwr. LED On
> + Name(PLBL, 0x08) // Slot Pwr. LED Blink
> + Name(PLOF, 0x0C) // Slot Pwr. LED Off
> +
> + //;*************************************
> + //; Bit 3 = Presence Detect Event
> + //; Bit 2 = MRL Sensor Event
> + //; Bit 1 = PWR Fault Event
> + //; Bit 0 = Attention Button Event
> + //;*************************************
> + Name(HPEV, 0xF) // Possible interrupt events (all)
> +
> +
> //;********************************************************
> ****************;
> + //; PCIe Slot Capabilities Register
> + //; Bit - 31-5 - Not used
> + //; Bit - 4 - Power Indicator Present.
> + //; Bit - 3 - Attention Indicator Present.
> + //; Bit - 2 - MRL Sensor Present.
> + //; Bit - 1 - Power Controller Present.
> + //; Bit - 0 - Attention Button Present.
> + //;
> + //; PCIe Slot control Register
> + //; Bit - 10 - PWR Control Disable
> + //; Bit - 9:8 - Attn Indicator
> + //; Bit - 7:6 - PWR Indicator
> + //; Bit - 5 - Hot-Plug Interrupt Event Enable
> + //; Bit - 4 - Command Complete Interrupt enable
> + //; Bit - 3 - Presence Detect Changed Interrupt enable
> + //; Bit - 2 - MRL Sensor Changed Interrupt enable
> + //; Bit - 1 - PwrFault Detect Interrupt enable
> + //; Bit - 0 - Attention Button Pressed Interrupt Enable
> + //;
> + //; PCIe Slot Status Registers
> + //; Bit - 6 - Presence Detect State.
> + //; Bit - 5 - MRL Sensor State.
> + //; Bit - 4 - Command Completed.
> + //;
> + //; RWC Status Bits
> + //;
> + //; Bit - 3 - Presence Detect Changed.
> + //; Bit - 2 - MRL Sensor Changed.
> + //; Bit - 1 - Power Fault Detected.
> + //; Bit - 0 - Attention Button Pressed.
> +
> //;********************************************************
> ****************;
> + OperationRegion (PXCP, PCI_Config, IRPC, 0x40)
> + Field (PXCP, ByteAcc, NoLock, Preserve) {
> + Offset (0x10), // Link Control Register
> + , 4,
> + LDIS, 1, // Link Disable bit4.
> + , 11,
> + Offset (0x14), // PCI Slot Capabilities Register
> + ATBP, 1, // Attention Button Present
> + , 1,
> + MRSP, 1, // MRL Sensor Present
> + ATIP, 1, // Attention Indicator Present
> + PWIP, 1, // Power Indicator Present
> + , 14,
> + PSNM, 13, // Physical Slot Number
> + Offset (0x18), // Slot Control Register
> + ABIE, 1, // Attention Button Pressed Interrupt Enable
> + PFIE, 1, // Power Fault Detected Interrupt Enable
> + MSIE, 1, // MRL Sensor Changed Interrupt Enable
> + PDIE, 1, // Presence Detect Changed Interrupt Enable.
> + CCIE, 1, // Command Complete Interrupt Enable.
> + HPIE, 1, // Hot-plug Interrupt Enable.
> + SCTL, 5, // Attn/Power indicator and Power controller.
> + , 5,
> + Offset (0x1A), // Slot Status Register
> + SSTS, 7, // The status bits in Slot Status Reg
> + , 1,
> + Offset (0x20), // Root Status Register
> + , 16,
> + PMES, 1, // PME Status bit 16
> + PMEP, 1, // PME Pending bit 17
> + , 14
> + }
> +
> + //
> + // These Methods replace the bit field definitions in PPA8
> + // that were bit fields within SCTL
> + //
> + Method (ATID, 0) {
> + Return (And (SCTL, 0x03))
> + }
> +
> + Method (PWID, 0) {
> + Return (ShiftRight (And (SCTL, 0x0C), 2))
> + }
> +
> + Method (PWCC, 0) {
> + Return (ShiftRight (And (SCTL, 0x10), 4))
> + }
> +
> + //
> + // These methods replace the bit fields definitions in PPA8
> + // that were bit fields within SSTS
> + //
> + Method (ABPS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x01, SSTS)
> + }
> + Return (And (SSTS, 0x01))
> + }
> +
> + Method (PFDS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x02, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x02), 1))
> + }
> +
> + Method (MSCS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x04, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x04), 2))
> + }
> +
> + Method (PDCS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x08, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x08), 3))
> + }
> +
> + Method (CMCS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x10, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x10), 4))
> + }
> +
> + Method (MSSC, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x20, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x20), 5))
> + }
> +
> + Method (PRDS, 1) {
> + If (LEqual (Arg0, 1)) {
> + Or (SSTS, 0x40, SSTS)
> + }
> + Return (ShiftRight (And (SSTS, 0x40), 6))
> + }
> +
> +
> +
> //;********************************************************
> ****************;
> + //; This OSHP (Operating System Hot Plug) method is provided for each
> HPC
> + //; which is controlled by ACPI. This method disables ACPI access to the
> + //; HPC and restores the normal System Interrupt and Wakeup Signal
> + //; connection.
> +
> //;********************************************************
> ****************;
> + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP
> code.
> + Store(SSTS, Local0) // Clear any status (RW1C)
> + Store(Local0, SSTS) // (use write thru Local to avoid iasl warning
> 'Duplicate value in list ^ (Source is the same as Target)')
> + }
> +
> +
> //;********************************************************
> ****************;
> + //; Hot Plug Controller Command Method
> + //;
> + //; Input: Arg0 - Command to issue
> + //;
> +
> //;********************************************************
> ****************;
> + Method(HPCC,1) {
> + Store(SCTL, Local0) // get current command state
> + Store(0, Local1) // reset the timeout value
> + If(LNotEqual(Arg0, Local0)) { // see if state is different
> + Store(Arg0, SCTL) // Update the Slot Control
> + While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while
> CMD complete bit is not set,
> + // check for timeout to avoid dead loop
> + if(LEqual(DBGM, 0x01)){
> + Store(0xFB, IO80)
> + }
> + Sleep(2) // allow processor time slice
> + Add(Local1, 2, Local1)
> + }
> + CMCS(1) // Clear the command complete status
> + }
> + }
> +
> +
> //;********************************************************
> ****************;
> + //; Attention Indicator Command
> + //;
> + //; Input: Arg0 - Command to issue
> + //; 1 = ON
> + //; 2 = Blink
> + //; 3 = OFF
> +
> //;********************************************************
> ****************;
> + Method(ATCM,1) {
> + Store(SCTL, Local0) // Get Slot Control
> + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
> + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
> + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
> + }
> + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
> + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
> + }
> + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
> + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
> + }
> + HPCC(Local0)
> + }
> +
> +
> //;********************************************************
> ****************;
> + //; Power Indicator Command
> + //;
> + //; Input: Arg0 - Command to issue
> + //; 1 = ON
> + //; 2 = Blink
> + //; 3 = OFF
> +
> //;********************************************************
> ****************;
> + Method(PWCM,1){
> + Store(SCTL, Local0) // Get Slot Control
> + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
> + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
> + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
> + }
> + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
> + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
> + }
> + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
> + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
> + }
> + HPCC(Local0)
> + }
> +
> +
> //;********************************************************
> ****************;
> + //; Power Slot Command
> + //;
> + //; Input: Arg0 - Command to issue
> + //; 1 = Slot Power ON
> + //; 2 = Slot Power Off
> +
> //;********************************************************
> ****************;
> + Method(PWSL,1){
> + Store(SCTL, Local0) // Get Slot Control
> + If(Arg0){ // Power Slot "ON" Arg0 = 1
> + And(Local0, SPON, Local0) // Turns the Power "ON"
> + } Else { // Power Slot "OFF"
> + Or(Local0, SPOF, Local0) // Turns the Power "OFF"
> + }
> + HPCC(Local0)
> + }
> +
> +
> //;********************************************************
> ****************;
> + //; _OST Methods to indicate that the device Eject/insert request is
> + //; pending, OS could not complete it
> + //;
> + //; Input: Arg0 - Value used in Notify to OS
> + //; 0x00 - card insert
> + //; 0x03 - card eject
> + //; Arg1 - status of Notify
> + //; 0 - success
> + //; 0x80 - Ejection not supported by OSPM
> + //; 0x81 - Device in use
> + //; 0x82 - Device Busy
> + //; 0x84 - Ejection in progress-pending
> +
> //;********************************************************
> ****************;
> + Method(_OST,3,Serialized) {
> + Switch(And(Arg0,0xFF)) { // Mask to retain low byte
> + Case(0x03) { // Ejection Request
> + Switch(ToInteger(Arg1)) {
> + Case(Package() {0x80, 0x81, 0x82, 0x83}) {
> + //
> + // Ejection Failure for some reason
> + //
> + If (Lnot(PWCC())) { // if slot is powered
> + PWCM(0x1) // Set PowerIndicator to ON
> + Store(0x1,ABIE) // Set AttnBtn Interrupt ON
> + }
> + }
> + }
> + }
> + }
> + #include "IioPcieEdpcOst.asi"
> + } // End _OST
> +
> + //
> + // _DSM Device Specific Method
> + //
> + // Arg0: UUID Unique function identifier
> + // Arg1: Integer Revision Level
> + // Arg2: Integer Function Index (0 = Return Supported Functions)
> + // Arg3: Package Parameters
> + Method(_DSM, 4, Serialized) {
> + //
> + // Switch based on which unique function identifier was passed in
> + //
> + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
> + //
> + // _DSM Definitions for Latency Tolerance Reporting
> + //
> + // Arguments:
> + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
> + // Arg1: Revision ID: 3
> + // Arg2: Function Index: 0, c, d
> + // Arg3: Empty Package
> + //
> + // Switch by function index
> + //
> + Switch(ToInteger(Arg2)) {
> + //
> + // Function Index:0
> + // Standard query - A bitmask of functions supported
> + //
> + Case (0) {
> + Name(OPTS, Buffer(2) {0, 0})
> + CreateBitField(OPTS, 0, FUN0)
> + CreateBitField(OPTS, 12, FUNC)
> + CreateBitField(OPTS, 13, FUND)
> +
> + Store(1, FUN0)
> + Store(1, FUNC)
> + Store(1, FUND)
> + Return(OPTS)
> + }
> + //
> + // Function Index: C
> + // Downstream Port Containment Hint
> + //
> + Case(12) {
> + Return(1)
> + }
> +
> + //
> + // Function Index: D
> + // Downstream Port Containment Device Location
> + //
> + Case(13) {
> + Name(DLOC, Buffer(2){0, 0})
> + CreateField(DLOC, 0, 3, DFUN)
> + CreateField(DLOC, 3, 5, DDEV)
> + CreateField(DLOC, 8, 8, DBUS)
> + Store(_BBN, DBUS)
> + store(_ADR, Local2)
> + And(Local2, 0xffff, Local3)
> + ShiftRight (Local2, 16, Local4)
> + Store(Local4, DDEV)
> + Store(Local3, DFUN)
> + Return(ToInteger(DLOC))
> + }
> +
> + } // End of switch(Arg2)
> + } // End of if
> + return (Buffer() {0x00})
> + } // End of _DSM
> +
> +
> //;********************************************************
> ****************;
> + //; Eject Control Methods to indicate that the device is hot-ejectable and
> + //; should "eject" the device.
> + //;
> + //;
> +
> //;********************************************************
> ****************;
> + Method(EJ0L){
> + if(LEqual(DBGM, 0x01)){
> + Store(0xFF, IO80)
> + }
> + Store(SCTL, Local0) // Get IIO Port Control state
> + if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid "ON"
> + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
> + Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
> + }
> + HPCC(Local0) // issue command
> +
> + Store(SCTL, Local0) // Get IIO Port Control state
> + Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power
> Off
> + HPCC(Local0)
> +
> + Store(SCTL, Local0) // Get IIO Port Control state
> + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
> + HPCC(Local0)
> +
> + Store(SCTL, Local0) // Get IIO Port Control state
> + Or(Local0, ALOF, Local0) // Set the Attntion LED to Off.
> + HPCC(Local0)
> +
> + } // End of EJ0L
> +
> +
> //;********************************************************
> ****************;
> + //; PM_PME Wake Handler for All Slots
> + //;
> + //; Input: Arg0 - Slot Numnber
> + //;
> +
> //;********************************************************
> ****************;
> + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake
> Event/Interupt (GPI xxh)
> + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
> + If(ABPS(0)) {
> + if(LEqual(DBGM, 0x01)){
> + if(LEqual(DBGM, 0x01)){
> + Store (Arg0, IO80) // Send slot number to Port 80
> + }
> + }
> + ABPS(1) // Clear the interrupt status
> + Sleep(200) // delay 200ms
> + }
> + }
> + Return (0xff) // Indicate that this controller did not interrupt
> + } // End of Method PMEH
> +
> +
> //;********************************************************
> ****************;
> + //; Hot-Plug Handler for All Slots.
> + //;
> + //; Input: Arg0 - Slot Number
> + //;
> +
> //;********************************************************
> ****************;
> + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt
> (GPI xxh)
> + if(LEqual(DBGM, 0x01)){
> + Store(0xFE, IO80)
> + }
> + Sleep(100)
> + Store(0,CCIE) // Disable command interrupt
> + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
> + if(LEqual(DBGM, 0x01)){
> + Store(0xFD, IO80)
> + }
> + Sleep(10)
> + if(LEqual(DBGM, 0x01)){
> + Store (Arg0, IO80) // Send slot number to Port 80
> + }
> + Sleep(10)
> + Store(PPXH(), Local0) // Call Hot plug Interrupt Handler
> + Return(Local0) // Return PPXH information
> + }
> + Else{
> + Return (0xff) // Indicate that this controller did not interrupt
> + }
> + if(LEqual(DBGM, 0x01)){
> + Store(0xFC, IO80)
> + }
> + Sleep(10)
> + } // End of Method HPEH
> +
> +
> //;********************************************************
> ****************;
> + //; Interrut Event Handler
> + //;
> + //;
> +
> //;********************************************************
> ****************;
> + Method(PPXH){ // Hot plug Interrupt Handler
> + //
> + // Check for the Atention Button Press, Slot Empty/Presence, Power
> Controller Control.
> + //
> + Sleep(200) // HW Workaround for AttentionButton Status to
> stabilise
> + If(ABPS(0)) { // Check if Attention Button Pressed
> + If(LNot(PRDS(0))) { // See if nothing installed (no card in slot)
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + PWSL(0x0) // make sure Power is Off
> + PWCM(0x3) // Set Power Indicator to "OFF"
> + //
> + // Check for MRL here and set attn indicator accordingly
> + //
> + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
> + ATCM(0x2) // Set Attention Indicator to "BLINK"
> + } else { // Standby power is off - MRL open
> + ATCM(0x3) // set attention indicator "OFF"
> + }
> + Store(0x0, ABIE) // set Attention Button Interrupt to disable
> + ABPS(1) // Clear the interrupt status
> + Sleep(200) // delay 200ms
> + Return(0xff) // Attn Button pressed without card in slot. Do
> nothing
> + }
> + //
> + // Card is present in slot so....
> + //
> + Store(0x0, ABIE) // set Attention Button Interrupt to disable
> + // Attn Btn Interrupt has to be enabled only after an
> insert oprn
> + ABPS(1) // Clear the interrupt status
> + Sleep(200) // delay 200ms
> + //
> + // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
> + //
> + //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off
> + // PWSL(0x0) // make sure Power is Off
> + // PWCM(0x3) // Set Power Indicator to "OFF"
> + // ATCM(0x2) // Set Attention Indicator to "BLINK"
> + // Return(0xff) // Attn Button pressed with card in slot, but MRL
> open. Do nothing
> + //}
> + //Card Present, if StandbyPwr is ON proceed as below with Eject
> Sequence
> + If(PWCC()) { // Slot not Powered
> + PWCM(0x3) // Set Power Indicator to "OFF"
> + ATCM(0x2) // Set Attention Indicator to "BLINK"
> + Return(0xff) // Attn Button pressed with card in slot, MRL
> closed, Slot not powered. Do nothing
> + } Else { // See if Slot is already Powered
> + PWCM(0x2) // Set power Indicator to BLINK
> + Sleep(600) // Wait 100ms
> + Store(600, Local0) // set 5 second accumulator to 0
> + ABPS(1) // Clear the interrupt status
> + Sleep(200) // delay 200ms
> + While(LNot(ABPS(0))) { // check for someone pressing Attention
> + Sleep(200) // Wait 200ms
> + Add(Local0, 200, Local0)
> + If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing
> attnetion btn
> + ABPS(1) // Clear the interrupt status
> + Sleep(200) // delay 200ms
> + Return (0x3) // continue with Eject request
> + }
> + }
> + PWCM(0x1) // Set power Indicator baCK "ON"
> + ABPS(1) // Clear the Attention status
> + Sleep(200) // delay 200ms
> + Store(0x1, ABIE) // set Attention Button Interrupt to enable
> + Return (0xff) // do nothing and abort
> + }
> + } // End if for the Attention Button Hot Plug Interrupt.
> +
> + If(PFDS(0)) { // Check if Power Fault Detected
> + PFDS(1) // Clear the Power Fault Status
> + PWSL(0x0) // set Power Off
> + PWCM(0x3) // set power indicator to OFF
> + ATCM(0x1) // set attention indicator "ON"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Return(0x03) // Eject request.
> + } // End if for the Power Fault Interrupt.
> +
> + If(MSCS(0)) { // Check interrupt caused by the MRL Sensor
> + MSCS(1) // Clear the MRL Status
> + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
> + If(PRDS(0)) { // Card is Present
> +
> + ATCM(0x3) // Set Attention Indicator to off
> + PWCM(0x2) // Set Power Indicator to Blink
> + Sleep(600) // Wait 100ms
> + Store(600, Local0) // set 5 second accumulator to 0
> + ABPS(1) // Clear the interrupt status
> + While(LNot(ABPS(0))) { // check for someone pressing Attention
> + Sleep(200) // Wait 200ms
> + Add(Local0, 200, Local0)
> + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
> + Store(0x1, ABIE) // Enable Attention button interrupt
> + ATCM(0x3) // set attention indicator "OFF"
> + Store(0x0, LDIS) // Enable the Link associated with PCI-E port
> + PWSL(0x1) // Power the Slot
> + Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
> + // Check for the Power Fault Detection
> + If(LNot(PFDS(0))) { // No Power Fault
> + PWCM(0x1) // Set Power Indicator to "ON"
> + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock
> (GPIO16)
> + // Notify the OS to load the Driver for the card
> + Store(0x00, Local1)
> + Store(0x1, ABIE) // Enable Attention button interrupt
> + } Else { // Power Fault present
> + PWSL(0x0) // set Slot Power Off
> + PWCM(0x3) // set power indicator to OFF
> + ATCM(0x1) // set attention indicator "ON"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E
> port
> + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock
> (GPIO16)
> + Store(0x03, Local1) // Eject request.
> + } // End if for the Slot Power Fault
> + ABPS(1) // Clear the Attention status
> + Sleep(200) // delay 200ms
> + Return(Local1)
> + }
> + }
> + //
> + // someone pressed Attention Button
> + //
> + ABPS(1) // Clear the Attention status
> + Sleep(200) // delay 200ms
> + PWSL(0x0) // Set Slot Power off
> + PWCM(0x3) // Set Power Indicator back to "OFF"
> + ATCM(02) // Set Attention Indicator to "BLINK"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Return(0xff) // leave it off
> + // End of Insert sequence
> + }
> + //MRL is closed, Card is not present
> + PWSL(0x0) // Set Slot Power off
> + PWCM(0x3) // Set Power Indicator back to "OFF"
> + ATCM(02) // Set Attention Indicator to "BLINK"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Return(0xff) // leave it off
> + } Else { // MRL is open i.e Stdby power is turned off
> + If(PRDS(0)) { //card present MRL switched off
> + ATCM(0x2) // Set Attention Indicator to "BLINK"
> + If(Lnot(PWCC())) { // If slot is powered
> + // This event is not supported and someone has opened the MRL and
> dumped the power
> + // on the slot with possible pending transactions. This could hose the
> OS.
> + // Try to Notify the OS to unload the drivers.
> + PWSL(0x0) // Set Slot Power off
> + PWCM(0x3) // Set Power Indicator back to "OFF"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Return(0x03) // Eject request.
> + } Else { // Slot not powered, MRL is opened, card still in slot -
> Eject not fully complete
> + Return(0xFF)
> + }
> + }
> + //no card present and Stdby power switched off, turn AI off
> + ATCM(0x3) // Set Attention Indicator to "OFF"
> + Return(0xff) // leave it off
> + } // End of MRL switch open/close state
> + } // End of MRL Sensor State Change
> +
> + If(PDCS(0)) { // Check if Presence Detect Changed Status
> + PDCS(1) // Clear the Presence Detect Changed Status
> + If(LNot(PRDS(0))) { // Slot is Empty
> + PWSL(0x0) // Set Slot Power "OFF"
> + PWCM(0x3) // set power indicator to "OFF"
> + If(LEqual(MSSC(0),MRLS)) { // If Standby power is on
> + ATCM(0x2) // Set Attention Indicator to "Blink"
> + } else {
> + ATCM(0x3) // Set Attention Indicator to "OFF"
> + }
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Return(0xFF) // Do nothing
> + } Else { // Slot Card is inserted
> + // Irrespective of MRL state, do the following
> + Store(0x0, LDIS) // Enable the Link associated with PCI-E port
> + PWSL(0x1) // Set Slot Power ON
> + Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
> + If(LNot(PFDS(0))) { // No Power Fault
> + PWCM(0x1) // Set Power Indicator to "ON"
> + Store(0x00, Local1)
> + Store(0x1, ABIE) // Enable Attention button interrupt
> + ATCM(0x3) // Set Attention Indicator to "OFF"
> + } Else { // Power Fault present
> + PWSL(0x0) // set Slot Power Off
> + PWCM(0x3) // set power indicator to OFF
> + ATCM(0x1) // set attention indicator "ON"
> + Store(0x1, LDIS) // Disable the Link associated with PCI-E port
> + Store(0x03, Local1) // Eject request.
> + } // End if for the Slot Power Fault
> + ABPS(1) // Clear the Attention status
> + Sleep(200) // delay 200ms
> + Return(Local1)
> + }
> + } // End if for the Presence Detect Changed Hot Plug Interrupt.
> + Return(0xff) // should not get here, but do device check if it does.
> + } // End of method PP5H
> + //
> + // End of hotplug code
> + //
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHpDev.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHpDev.asi
> new file mode 100644
> index 0000000000..ce48d3800a
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eHpDev.asi
> @@ -0,0 +1,53 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Method(SNUM, 0, Serialized) {
> + Store(PSNM, Local0)
> + Return(Local0)
> + }
> +
> + Device(H000) {
> + Name(_ADR, 0x00000000)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H001) {
> + Name(_ADR, 0x00000001)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H002) {
> + Name(_ADR, 0x00000002)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H003) {
> + Name(_ADR, 0x00000003)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H004) {
> + Name(_ADR, 0x00000004)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H005) {
> + Name(_ADR, 0x00000005)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H006) {
> + Name(_ADR, 0x00000006)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> + Device(H007) {
> + Name(_ADR, 0x00000007)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eNonHpDev.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eNonHpDev.asi
> new file mode 100644
> index 0000000000..44872cefd4
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pci
> eNonHpDev.asi
> @@ -0,0 +1,45 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + Method(SNUM, 0, Serialized) {
> + Store(PSNM, Local0)
> + Return(Local0)
> + }
> +
> + Device(H000) {
> + Name(_ADR, 0x00000000)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H001) {
> + Name(_ADR, 0x00000001)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H002) {
> + Name(_ADR, 0x00000002)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H003) {
> + Name(_ADR, 0x00000003)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H004) {
> + Name(_ADR, 0x00000004)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H005) {
> + Name(_ADR, 0x00000005)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H006) {
> + Name(_ADR, 0x00000006)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> + Device(H007) {
> + Name(_ADR, 0x00000007)
> + Method(_SUN, 0) { Return(SNUM) } // Slot User Number
> + }
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tform.asl
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tform.asl
> new file mode 100644
> index 0000000000..bd33a63efc
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tform.asl
> @@ -0,0 +1,91 @@
> +/** @file
> + ACPI DSDT table
> +
> + @copyright
> + Copyright 2011 - 2019 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +//
> +// Port from client
> +//
> +
> +//
> +// Original file line: 91
> +//
> +
> +
> + External (\_SB.OSNC, MethodObj)
> +
> +
> +
> +//
> +// Original file line: 163
> +//
> +
> +Method(ADBG,1,Serialized)
> +{
> + Return(0)
> +}
> +
> +//
> +// Original file line: 1460
> +//
> +Scope (\)
> +{
> + //
> + // Global Name, returns current Interrupt controller mode;
> + // updated from _PIC control method
> + //
> +
> + //
> + // Procedure: GPRW
> + //
> + // Description: Generic Wake up Control Method ("Big brother")
> + // to detect the Max Sleep State available in ASL Name scope
> + // and Return the Package compatible with _PRW format.
> + // Input: Arg0 = bit offset within GPE register space device event will be
> triggered to.
> + // Arg1 = Max Sleep state, device can resume the System from.
> + // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the
> System.
> + // Output: _PRW package
> + //
> + Name(PRWP, Package(){Zero, Zero}) // _PRW Package
> +
> + Method(GPRW, 2)
> + {
> + Store(Arg0, Index(PRWP, 0)) // copy GPE#
> + //
> + // SS1-SS4 - enabled in BIOS Setup Sleep states
> + //
> + Store(ShiftLeft(SS1,1),Local0) // S1 ?
> + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
> + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
> + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
> + //
> + // Local0 has a bit mask of enabled Sx(1 based)
> + // bit mask of enabled in BIOS Setup Sleep states(1 based)
> + //
> + If(And(ShiftLeft(1, Arg1), Local0))
> + {
> + //
> + // Requested wake up value (Arg1) is present in Sx list of available Sleep
> states
> + //
> + Store(Arg1, Index(PRWP, 1)) // copy Sx#
> + }
> + Else
> + {
> + //
> + // Not available -> match Wake up value to the higher Sx state
> + //
> + ShiftRight(Local0, 1, Local0)
> + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
> + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
> + // } Else { // ??? Win2k / XP
> + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
> + // }
> + }
> +
> + Return(PRWP)
> + }
> +}
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformGpe10nm.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformGpe10nm.asi
> new file mode 100644
> index 0000000000..4faa4cbaea
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformGpe10nm.asi
> @@ -0,0 +1,191 @@
> +/** @file
> +
> + @copyright
> + Copyright 2017 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "MaxSocket.h"
> +External(\_SB.WERR, DeviceObj)
> +
> +// General Purpose Event
> +
> +Scope (\_GPE) {
> +
> + // Based on Socket ID to be notified, evaluate appropriate devices.
> + Method(NTFC, 2){
> + If(And(Arg0, 0x01)){
> + Notify(\_SB.SCK0, Arg1)
> + }
> +
> +#if MAX_SOCKET > 1
> + If(And(Arg0, 0x02)){
> + Notify(\_SB.SCK1, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 2
> + If(And(Arg0, 0x04)){
> + Notify(\_SB.SCK2, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 3
> + If(And(Arg0, 0x08)){
> + Notify(\_SB.SCK3, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 4
> + If(And(Arg0, 0x10)){
> + Notify(\_SB.SCK4, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 5
> + If(And(Arg0, 0x20)){
> + Notify(\_SB.SCK5, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 6
> + If(And(Arg0, 0x40)){
> + Notify(\_SB.SCK6, Arg1)
> + }
> +#endif
> +
> +#if MAX_SOCKET > 7
> + If(And(Arg0, 0x80)){
> + Notify(\_SB.SCK7, Arg1)
> + }
> +#endif
> + } //End Method NTFC
> +#if 0
> + Method(NTFM, 2){
> +
> + // Based on Memory Board ID to be notified, evaluate appropriate
> devices.
> + If(And(Arg0, 0x01)){
> + Notify(\_SB.SCK0.M000, Arg1)
> + }
> + If(And(Arg0, 0x02)){
> + Notify(\_SB.SCK0.M001, Arg1)
> + }
> +#if MAX_SOCKET > 1
> + If(And(Arg0, 0x04)){
> + Notify(\_SB.SCK1.M000, Arg1)
> + }
> + If(And(Arg0, 0x08)){
> + Notify(\_SB.SCK1.M001, Arg1)
> + }
> +#endif
> +#if MAX_SOCKET > 2
> + If(And(Arg0, 0x10)){
> + Notify(\_SB.SCK2.M000, Arg1)
> + }
> + If(And(Arg0, 0x20)){
> + Notify(\_SB.SCK2.M001, Arg1)
> + }
> +#endif
> +#if MAX_SOCKET > 3
> + If(And(Arg0, 0x40)){
> + Notify(\_SB.SCK3.M000, Arg1)
> + }
> + If(And(Arg0, 0x80)){
> + Notify(\_SB.SCK3.M001, Arg1)
> + }
> +#endif
> +
> + } // End Method NTFM
> +#endif
> +
> + Method(NTFI, 2){
> +#if MAX_SOCKET > 1
> + If(And(Arg0, 0x01)){
> + Notify(\_SB.PC06, Arg1)
> + Notify(\_SB.PC07, Arg1)
> + Notify(\_SB.PC08, Arg1)
> + Notify(\_SB.PC09, Arg1)
> + Notify(\_SB.PC10, Arg1)
> + Notify(\_SB.PC11, Arg1)
> +
> + }
> +#endif
> +#if MAX_SOCKET > 2
> + If(And(Arg0, 0x02)){
> + Notify(\_SB.PC12, Arg1)
> + Notify(\_SB.PC13, Arg1)
> + Notify(\_SB.PC14, Arg1)
> + Notify(\_SB.PC15, Arg1)
> + Notify(\_SB.PC16, Arg1)
> + Notify(\_SB.PC17, Arg1)
> + }
> +#endif
> +#if MAX_SOCKET > 3
> + If(And(Arg0, 0x04)){
> + Notify(\_SB.PC18, Arg1)
> + Notify(\_SB.PC19, Arg1)
> + Notify(\_SB.PC20, Arg1)
> + Notify(\_SB.PC21, Arg1)
> + Notify(\_SB.PC22, Arg1)
> + Notify(\_SB.PC23, Arg1)
> + }
> +#endif
> + } //End Method NTFI
> +
> + // Tell OS to run thru the new status of this device (Software SCI generated
> from SMM for all Hot plug events)
> + Method (_L62, 0x0, NotSerialized) {
> + if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
> + //NTFM (SCI1, 3)
> + NTFC (SCI2, 3)
> + Store (0, SCI0)
> + } ElseIf (LEqual(SCI0, 1)) { // Device check (OS can still reject online
> request based on resources and capability)
> + NTFC (CPHP, 0)
> + NTFI (IIOP, 0)
> + Store (0, CPHP)
> + Store (0, IIOP)
> + Store (0, SCI0)
> + }
> +
> + #include "NvdimmGpe.asi"
> +
> + // Retrieve leaf and root notification data pre SWGPE clear
> + Store (NNPR (), Local0)
> +
> + Store (0, GPEC)
> +
> + if(LEqual(WSCI, 0x1)) {
> + Store(0, WSCI)
> + if(LEqual(DBGM, 0x01)){
> + Store (0x4A, IO80)
> + }
> + If (CondRefOf (\_SB.WERR)) {
> + Notify (\_SB.WERR, 0x80)
> + }
> + }
> +
> + // Perform NVDIMM leaf and root notifications with notification data
> updated post SWGPE clear
> + NNDO (Local0)
> +
> + ///
> + /// Handle HWP SCI event
> + ///
> + //#include "HwpLvt.asi"
> +
> + //
> + // Handle eDPC SWGPE event
> + //
> + #include "IioPcieEdpcGpe.asi"
> + }
> +
> + // PME supported for Slots, use GPE 9 for PME
> + // Hot plug on all slots for now, change later.
> + // Slot numbers on silk screen might be different than the port number,
> currently use port numbers.
> + //
> + // IIO PCI_E Slot Hotplug GPE Event
> + //
> + Method (_L61, 0, NotSerialized) {
> + #include "IioPcieHotPlugGpeHandler10nm.asl"
> + }// end of _L61 GPE Method
> +
> +}// end of _GPE scope
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformPciTree10nm_EPRP.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformPciTree10nm_EPRP.asi
> new file mode 100644
> index 0000000000..2ad0a32d25
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Pla
> tformPciTree10nm_EPRP.asi
> @@ -0,0 +1,5388 @@
> +/** @file
> + @copyright
> + Copyright 2005 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <MaxSocket.h>
> +
> +#ifndef CONCATENATE2
> +#define CONCATENATE2_(a, b) a ## b
> +#define CONCATENATE2(a, b) CONCATENATE2_(a, b)
> +#endif
> +#ifndef CONCATENATE3
> +#define CONCATENATE3_(a, b, c) a ## b ## c
> +#define CONCATENATE3(a, b, c) CONCATENATE3_(a, b, c)
> +#endif
> +
> +Scope (\_SB) {
> +
> + Name (AR00, Package() {
> + // [IIM0]: IIOMISC on PC00
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [CB0A]: CB3DMA on PC00
> + // [CB0E]: CB3DMA on PC00
> + Package() { 0x0001FFFF, 0, 0, 17 },
> + // [CB0B]: CB3DMA on PC00
> + // [CB0F]: CB3DMA on PC00
> + Package() { 0x0001FFFF, 1, 0, 18 },
> + // [CB0C]: CB3DMA on PC00
> + // [CB0G]: CB3DMA on PC00
> + Package() { 0x0001FFFF, 2, 0, 19 },
> + // [CB0D]: CB3DMA on PC00
> + // [CB0H]: CB3DMA on PC00
> + Package() { 0x0001FFFF, 3, 0, 16 },
> + // [MSM1] MSM
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + // [PMON] PMON MSM
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + // [NRPK]: NorthPeak
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [DMI0]: Legacy PCI Express Port 0 on PC00
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + // [IHC1]: IE HECI #1
> + // [IHC3]: IE HECI #3
> + Package() { 0x0010FFFF, 0, 0, 16 },
> + // [IHC2]: IE HECI #2
> + Package() { 0x0010FFFF, 1, 0, 17 },
> + // [IIDR]: IE IDE-Redirection (IDE-R)
> + Package() { 0x0010FFFF, 2, 0, 18 },
> + // [IMKT]: IE Keyboard and Text (KT) Redirection
> + Package() { 0x0010FFFF, 3, 0, 19 },
> + // [SAT2]: sSATA Host controller on PCH
> + // [MRO0]: MROM 0 function
> + // [MRO1]: MROM 1 function
> + Package() { 0x0011FFFF, 0, 0, 17 },
> + Package() { 0x0011FFFF, 1, 0, 18 },
> + Package() { 0x0011FFFF, 2, 0, 19 },
> + Package() { 0x0011FFFF, 3, 0, 16 },
> + // [XHCI]: xHCI controller 1 on PCH
> + Package() { 0x0014FFFF, 0, 0, 16 },
> + Package() { 0x0014FFFF, 1, 0, 17 },
> + // [TERM]: Thermal Subsystem on PCH
> + Package() { 0x0014FFFF, 2, 0, 18 },
> + Package() { 0x0014FFFF, 3, 0, 19 },
> + // [HEC1]: ME HECI #1 on PCH
> + // [HEC3]: ME HECI #3 on PCH
> + Package() { 0x0016FFFF, 0, 0, 18 },
> + // [HEC2]: ME HECI #2 on PCH
> + Package() { 0x0016FFFF, 1, 0, 19 },
> + // [IDER]: ME IDE redirect on PCH
> + Package() { 0x0016FFFF, 2, 0, 16 },
> + // [MEKT]: MEKT on PCH
> + Package() { 0x0016FFFF, 3, 0, 17 },
> + // [SAT1]: SATA controller 1 on PCH
> + Package() { 0x0017FFFF, 0, 0, 19 },
> + // [RP17]: PCIE PCH Root Port #17
> + Package() { 0x001BFFFF, 0, 0, 19 },
> + // [RP18]: PCIE PCH Root Port #18
> + Package() { 0x001BFFFF, 1, 0, 16 },
> + // [RP19]: PCIE PCH Root Port #19
> + Package() { 0x001BFFFF, 2, 0, 17 },
> + // [RP20]: PCIE PCH Root Port #20
> + Package() { 0x001BFFFF, 3, 0, 18 },
> + // [RP01]: PCIE PCH Root Port #1
> + // [RP05]: PCIE PCH Root Port #5
> + Package() { 0x001CFFFF, 0, 0, 16 },
> + // [RP02]: PCIE PCH Root Port #2
> + // [RP06]: PCIE PCH Root Port #6
> + Package() { 0x001CFFFF, 1, 0, 17 },
> + // [RP03]: PCIE PCH Root Port #3
> + // [RP07]: PCIE PCH Root Port #7
> + Package() { 0x001CFFFF, 2, 0, 18 },
> + // [RP04]: PCIE PCH Root Port #4
> + // [RP08]: PCIE PCH Root Port #8
> + Package() { 0x001CFFFF, 3, 0, 19 },
> + // [RP09]: PCIE PCH Root Port #9
> + // [RP13]: PCIE PCH Root Port #13
> + Package() { 0x001DFFFF, 0, 0, 17 },
> + // [RP10]: PCIE PCH Root Port #10
> + // [RP14]: PCIE PCH Root Port #14
> + Package() { 0x001DFFFF, 1, 0, 18 },
> + // [RP11]: PCIE PCH Root Port #11
> + // [RP15]: PCIE PCH Root Port #15
> + Package() { 0x001DFFFF, 2, 0, 19 },
> + // [RP12]: PCIE PCH Root Port #12
> + // [RP16]: PCIE PCH Root Port #16
> + Package() { 0x001DFFFF, 3, 0, 16 },
> + // [P2SB]: P2SB
> + // [PMC1]: Power Management Controller on PCH
> + // [CAVS]: HD Audio Subsystem Controller on PCH
> + // [SMBS]: SMBus controller on PCH
> + // [GBE1]: GbE Controller on PCH
> + // [TRHB]: Intel Trace Hub on PCH
> + Package() { 0x001FFFFF, 3, 0, 19 },
> + Package() { 0x001FFFFF, 2, 0, 18 },
> + Package() { 0x001FFFFF, 1, 0, 17 },
> + Package() { 0x001FFFFF, 0, 0, 16 },
> + })
> +
> + Name (AR01, Package() {
> + // [SLTH]: PCIE PCH Slot #17
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR02, Package() {
> + // [SLTI]: PCIE PCH Slot #18
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR03, Package() {
> + // [SLTJ]: PCIE PCH Slot #19
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR04, Package() {
> + // [SLTK]: PCIE PCH Slot #20
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR05, Package() {
> + // [SLT1]: PCIE PCH Slot #1
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR06, Package() {
> + // [SLT2]: PCIE PCH Slot #2
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR07, Package() {
> + // [SLT3]: PCIE PCH Slot #3
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR08, Package() {
> + // [SLT4]: PCIE PCH Slot #4
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR09, Package() {
> + // [SLT5]: PCIE PCH Slot #5
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR0A, Package() {
> + // [SLT6]: PCIE PCH Slot #6
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR0B, Package() {
> + // [SLT7]: PCIE PCH Slot #7
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR0C, Package() {
> + // [SLT8]: PCIE PCH Slot #8
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR0D, Package() {
> + // [SLT9]: PCIE PCH Slot #9
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR0E, Package() {
> + // [SLTA]: PCIE PCH Slot #10
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR0F, Package() {
> + // [SLTB]: PCIE PCH Slot #11
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR10, Package() {
> + // [SLTC]: PCIE PCH Slot #12
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR11, Package() {
> + // [SLTD]: PCIE PCH Slot #13
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR12, Package() {
> + // [SLTE]: PCIE PCH Slot #14
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR13, Package() {
> + // [SLTF]: PCIE PCH Slot #15
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR14, Package() {
> + // [SLTG]: PCIE PCH Slot #16
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR15, Package() {
> + // [BR1A]: PCI Express Port 1A on PC01
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [BR1B]: PCI Express Port 1B on PC01
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [BR1C]: PCI Express Port 1C on PC01
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [BR1D]: PCI Express Port 1D on PC01
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR16, Package() {
> + // [SL01]: PCI Express Slot 1 on 1A on PC01
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR17, Package() {
> + // [SL02]: PCI Express Slot 2 on 1B on PC01
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR18, Package() {
> + // [SL03]: PCI Express Slot 3 on 1C on PC01
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR19, Package() {
> + // [SL04]: PCI Express Slot 4 on 1D on PC01
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR1A, Package() {
> + // [BR2A]: PCI Express Port 2A on PC02
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [BR2B]: PCI Express Port 2B on PC02
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [BR2C]: PCI Express Port 2C on PC02
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [BR2D]: PCI Express Port 2D on PC02
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR1B, Package() {
> + // [SL05]: PCI Express Slot 5 on 2A on PC02
> + // [EPCU]: EVA PCIe Uplink
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR1C, Package() {
> + // [VSP0]: EVA Virtual Switch Port 0
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + // [VSP1]: EVA Virtual Switch Port 1
> + Package() { 0x0001FFFF, 0, 0, 19 },
> + // [VSP2]: EVA Virtual Switch Port 2
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + // [VSP3]: EVA Virtual Switch Port 3
> + Package() { 0x0003FFFF, 0, 0, 17 },
> + })
> +
> + Name (AR1D, Package() {
> + // [CPM0]: EVA CPM0
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + })
> +
> + Name (AR1E, Package() {
> + // [CPM1]: EVA CPM1
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + })
> +
> + Name (AR1F, Package() {
> + // [CPM2]: EVA CPM2
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + })
> +
> + Name (AR20, Package() {
> + // [SL06]: PCI Express Slot 6 on 2B on PC02
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR21, Package() {
> + // [SL07]: PCI Express Slot 7 on 2C on PC02
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR22, Package() {
> + // [SL08]: PCI Express Slot 8 on 2D on PC02
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR23, Package() {
> + // [BR3A]: PCI Express Port 3A on PC03
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [BR3B]: PCI Express Port 3B on PC03
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [BR3C]: PCI Express Port 3C on PC03
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [BR3D]: PCI Express Port 3D on PC03
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR24, Package() {
> + // [SL09]: PCI Express Slot 9 on 3A on PC03
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR25, Package() {
> + // [SL0A]: PCI Express Slot 10 on 3B on PC03
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR26, Package() {
> + // [SL0B]: PCI Express Slot 11 on 3C on PC03
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR27, Package() {
> + // [SL0C]: PCI Express Slot 12 on 3D on PC03
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR28, Package() {
> + // [BR4A]: PCI Express Port 4A on PC04
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [BR4B]: PCI Express Port 4B on PC04
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [BR4C]: PCI Express Port 4C on PC04
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [BR4D]: PCI Express Port 4D on PC04
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR29, Package() {
> + // [SL0D]: PCI Express Slot 13 on 4A on PC04
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR2A, Package() {
> + // [SL0E]: PCI Express Slot 14 on 4B on PC04
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR2B, Package() {
> + // [SL0F]: PCI Express Slot 15 on 4C on PC04
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR2C, Package() {
> + // [SL10]: PCI Express Slot 16 on 4D on PC04
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR2D, Package() {
> + // [BR5A]: PCI Express Port 5A on PC05
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [BR5B]: PCI Express Port 5B on PC05
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [BR5C]: PCI Express Port 5C on PC05
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [BR5D]: PCI Express Port 5D on PC05
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR2E, Package() {
> + // [SL11]: PCI Express Slot 17 on 5A on PC05
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR2F, Package() {
> + // [SL12]: PCI Express Slot 18 on 5B on PC05
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR30, Package() {
> + // [SL13]: PCI Express Slot 19 on 5C on PC05
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR31, Package() {
> + // [SL14]: PCI Express Slot 20 on 5D on PC05
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR32, Package() {
> + // [UBX0]: Uncore 0 UBOX Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [UP00]: Uncore 0 Misc 2 UPI 0-7 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [UP01]: Unocre 0 Misc 1 UPI 0-7 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [M2U0]: Uncore 0 M2UPI0 Device
> + Package() { 0x0005FFFF, 0, 0, 16 },
> + Package() { 0x0005FFFF, 1, 0, 17 },
> + Package() { 0x0005FFFF, 2, 0, 18 },
> + Package() { 0x0005FFFF, 3, 0, 19 },
> + // [M2U1]: Uncore 0 M2UPI1 Device
> + Package() { 0x0006FFFF, 0, 0, 16 },
> + Package() { 0x0006FFFF, 1, 0, 17 },
> + Package() { 0x0006FFFF, 2, 0, 18 },
> + Package() { 0x0006FFFF, 3, 0, 19 },
> + // [M2U2]: Uncore 0 M2UPI2 Device
> + Package() { 0x0007FFFF, 0, 0, 16 },
> + Package() { 0x0007FFFF, 1, 0, 17 },
> + Package() { 0x0007FFFF, 2, 0, 18 },
> + Package() { 0x0007FFFF, 3, 0, 19 },
> + // [CSM0]: Uncore 0 CHASIS_SMBUS Devices
> + Package() { 0x000BFFFF, 0, 0, 16 },
> + Package() { 0x000BFFFF, 1, 0, 17 },
> + Package() { 0x000BFFFF, 2, 0, 18 },
> + Package() { 0x000BFFFF, 3, 0, 19 },
> + // [M2M0]: Uncore 0 MS2MEM_SCF_MS2MEM0 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [M2M1]: Uncore 0 MS2MEM_SCF_MS2MEM1 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [MCD0]: Uncore 0 MCDDR0 Device
> + Package() { 0x001AFFFF, 0, 0, 16 },
> + Package() { 0x001AFFFF, 1, 0, 17 },
> + Package() { 0x001AFFFF, 2, 0, 18 },
> + Package() { 0x001AFFFF, 3, 0, 19 },
> + // [MCD1]: Uncore 0 MCDDR1 Device
> + Package() { 0x001BFFFF, 0, 0, 16 },
> + Package() { 0x001BFFFF, 1, 0, 17 },
> + Package() { 0x001BFFFF, 2, 0, 18 },
> + Package() { 0x001BFFFF, 3, 0, 19 },
> + })
> +
> + Name (AR33, Package() {
> + // [CHA0]: Uncore 1 GRP1_CHA0-7 Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [CHA1]: Uncore 1 GRP1_CHA8-15 Device
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // [CHA2]: Uncore 1 GRP1_CHA16-23 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [CHA3]: Uncore 1 GRP1_CHAU24-31 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [CHA4]: Uncore 1 GRP1_CHA32-33 Device
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [CHA5]: Uncore 1 GRP0_CHA0-7 Device
> + Package() { 0x000AFFFF, 0, 0, 16 },
> + Package() { 0x000AFFFF, 1, 0, 17 },
> + Package() { 0x000AFFFF, 2, 0, 18 },
> + Package() { 0x000AFFFF, 3, 0, 19 },
> + // [CHA8]: Uncore 1 GRP0_CHA24-31 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [CHA9]: Uncore 1 GRP0_CHA32-33 Device
> + Package() { 0x000EFFFF, 0, 0, 16 },
> + Package() { 0x000EFFFF, 1, 0, 17 },
> + Package() { 0x000EFFFF, 2, 0, 18 },
> + Package() { 0x000EFFFF, 3, 0, 19 },
> + // [CHA6]: Uncore 1 GRP0_CHA8-15 Device
> + Package() { 0x00B0FFFF, 0, 0, 16 },
> + Package() { 0x00B0FFFF, 1, 0, 17 },
> + Package() { 0x00B0FFFF, 2, 0, 18 },
> + Package() { 0x00B0FFFF, 3, 0, 19 },
> + // [CHA7]: Uncore 1 GRP0_CHA16-23 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [CA00]: Uncore 1 CHAALL0-1 Device
> + Package() { 0x001DFFFF, 0, 0, 16 },
> + Package() { 0x001DFFFF, 1, 0, 17 },
> + Package() { 0x001DFFFF, 2, 0, 18 },
> + Package() { 0x001DFFFF, 3, 0, 19 },
> + // [PUC0]: Uncore 1 CHASIS_PUINT0-7 Device
> + Package() { 0x001EFFFF, 0, 0, 16 },
> + Package() { 0x001EFFFF, 1, 0, 17 },
> + Package() { 0x001EFFFF, 2, 0, 18 },
> + Package() { 0x001EFFFF, 3, 0, 19 },
> + // [GN30]: Uncore 1 Gen3Phy Device
> + Package() { 0x001FFFFF, 0, 0, 16 },
> + Package() { 0x001FFFFF, 1, 0, 17 },
> + Package() { 0x001FFFFF, 2, 0, 18 },
> + Package() { 0x001FFFFF, 3, 0, 19 },
> + })
> +#if MAX_SOCKET > 1
> + Name (AR34, Package() {
> + // [IIM1]: IIOMISC on PC06
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [CB1A]: CB3DMA on PC06
> + // [CB1E]: CB3DMA on PC06
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + // [CB1B]: CB3DMA on PC06
> + // [CB1F]: CB3DMA on PC06
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + // [CB1C]: CB3DMA on PC06
> + // [CB1G]: CB3DMA on PC06
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + // [CB1D]: CB3DMA on PC06
> + // [CB1H]: CB3DMA on PC06
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // NorthPeak
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + })
> +
> + Name (AR35, Package() {
> + // [QR1A]: PCI Express Port 1A on PC07
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [QR1B]: PCI Express Port 1B on PC07
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [QR1C]: PCI Express Port 1C on PC07
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [QR1D]: PCI Express Port 1D on PC07
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR36, Package() {
> + // [SL16]: PCI Express Slot 22 on 1A on PC07
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR37, Package() {
> + // [SL17]: PCI Express Slot 23 on 1B on PC07
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR38, Package() {
> + // [SL18]: PCI Express Slot 24 on 1C on PC07
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR39, Package() {
> + // [SL19]: PCI Express Slot 25 on 1D on PC07
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR3A, Package() {
> + // [QR2A]: PCI Express Port 2A on PC08
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [QR2B]: PCI Express Port 2B on PC08
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [QR2C]: PCI Express Port 2C on PC08
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [QR2D]: PCI Express Port 2D on PC08
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR3B, Package() {
> + // [SL1A]: PCI Express Slot 26 on 2A on PC08
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR3C, Package() {
> + // [SL1B]: PCI Express Slot 27 on 2B on PC08
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR3D, Package() {
> + // [SL1C]: PCI Express Slot 28 on 2C on PC08
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR3E, Package() {
> + // [SL1D]: PCI Express Slot 29 on 2D on PC08
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR3F, Package() {
> + // [QR3A]: PCI Express Port 3A on PC09
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [QR3B]: PCI Express Port 3B on PC09
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [QR3C]: PCI Express Port 3C on PC09
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [QR3D]: PCI Express Port 3D on PC09
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR40, Package() {
> + // [SL1E]: PCI Express Slot 30 on 3A on PC09
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR41, Package() {
> + // [SL1F]: PCI Express Slot 31 on 3B on PC09
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR42, Package() {
> + // [SL20]: PCI Express Slot 32 on 3C on PC09
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR43, Package() {
> + // [SL21]: PCI Express Slot 33 on 3D on PC09
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR44, Package() {
> + // [QR4A]: PCI Express Port 4A on PC10
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [QR4B]: PCI Express Port 4B on PC10
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [QR4C]: PCI Express Port 4C on PC10
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [QR4D]: PCI Express Port 4D on PC10
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR45, Package() {
> + // [SL22]: PCI Express Slot 34 on 4A on PC10
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR46, Package() {
> + // [SL23]: PCI Express Slot 35 on 4B on PC10
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR47, Package() {
> + // [SL24]: PCI Express Slot 36 on 4C on PC10
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR48, Package() {
> + // [SL25]: PCI Express Slot 37 on 4D on PC10
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR49, Package() {
> + // [QR5A]: PCI Express Port 5A on PC11
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [QR5B]: PCI Express Port 5B on PC11
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [QR5C]: PCI Express Port 5C on PC11
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [QR5D]: PCI Express Port 5D on PC11
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR4A, Package() {
> + // [SL26]: PCI Express Slot 38 on 5A on PC11
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR4B, Package() {
> + // [SL27]: PCI Express Slot 39 on 5B on PC11
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR4C, Package() {
> + // [SL28]: PCI Express Slot 40 on 5C on PC11
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR4D, Package() {
> + // [SL29]: PCI Express Slot 41 on 5D on PC11
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR4E, Package() {
> + // [UBX1]: Uncore 2 UBOX Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [UP02]: Uncore 2 Misc 2 UPI 0-7 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [UP03]: Uncore 2 Misc 1 UPI 0-7 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [M2U3]: Uncore 2 M2UPI0 Device
> + Package() { 0x0005FFFF, 0, 0, 16 },
> + Package() { 0x0005FFFF, 1, 0, 17 },
> + Package() { 0x0005FFFF, 2, 0, 18 },
> + Package() { 0x0005FFFF, 3, 0, 19 },
> + // [M2U4]: Uncore 2 M2UPI1 Device
> + Package() { 0x0006FFFF, 0, 0, 16 },
> + Package() { 0x0006FFFF, 1, 0, 17 },
> + Package() { 0x0006FFFF, 2, 0, 18 },
> + Package() { 0x0006FFFF, 3, 0, 19 },
> + // [M2U5]: Uncore 2 M2UPI2 Device
> + Package() { 0x0007FFFF, 0, 0, 16 },
> + Package() { 0x0007FFFF, 1, 0, 17 },
> + Package() { 0x0007FFFF, 2, 0, 18 },
> + Package() { 0x0007FFFF, 3, 0, 19 },
> + // [CSM1]: Uncore 2 CHASIS_SMBUS Devices
> + Package() { 0x000BFFFF, 0, 0, 16 },
> + Package() { 0x000BFFFF, 1, 0, 17 },
> + Package() { 0x000BFFFF, 2, 0, 18 },
> + Package() { 0x000BFFFF, 3, 0, 19 },
> + // [M2M2]: Uncore 2 MS2MEM_SCF_MS2MEM0 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [M2M3]: Uncore 2 MS2MEM_SCF_MS2MEM1 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [MCD2]: Uncore 2 MCDDR0 Device
> + Package() { 0x001AFFFF, 0, 0, 16 },
> + Package() { 0x001AFFFF, 1, 0, 17 },
> + Package() { 0x001AFFFF, 2, 0, 18 },
> + Package() { 0x001AFFFF, 3, 0, 19 },
> + // [MCD3]: Uncore 2 MCDDR1 Device
> + Package() { 0x001BFFFF, 0, 0, 16 },
> + Package() { 0x001BFFFF, 1, 0, 17 },
> + Package() { 0x001BFFFF, 2, 0, 18 },
> + Package() { 0x001BFFFF, 3, 0, 19 },
> + })
> +
> + Name (AR4F, Package() {
> + // [DHA0]: Uncore 3 GRP1_CHA0-7 Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [DHA1]: Uncore 3 GRP1_CHA8-15 Device
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // [DHA2]: Uncore 3 GRP1_CHA16-23 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [DHA3]: Uncore 3 GRP1_CHAU24-31 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [DHA4]: Uncore 3 GRP1_CHA32-33 Device
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [DHA5]: Uncore 3 GRP0_CHA0-7 Device
> + Package() { 0x000AFFFF, 0, 0, 16 },
> + Package() { 0x000AFFFF, 1, 0, 17 },
> + Package() { 0x000AFFFF, 2, 0, 18 },
> + Package() { 0x000AFFFF, 3, 0, 19 },
> + // [DHA8]: Uncore 3 GRP0_CHA24-31 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [DHA9]: Uncore 3 GRP0_CHA32-33 Device
> + Package() { 0x000EFFFF, 0, 0, 16 },
> + Package() { 0x000EFFFF, 1, 0, 17 },
> + Package() { 0x000EFFFF, 2, 0, 18 },
> + Package() { 0x000EFFFF, 3, 0, 19 },
> + // [DHA6]: Uncore 3 GRP0_CHA8-15 Device
> + Package() { 0x00B0FFFF, 0, 0, 16 },
> + Package() { 0x00B0FFFF, 1, 0, 17 },
> + Package() { 0x00B0FFFF, 2, 0, 18 },
> + Package() { 0x00B0FFFF, 3, 0, 19 },
> + // [DHA7]: Uncore 3 GRP0_CHA16-23 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [CA01]: Uncore 3 CHAALL0-1 Device
> + Package() { 0x001DFFFF, 0, 0, 16 },
> + Package() { 0x001DFFFF, 1, 0, 17 },
> + Package() { 0x001DFFFF, 2, 0, 18 },
> + Package() { 0x001DFFFF, 3, 0, 19 },
> + // [PUC1]: Uncore 3 CHASIS_PUINT0-7 Device
> + Package() { 0x001EFFFF, 0, 0, 16 },
> + Package() { 0x001EFFFF, 1, 0, 17 },
> + Package() { 0x001EFFFF, 2, 0, 18 },
> + Package() { 0x001EFFFF, 3, 0, 19 },
> + // [GN31]: Uncore 3 Gen3Phy Device
> + Package() { 0x001FFFFF, 0, 0, 16 },
> + Package() { 0x001FFFFF, 1, 0, 17 },
> + Package() { 0x001FFFFF, 2, 0, 18 },
> + Package() { 0x001FFFFF, 3, 0, 19 },
> + })
> +#endif
> +
> +#if MAX_SOCKET > 2
> + Name (AR50, Package() {
> + // [IIM2]: IIOMISC on PC12
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [CB2A]: CB3DMA on PC12
> + // [CB2E]: CB3DMA on PC12
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + // [CB2B]: CB3DMA on PC12
> + // [CB2F]: CB3DMA on PC12
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + // [CB2C]: CB3DMA on PC12
> + // [CB2G]: CB3DMA on PC12
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + // [CB2D]: CB3DMA on PC12
> + // [CB2H]: CB3DMA on PC12
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // NorthPeak
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + })
> +
> + Name (AR51, Package() {
> + // [RR1A]: PCI Express Port 1A on PC13
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [RR1B]: PCI Express Port 1B on PC13
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [RR1C]: PCI Express Port 1C on PC13
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [RR1D]: PCI Express Port 1D on PC13
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR52, Package() {
> + // [SL2B]: PCI Express Slot 43 on 1A on PC13
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR53, Package() {
> + // [SL2C]: PCI Express Slot 44 on 1B on PC13
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR54, Package() {
> + // [SL2D]: PCI Express Slot 45 on 1C on PC13
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR55, Package() {
> + // [SL2E]: PCI Express Slot 46 on 1D on PC13
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR56, Package() {
> + // [RR2A]: PCI Express Port 2A on PC14
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [RR2B]: PCI Express Port 2B on PC14
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [RR2C]: PCI Express Port 2C on PC14
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [RR2D]: PCI Express Port 2D on PC14
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR57, Package() {
> + // [SL2F]: PCI Express Slot 47 on 2A on PC14
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR58, Package() {
> + // [SL30]: PCI Express Slot 48 on 2B on PC14
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR59, Package() {
> + // [SL31]: PCI Express Slot 49 on 2C on PC14
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR5A, Package() {
> + // [SL32]: PCI Express Slot 50 on 2D on PC14
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR5B, Package() {
> + // [RR3A]: PCI Express Port 3A on PC15
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [RR3B]: PCI Express Port 3B on PC15
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [RR3C]: PCI Express Port 3C on PC15
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [RR3D]: PCI Express Port 3D on PC15
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR5C, Package() {
> + // [SL33]: PCI Express Slot 51 on 3A on PC15
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR5D, Package() {
> + // [SL34]: PCI Express Slot 52 on 3B on PC15
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR5E, Package() {
> + // [SL35]: PCI Express Slot 53 on 3C on PC15
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR5F, Package() {
> + // [SL36]: PCI Express Slot 54 on 3D on PC15
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR60, Package() {
> + // [RR4A]: PCI Express Port 4A on PC16
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [RR4B]: PCI Express Port 4B on PC16
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [RR4C]: PCI Express Port 4C on PC16
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [RR4D]: PCI Express Port 4D on PC16
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR61, Package() {
> + // [SL37]: PCI Express Slot 55 on 4A on PC16
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR62, Package() {
> + // [SL38]: PCI Express Slot 56 on 4B on PC16
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR63, Package() {
> + // [SL39]: PCI Express Slot 57 on 4C on PC16
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR64, Package() {
> + // [SL3A]: PCI Express Slot 58 on 4D on PC16
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR65, Package() {
> + // [RR5A]: PCI Express Port 5A on PC17
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [RR5B]: PCI Express Port 5B on PC17
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [RR5C]: PCI Express Port 5C on PC17
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [RR5D]: PCI Express Port 5D on PC17
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR66, Package() {
> + // [SL3B]: PCI Express Slot 59 on 5A on PC17
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR67, Package() {
> + // [SL3C]: PCI Express Slot 60 on 5B on PC17
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR68, Package() {
> + // [SL3D]: PCI Express Slot 61 on 5C on PC17
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR69, Package() {
> + // [SL3E]: PCI Express Slot 62 on 5D on PC17
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR6A, Package() {
> + // [UBX2]: Uncore 4 UBOX Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [UP04]: Uncore 4 Misc 2 UPI 0-7 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [UP05]: Uncore 4 Misc 1 UPI 0-7 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [M2U6]: Uncore 4 M2UPI Device
> + Package() { 0x0005FFFF, 0, 0, 16 },
> + Package() { 0x0005FFFF, 1, 0, 17 },
> + Package() { 0x0005FFFF, 2, 0, 18 },
> + Package() { 0x0005FFFF, 3, 0, 19 },
> + // [M2U7]: Uncore 4 M2UPI Device
> + Package() { 0x0006FFFF, 0, 0, 16 },
> + Package() { 0x0006FFFF, 1, 0, 17 },
> + Package() { 0x0006FFFF, 2, 0, 18 },
> + Package() { 0x0006FFFF, 3, 0, 19 },
> + // [M2U8]: Uncore 4 M2UPI Device
> + Package() { 0x0007FFFF, 0, 0, 16 },
> + Package() { 0x0007FFFF, 1, 0, 17 },
> + Package() { 0x0007FFFF, 2, 0, 18 },
> + Package() { 0x0007FFFF, 3, 0, 19 },
> + // [CSM2]: Uncore 4 CHASIS_SMBUS Devices
> + Package() { 0x000BFFFF, 0, 0, 16 },
> + Package() { 0x000BFFFF, 1, 0, 17 },
> + Package() { 0x000BFFFF, 2, 0, 18 },
> + Package() { 0x000BFFFF, 3, 0, 19 },
> + // [M2M4]: Uncore 4 MS2MEM_SCF_MS2MEM0 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [M2M5]: Uncore 4 MS2MEM_SCF_MS2MEM1 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [MCD4]: Uncore 4 MCDDR0 Device
> + Package() { 0x001AFFFF, 0, 0, 16 },
> + Package() { 0x001AFFFF, 1, 0, 17 },
> + Package() { 0x001AFFFF, 2, 0, 18 },
> + Package() { 0x001AFFFF, 3, 0, 19 },
> + // [MCD5]: Uncore 4 MCDDR1 Device
> + Package() { 0x001BFFFF, 0, 0, 16 },
> + Package() { 0x001BFFFF, 1, 0, 17 },
> + Package() { 0x001BFFFF, 2, 0, 18 },
> + Package() { 0x001BFFFF, 3, 0, 19 },
> + })
> +
> + Name (AR6B, Package() {
> + // [EHA0]: Uncore 5 GRP1_CHA0-7 Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [EHA1]: Uncore 5 GRP1_CHA8-15 Device
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // [EHA2]: Uncore 5 GRP1_CHA16-23 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [EHA3]: Uncore 5 GRP1_CHAU24-31 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [EHA4]: Uncore 5 GRP1_CHA32-33 Device
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [EHA5]: Uncore 5 GRP0_CHA0-7 Device
> + Package() { 0x000AFFFF, 0, 0, 16 },
> + Package() { 0x000AFFFF, 1, 0, 17 },
> + Package() { 0x000AFFFF, 2, 0, 18 },
> + Package() { 0x000AFFFF, 3, 0, 19 },
> + // [EHA8]: Uncore 5 GRP0_CHA24-31 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [EHA9]: Uncore 5 GRP0_CHA32-33 Device
> + Package() { 0x000EFFFF, 0, 0, 16 },
> + Package() { 0x000EFFFF, 1, 0, 17 },
> + Package() { 0x000EFFFF, 2, 0, 18 },
> + Package() { 0x000EFFFF, 3, 0, 19 },
> + // [EHA6]: Uncore 5 GRP0_CHA8-15 Device
> + Package() { 0x00B0FFFF, 0, 0, 16 },
> + Package() { 0x00B0FFFF, 1, 0, 17 },
> + Package() { 0x00B0FFFF, 2, 0, 18 },
> + Package() { 0x00B0FFFF, 3, 0, 19 },
> + // [EHA7]: Uncore 5 GRP0_CHA16-23 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [CA02]: Uncore 5 CHAALL0-1 Device
> + Package() { 0x001DFFFF, 0, 0, 16 },
> + Package() { 0x001DFFFF, 1, 0, 17 },
> + Package() { 0x001DFFFF, 2, 0, 18 },
> + Package() { 0x001DFFFF, 3, 0, 19 },
> + // [PUC2]: Uncore 5 CHASIS_PUINT0-7 Device
> + Package() { 0x001EFFFF, 0, 0, 16 },
> + Package() { 0x001EFFFF, 1, 0, 17 },
> + Package() { 0x001EFFFF, 2, 0, 18 },
> + Package() { 0x001EFFFF, 3, 0, 19 },
> + // [GN32]: Uncore 5 Gen3Phy Device
> + Package() { 0x001FFFFF, 0, 0, 16 },
> + Package() { 0x001FFFFF, 1, 0, 17 },
> + Package() { 0x001FFFFF, 2, 0, 18 },
> + Package() { 0x001FFFFF, 3, 0, 19 },
> + })
> +#endif
> +
> +#if MAX_SOCKET > 3
> + Name (AR6C, Package() {
> + // [IIM3]: IIOMISC on PC18
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [CB3A]: CB3DMA on PC18
> + // [CB3E]: CB3DMA on PC18
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + // [CB3B]: CB3DMA on PC18
> + // [CB3F]: CB3DMA on PC18
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + // [CB3C]: CB3DMA on PC18
> + // [CB3G]: CB3DMA on PC18
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + // [CB3D]: CB3DMA on PC18
> + // [CB3H]: CB3DMA on PC18
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // NorthPeak
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + })
> +
> + Name (AR6D, Package() {
> + // [SR1A]: PCI Express Port 1A on PC19
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [SR1B]: PCI Express Port 1B on PC19
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [SR1C]: PCI Express Port 1C on PC19
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [SR1D]: PCI Express Port 1D on PC19
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR6E, Package() {
> + // [SL40]: PCI Express Slot 64 on 1A on PC19
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR6F, Package() {
> + // [SL41]: PCI Express Slot 65 on 1B on PC19
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR70, Package() {
> + // [SL42]: PCI Express Slot 66 on 1C on PC19
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR71, Package() {
> + // [SL43]: PCI Express Slot 67 on 1D on PC19
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR72, Package() {
> + // [SR2A]: PCI Express Port 2A on PC20
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [SR2B]: PCI Express Port 2B on PC20
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [SR2C]: PCI Express Port 2C on PC20
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [SR2D]: PCI Express Port 2D on PC20
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR73, Package() {
> + // [SL44]: PCI Express Slot 68 on 2A on PC20
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR74, Package() {
> + // [SL45]: PCI Express Slot 69 on 2B on PC20
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR75, Package() {
> + // [SL46]: PCI Express Slot 70 on 2C on PC20
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR76, Package() {
> + // [SL47]: PCI Express Slot 71 on 2D on PC20
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR77, Package() {
> + // [SR3A]: PCI Express Port 3A on PC21
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [SR3B]: PCI Express Port 3B on PC21
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [SR3C]: PCI Express Port 3C on PC21
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [SR3D]: PCI Express Port 3D on PC21
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR78, Package() {
> + // [SL48]: PCI Express Slot 72 on 3A on PC21
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR79, Package() {
> + // [SL49]: PCI Express Slot 73 on 3B on PC21
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR7A, Package() {
> + // [SL4A]: PCI Express Slot 74 on 3C on PC21
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR7B, Package() {
> + // [SL4B]: PCI Express Slot 75 on 3D on PC21
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR7C, Package() {
> + // [SR4A]: PCI Express Port 4A on PC22
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [SR4B]: PCI Express Port 4B on PC22
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [SR4C]: PCI Express Port 4C on PC22
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [SR4D]: PCI Express Port 4D on PC22
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR7D, Package() {
> + // [SL4C]: PCI Express Slot 76 on 4A on PC22
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR7E, Package() {
> + // [SL4D]: PCI Express Slot 77 on 4B on PC22
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR7F, Package() {
> + // [SL4D]: PCI Express Slot 78 on 4C on PC22
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR80, Package() {
> + // [SL4E]: PCI Express Slot 79 on 4D on PC22
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR81, Package() {
> + // [SR5A]: PCI Express Port 5A on PC23
> + Package() { 0x0002FFFF, 0, 0, 18 },
> + Package() { 0x0002FFFF, 1, 0, 19 },
> + Package() { 0x0002FFFF, 2, 0, 16 },
> + Package() { 0x0002FFFF, 3, 0, 17 },
> + // [SR5B]: PCI Express Port 5B on PC23
> + Package() { 0x0003FFFF, 0, 0, 19 },
> + Package() { 0x0003FFFF, 1, 0, 16 },
> + Package() { 0x0003FFFF, 2, 0, 17 },
> + Package() { 0x0003FFFF, 3, 0, 18 },
> + // [SR5C]: PCI Express Port 5C on PC23
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [SR5D]: PCI Express Port 5D on PC23
> + Package() { 0x0005FFFF, 0, 0, 17 },
> + Package() { 0x0005FFFF, 1, 0, 18 },
> + Package() { 0x0005FFFF, 2, 0, 19 },
> + Package() { 0x0005FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR82, Package() {
> + // [SL4F]: PCI Express Slot 80 on 5A on PC23
> + Package() { 0x0000FFFF, 0, 0, 18 },
> + Package() { 0x0000FFFF, 1, 0, 19 },
> + Package() { 0x0000FFFF, 2, 0, 16 },
> + Package() { 0x0000FFFF, 3, 0, 17 },
> + })
> +
> + Name (AR83, Package() {
> + // [SL50]: PCI Express Slot 81 on 5B on PC23
> + Package() { 0x0000FFFF, 0, 0, 19 },
> + Package() { 0x0000FFFF, 1, 0, 16 },
> + Package() { 0x0000FFFF, 2, 0, 17 },
> + Package() { 0x0000FFFF, 3, 0, 18 },
> + })
> +
> + Name (AR84, Package() {
> + // [SL51]: PCI Express Slot 82 on 5C on PC23
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +
> + Name (AR85, Package() {
> + // [SL52]: PCI Express Slot 83 on 5D on PC23
> + Package() { 0x0000FFFF, 0, 0, 17 },
> + Package() { 0x0000FFFF, 1, 0, 18 },
> + Package() { 0x0000FFFF, 2, 0, 19 },
> + Package() { 0x0000FFFF, 3, 0, 16 },
> + })
> +
> + Name (AR86, Package() {
> + // [UBX3]: Uncore 6 UBOX Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [UP06]: Uncore 6 Misc 2 UPI 0-7 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [UP07]: Uncore 6 Misc 1 UPI 0-7 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [M2U9]: Uncore 6 M2UPI0 Device
> + Package() { 0x0005FFFF, 0, 0, 16 },
> + Package() { 0x0005FFFF, 1, 0, 17 },
> + Package() { 0x0005FFFF, 2, 0, 18 },
> + Package() { 0x0005FFFF, 3, 0, 19 },
> + // [M2UA]: Uncore 6 M2UPI1 Device
> + Package() { 0x0006FFFF, 0, 0, 16 },
> + Package() { 0x0006FFFF, 1, 0, 17 },
> + Package() { 0x0006FFFF, 2, 0, 18 },
> + Package() { 0x0006FFFF, 3, 0, 19 },
> + // [M2UB]: Uncore 6 M2UPI2 Device
> + Package() { 0x0007FFFF, 0, 0, 16 },
> + Package() { 0x0007FFFF, 1, 0, 17 },
> + Package() { 0x0007FFFF, 2, 0, 18 },
> + Package() { 0x0007FFFF, 3, 0, 19 },
> + // [CSM3]: Uncore 6 CHASIS_SMBUS Devices
> + Package() { 0x000BFFFF, 0, 0, 16 },
> + Package() { 0x000BFFFF, 1, 0, 17 },
> + Package() { 0x000BFFFF, 2, 0, 18 },
> + Package() { 0x000BFFFF, 3, 0, 19 },
> + // [M2M6]: Uncore 6 MS2MEM_SCF_MS2MEM0 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [M2M7]: Uncore 6 MS2MEM_SCF_MS2MEM1 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [MCD6]: Uncore 6 MCDDR0 Device
> + Package() { 0x001AFFFF, 0, 0, 16 },
> + Package() { 0x001AFFFF, 1, 0, 17 },
> + Package() { 0x001AFFFF, 2, 0, 18 },
> + Package() { 0x001AFFFF, 3, 0, 19 },
> + // [MCD7]: Uncore 6 MCDDR1 Device
> + Package() { 0x001BFFFF, 0, 0, 16 },
> + Package() { 0x001BFFFF, 1, 0, 17 },
> + Package() { 0x001BFFFF, 2, 0, 18 },
> + Package() { 0x001BFFFF, 3, 0, 19 },
> + })
> +
> + Name (AR87, Package() {
> + // [FHA0]: Uncore 7 GRP1_CHA0-7 Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + // [FHA1]: Uncore 7 GRP1_CHA8-15 Device
> + Package() { 0x0001FFFF, 0, 0, 16 },
> + Package() { 0x0001FFFF, 1, 0, 17 },
> + Package() { 0x0001FFFF, 2, 0, 18 },
> + Package() { 0x0001FFFF, 3, 0, 19 },
> + // [FHA2]: Uncore 7 GRP1_CHA16-23 Device
> + Package() { 0x0002FFFF, 0, 0, 16 },
> + Package() { 0x0002FFFF, 1, 0, 17 },
> + Package() { 0x0002FFFF, 2, 0, 18 },
> + Package() { 0x0002FFFF, 3, 0, 19 },
> + // [FHA3]: Uncore 7 GRP1_CHAU24-31 Device
> + Package() { 0x0003FFFF, 0, 0, 16 },
> + Package() { 0x0003FFFF, 1, 0, 17 },
> + Package() { 0x0003FFFF, 2, 0, 18 },
> + Package() { 0x0003FFFF, 3, 0, 19 },
> + // [FHA4]: Uncore 7 GRP1_CHA32-33 Device
> + Package() { 0x0004FFFF, 0, 0, 16 },
> + Package() { 0x0004FFFF, 1, 0, 17 },
> + Package() { 0x0004FFFF, 2, 0, 18 },
> + Package() { 0x0004FFFF, 3, 0, 19 },
> + // [FHA5]: Uncore 7 GRP0_CHA0-7 Device
> + Package() { 0x000AFFFF, 0, 0, 16 },
> + Package() { 0x000AFFFF, 1, 0, 17 },
> + Package() { 0x000AFFFF, 2, 0, 18 },
> + Package() { 0x000AFFFF, 3, 0, 19 },
> + // [FHA8]: Uncore 7 GRP0_CHA24-31 Device
> + Package() { 0x000DFFFF, 0, 0, 16 },
> + Package() { 0x000DFFFF, 1, 0, 17 },
> + Package() { 0x000DFFFF, 2, 0, 18 },
> + Package() { 0x000DFFFF, 3, 0, 19 },
> + // [FHA9]: Uncore 7 GRP0_CHA32-33 Device
> + Package() { 0x000EFFFF, 0, 0, 16 },
> + Package() { 0x000EFFFF, 1, 0, 17 },
> + Package() { 0x000EFFFF, 2, 0, 18 },
> + Package() { 0x000EFFFF, 3, 0, 19 },
> + // [FHA6]: Uncore 7 GRP0_CHA8-15 Device
> + Package() { 0x00B0FFFF, 0, 0, 16 },
> + Package() { 0x00B0FFFF, 1, 0, 17 },
> + Package() { 0x00B0FFFF, 2, 0, 18 },
> + Package() { 0x00B0FFFF, 3, 0, 19 },
> + // [FHA7]: Uncore 7 GRP0_CHA16-23 Device
> + Package() { 0x000CFFFF, 0, 0, 16 },
> + Package() { 0x000CFFFF, 1, 0, 17 },
> + Package() { 0x000CFFFF, 2, 0, 18 },
> + Package() { 0x000CFFFF, 3, 0, 19 },
> + // [CA03]: Uncore 7 CHAALL0-1 Device
> + Package() { 0x001DFFFF, 0, 0, 16 },
> + Package() { 0x001DFFFF, 1, 0, 17 },
> + Package() { 0x001DFFFF, 2, 0, 18 },
> + Package() { 0x001DFFFF, 3, 0, 19 },
> + // [PUC3]: Uncore 7 CHASIS_PUINT0-7 Device
> + Package() { 0x001EFFFF, 0, 0, 16 },
> + Package() { 0x001EFFFF, 1, 0, 17 },
> + Package() { 0x001EFFFF, 2, 0, 18 },
> + Package() { 0x001EFFFF, 3, 0, 19 },
> + // [GN33]: Uncore 7 Gen3Phy Device
> + Package() { 0x001FFFFF, 0, 0, 16 },
> + Package() { 0x001FFFFF, 1, 0, 17 },
> + Package() { 0x001FFFFF, 2, 0, 18 },
> + Package() { 0x001FFFFF, 3, 0, 19 },
> + })
> +#endif
> + Name (AR88, Package() {
> + // [FPG0]: FPGA Device
> + Package() { 0x0000FFFF, 0, 0, 16 },
> + })
> +
> +#if MAX_SOCKET > 1
> + Name (AR89, Package() {
> + // [FPG1]: FPGA Device
> + Package() { 0x0000FFFF, 1, 0, 17 },
> + })
> +#endif
> +
> +#if MAX_SOCKET > 2
> + Name (AR8A, Package() {
> + // [FPG2]: FPGA Device
> + Package() { 0x0000FFFF, 2, 0, 18 },
> + })
> +#endif
> +
> +#if MAX_SOCKET > 3
> + Name (AR8B, Package() {
> + // [FPG3]: FPGA Device
> + Package() { 0x0000FFFF, 3, 0, 19 },
> + })
> +#endif
> + //
> + // Socket 0 Root bridge (Stack 0)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 0
> + Device (PC00) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x00)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR00)
> + }
> +
> + #include "PC0010nm.asi"
> +
> + // IIOMISC on PC00
> + Device (IIM0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0A) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0B) {
> + Name (_ADR, 0x00010001)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0C) {
> + Name (_ADR, 0x00010002)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0D) {
> + Name (_ADR, 0x00010003)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0E) {
> + Name (_ADR, 0x00010004)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0F) {
> + Name (_ADR, 0x00010005)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0G) {
> + Name (_ADR, 0x00010006)
> + }
> +
> + // CB3DMA on PC00
> + Device (CB0H) {
> + Name (_ADR, 0x00010007)
> + }
> +
> + // MSM on PC00
> + Device (MSM1) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // PMON MSM on PC00
> + Device (PMON) {
> + Name (_ADR, 0x00020001)
> + }
> +
> + // NorthPeak on PC00
> + Device (NRPK) {
> + Name (_ADR, 0x00020004)
> + }
> +
> + // Legacy PCI Express Port 0 on PC00
> + Device (DMI0) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // IE HECI #1
> + Device (IHC1) {
> + Name (_ADR, 0x00100000)
> + }
> +
> + // IE HECI #2
> + Device (IHC2) {
> + Name (_ADR, 0x00100001)
> + }
> +
> + // IE IDE-Redirection (IDE-R)
> + Device (IIDR) {
> + Name (_ADR, 0x00100002)
> + }
> +
> + // IE Keyboard and Text (KT) Redirection
> + Device (IMKT) {
> + Name (_ADR, 0x00100003)
> + }
> +
> + // IE HECI #3
> + Device (IHC3) {
> + Name (_ADR, 0x00100004)
> + }
> +
> + // MROM 0 function function
> + Device (MRO0) {
> + Name (_ADR, 0x00110000)
> + }
> +
> + // MROM 1 function function
> + Device (MRO1) {
> + Name (_ADR, 0x00110001)
> + }
> +
> + // sSATA Host controller on PCH
> + Device (SAT2) {
> + Name (_ADR, 0x00110005)
> + }
> +
> + // xHCI controller 1 on PCH
> + Device (XHCI) {
> + Name (_ADR, 0x00140000)
> + }
> +
> + // Thermal Subsystem on PCH
> + Device (TERM) {
> + Name (_ADR, 0x00140002)
> + }
> +
> + // ME HECI #1 on PCH
> + Device (HEC1) {
> + Name (_ADR, 0x00160000)
> + }
> +
> + // ME HECI #2 on PCH
> + Device (HEC2) {
> + Name (_ADR, 0x00160001)
> + }
> +
> + // ME IDE redirect on PCH
> + Device (IDER) {
> + Name (_ADR, 0x00160002)
> + }
> +
> + // MEKT on PCH
> + Device (MEKT) {
> + Name (_ADR, 0x00160003)
> + }
> +
> + // ME HECI #3 on PCH
> + Device (HEC3) {
> + Name (_ADR, 0x00160004)
> + }
> +
> + // SATA controller 1 on PCH
> + Device (SAT1) {
> + Name (_ADR, 0x00170000)
> + }
> +
> + // PCIE PCH Root Port #17
> + Device (RP17) {
> + #include "RP17_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR01)
> + }
> +
> + // PCIE PCH Slot #17
> + Device (SLTH) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #18
> + Device (RP18) {
> + #include "RP18_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR02)
> + }
> +
> + // PCIE PCH Slot #18
> + Device (SLTI) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #19
> + Device (RP19) {
> + #include "RP19_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR03)
> + }
> +
> + // PCIE PCH Slot #19
> + Device (SLTJ) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #20
> + Device (RP20) {
> + #include "RP20_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR04)
> + }
> +
> + // PCIE PCH Slot #20
> + Device (SLTK) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #1
> + Device (RP01) {
> + #include "RP01_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR05)
> + }
> + }
> +
> + // PCIE PCH Root Port #2
> + Device (RP02) {
> + #include "RP02_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR06)
> + }
> + }
> +
> + // PCIE PCH Root Port #3
> + Device (RP03) {
> + #include "RP03_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR07)
> + }
> + }
> +
> + // PCIE PCH Root Port #4
> + Device (RP04) {
> + #include "RP04_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR08)
> + }
> + }
> +
> + // PCIE PCH Root Port #5
> + Device (RP05) {
> + #include "RP05_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR09)
> + }
> + }
> +
> + // PCIE PCH Root Port #6
> + Device (RP06) {
> + #include "RP06_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0A)
> + }
> + }
> +
> + // PCIE PCH Root Port #7
> + Device (RP07) {
> + #include "RP07_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0B)
> + }
> + }
> +
> + // PCIE PCH Root Port #8
> + Device (RP08) {
> + #include "RP08_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0C)
> + }
> + }
> +
> + // PCIE PCH Root Port #9
> + Device (RP09) {
> + #include "RP09_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0D)
> + }
> +
> + // PCIE PCH Slot #9
> + Device (SLT9) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #10
> + Device (RP10) {
> + #include "RP10_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0E)
> + }
> +
> + // PCIE PCH Slot #10
> + Device (SLTA) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #11
> + Device (RP11) {
> + #include "RP11_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR0F)
> + }
> +
> + // PCIE PCH Slot #11
> + Device (SLTB) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #12
> + Device (RP12) {
> + #include "RP12_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR10)
> + }
> +
> + // PCIE PCH Slot #12
> + Device (SLTC) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #13
> + Device (RP13) {
> + #include "RP13_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR11)
> + }
> +
> + // PCIE PCH Slot #13
> + Device (SLTD) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #14
> + Device (RP14) {
> + #include "RP14_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR12)
> + }
> +
> + // PCIE PCH Slot #14
> + Device (SLTE) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #15
> + Device (RP15) {
> + #include "RP15_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR13)
> + }
> +
> + // PCIE PCH Slot #15
> + Device (SLTF) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // PCIE PCH Root Port #16
> + Device (RP16) {
> + #include "RP16_ADR.asl"
> + Method (_PRT, 0) {
> +
> + Return (AR14)
> + }
> +
> + // PCIE PCH Slot #16
> + Device (SLTG) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // ISA Bridge on PCH
> + Device (LPC0) {
> + Name (_ADR, 0x001F0000)
> +
> + #include "Mother.asi"
> + }
> +
> + // P2SB
> + Device (P2SB) {
> + Name (_ADR, 0x001F0001)
> + }
> +
> + // Power Management Controller on PCH
> + Device (PMC1) {
> + Name (_ADR, 0x001F0002)
> + }
> +
> + // HD Audio Subsystem Controller on PCH
> + Device (CAVS) {
> + Name (_ADR, 0x001F0003)
> + }
> +
> + // SMBus controller on PCH
> + Device (SMBS) {
> + Name (_ADR, 0x001F0004)
> + }
> +
> + // SPI controller on PCH
> + Device (SPIC) {
> + Name (_ADR, 0x001F0005)
> + }
> +
> + // GbE Controller on PCH
> + Device (GBE1) {
> + Name (_ADR, 0x001F0006)
> + }
> +
> + // Intel Trace Hub on PCH
> + Device (TRHB) {
> + Name (_ADR, 0x001F0007)
> + }
> + }
> +
> + // Socket 0 Root bridge (Stack 1)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 1
> + Device (PC01) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x01)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR15)
> + }
> +
> + #include "IioRootBridge.asi"
> +
> + // PCI Express Port 1A on PC01
> + Device (BR1A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR16)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 1B on PC01
> + Device (BR1B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR17)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 1C on PC01
> + Device (BR1C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR18)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 1D on PC01
> + Device (BR1D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR19)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> + }
> +
> + // Socket 0 Root bridge (Stack 2)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 2
> + Device (PC02) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x02)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR1A)
> + }
> +
> + #include "IioRootBridge.asi"
> +
> + // PCI Express Port 2A on PC02
> + Device (BR2A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR1B)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> +
> + // EVA PCIe Uplink
> + Device (EPCU) {
> + Name (_ADR, 0x00000000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x0B, 0x00})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR1C)
> + }
> +
> + // EVA Virtual Switch Port 0
> + Device (VSP0) {
> + Name (_ADR, 0x00000000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x0B, 0x00})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR1D)
> + }
> +
> + // EVA CPM0
> + Device (CPM0) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // EVA Virtual Switch Port 1
> + Device (VSP1) {
> + Name (_ADR, 0x00010000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x0B, 0x00})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR1E)
> + }
> +
> + // EVA CPM1
> + Device (CPM1) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // EVA Virtual Switch Port 2
> + Device (VSP2) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x0B, 0x00})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR1F)
> + }
> +
> + // EVA CPM2
> + Device (CPM2) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +
> + // EVA Virtual Switch Port 3
> + Device (VSP3) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x0B, 0x00})
> + }
> + }
> + }
> + }
> +
> + // PCI Express Port 2B on PC02
> + Device (BR2B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR20)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 2C on PC02
> + Device (BR2C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR21)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 2D on PC02
> + Device (BR2D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR22)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> + }
> +
> + // Socket 0 Root bridge (Stack 3)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 3
> + Device (PC03) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x03)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR23)
> + }
> +
> + #include "IioRootBridge.asi"
> +
> + // PCI Express Port 3A on PC03
> + Device (BR3A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR24)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 3B on PC03
> + Device (BR3B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR25)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 3C on PC03
> + Device (BR3C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR26)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 3D on PC03
> + Device (BR3D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR27)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> + }
> +
> + // Socket 0 Root bridge (Stack 4)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 4
> + Device (PC04) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x04)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR28)
> + }
> +
> + #include "IioRootBridge.asi"
> +
> + // PCI Express Port 4A on PC04
> + Device (BR4A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR29)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + }
> +
> + // PCI Express Port 4B on PC04
> + Device (BR4B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR2A)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 4C on PC04
> + Device (BR4C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR2B)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 4D on PC04
> + Device (BR4D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR2C)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> + }
> +
> + // Socket 0 Root bridge (Stack 5)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 5
> + Device (PC05) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x05)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR2D)
> + }
> +
> + #include "IioRootBridge.asi"
> +
> + // PCI Express Port 5A on PC05
> + Device (BR5A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR2E)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 5B on PC05
> + Device (BR5B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR2F)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 5C on PC05
> + Device (BR5C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR30)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> +
> + // PCI Express Port 5D on PC05
> + Device (BR5D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR31)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieNonHpDev.asi"
> + }
> + }
> +
> + // Socket 0 Uncore 0
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 6
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x32)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR32)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 0 UBOX Device
> + Device (UBX0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 0 Misc 2 UPI 0-7 Device
> + Device (UP00) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Unocre 0 Misc 1 UPI 0-7 Device
> + Device (UP01) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 0 M2UPI0 Device
> + Device (M2U0) {
> + Name (_ADR, 0x00050000)
> + }
> +
> + // Uncore 0 M2UPI1 Device
> + Device (M2U1) {
> + Name (_ADR, 0x00060000)
> + }
> +
> + // Uncore 0 M2UPI2 Device
> + Device (M2U2) {
> + Name (_ADR, 0x00070000)
> + }
> +
> + // Uncore 0 CHASIS_SMBUS Devices
> + Device (CSM0) {
> + Name (_ADR, 0x000B0000)
> + }
> +
> + // Uncore 0 MS2MEM_SCF_MS2MEM0 Device
> + Device (M2M0) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 0 MS2MEM_SCF_MS2MEM1 Device
> + Device (M2M1) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 0 MCDDR0 Device
> + Device (MCD0) {
> + Name (_ADR, 0x001A0000)
> + }
> +
> + // Uncore 0 MCDDR1 Device
> + Device (MCD1) {
> + Name (_ADR, 0x001B0000)
> + }
> + }
> +
> + // Socket 0 Uncore 1
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 0
> +#define STACK 7
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x33)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR33)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 1 GRP1_CHA0-7 Device
> + Device (CHA0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 1 GRP1_CHA8-15 Device
> + Device (CHA1) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // Uncore 1 GRP1_CHA16-23 Device
> + Device (CHA2) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 1 GRP1_CHAU24-31 Device
> + Device (CHA3) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 1 GRP1_CHA32-33 Device
> + Device (CHA4) {
> + Name (_ADR, 0x00040000)
> + }
> +
> + // Uncore 1 GRP0_CHA0-7 Device
> + Device (CHA5) {
> + Name (_ADR, 0x000A0000)
> + }
> +
> + // Uncore 1 GRP0_CHA24-31 Device
> + Device (CHA8) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 1 GRP0_CHA32-33 Device
> + Device (CHA9) {
> + Name (_ADR, 0x000E0000)
> + }
> +
> + // Uncore 1 GRP0_CHA8-15 Device
> + Device (CHA6) {
> + Name (_ADR, 0x00B00000)
> + }
> +
> + // Uncore 1 GRP0_CHA16-23 Device
> + Device (CHA7) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 1 CHAALL0-1 Device
> + Device (CA00) {
> + Name (_ADR, 0x001D0000)
> + }
> +
> + // Uncore 1 CHASIS_PUINT0-7 Device
> + Device (PUC0) {
> + Name (_ADR, 0x001E0000)
> + }
> +
> + // Uncore 1 Gen3Phy Device
> + Device (GN30) {
> + Name (_ADR, 0x001F0000)
> + }
> + }
> +
> +#if MAX_SOCKET > 1
> + //
> + // Socket 1 Root bridge (Stack 0)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 0
> + Device (PC06) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x06)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR34)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // IIOMISC on PC06
> + Device (IIM1) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1A) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1B) {
> + Name (_ADR, 0x00010001)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1C) {
> + Name (_ADR, 0x00010002)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1D) {
> + Name (_ADR, 0x00010003)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1E) {
> + Name (_ADR, 0x00010004)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1F) {
> + Name (_ADR, 0x00010005)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1G) {
> + Name (_ADR, 0x00010006)
> + }
> +
> + // CB3DMA on PC06
> + Device (CB1H) {
> + Name (_ADR, 0x00010007)
> + }
> + }
> +
> + // Socket 1 Root bridge (Stack 1)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 1
> + Device (PC07) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x07)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR35)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // PCI Express Port 1A on PC07
> + Device (QR1A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR36)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 1B on PC07
> + Device (QR1B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR37)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 1C on PC07
> + Device (QR1C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR38)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 1D on PC07
> + Device (QR1D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR39)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> + }
> +
> + // Socket 1 Root bridge (Stack 2)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 2
> + Device (PC08) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x08)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR3A)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // PCI Express Port 2A on PC08
> + Device (QR2A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR3B)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 2B on PC08
> + Device (QR2B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR3C)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 2C on PC08
> + Device (QR2C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR3D)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 2D on PC08
> + Device (QR2D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR3E)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> + }
> +
> + // Socket 1 Root bridge (Stack 3)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 3
> + Device (PC09) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x09)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR3F)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // PCI Express Port 3A on PC09
> + Device (QR3A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR40)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 3B on PC09
> + Device (QR3B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR41)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 3C on PC09
> + Device (QR3C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR42)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 3D on PC09
> + Device (QR3D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR43)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> + }
> +
> + // Socket 1 Root bridge (Stack 4)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 4
> + Device (PC10) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0A)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR44)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // PCI Express Port 4A on PC10
> + Device (QR4A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR45)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 4B on PC10
> + Device (QR4B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR46)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 4C on PC10
> + Device (QR4C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR47)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 4D on PC10
> + Device (QR4D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR48)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> + }
> +
> + // Socket 1 Root bridge (Stack 5)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 5
> + Device (PC11) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0B)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR49)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck1Ejd.asi"
> +
> + // PCI Express Port 5A on PC11
> + Device (QR5A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR4A)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 5B on PC11
> + Device (QR5B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR4B)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 5C on PC11
> + Device (QR5C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR4C)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> +
> + // PCI Express Port 5D on PC11
> + Device (QR5D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR4D)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC0610nmEjd.asi"
> + }
> + }
> +
> + // Socket 1 Uncore 0
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 6
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x34)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR4E)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 2 UBOX Device
> + Device (UBX1) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 2 Misc 2 UPI 0-7 Device
> + Device (UP02) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 2 Misc 1 UPI 0-7 Device
> + Device (UP03) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 2 M2UPI0 Device
> + Device (M2U3) {
> + Name (_ADR, 0x00050000)
> + }
> +
> + // Uncore 2 M2UPI1 Device
> + Device (M2U4) {
> + Name (_ADR, 0x00060000)
> + }
> +
> + // Uncore 2 M2UPI2 Device
> + Device (M2U5) {
> + Name (_ADR, 0x00070000)
> + }
> +
> + // Uncore 2 CHASIS_SMBUS Devices
> + Device (CSM1) {
> + Name (_ADR, 0x000B0000)
> + }
> +
> + // Uncore 2 MS2MEM_SCF_MS2MEM0 Device
> + Device (M2M2) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 2 MS2MEM_SCF_MS2MEM1 Device
> + Device (M2M3) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 2 MCDDR0 Device
> + Device (MCD2) {
> + Name (_ADR, 0x001A0000)
> + }
> +
> + // Uncore 2 MCDDR1 Device
> + Device (MCD3) {
> + Name (_ADR, 0x001B0000)
> + }
> + }
> +
> + // Socket 1 Uncore 1
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 1
> +#define STACK 7
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x35)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR4F)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 3 GRP1_CHA0-7 Device
> + Device (DHA0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 3 GRP1_CHA8-15 Device
> + Device (DHA1) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // Uncore 3 GRP1_CHA16-23 Device
> + Device (DHA2) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 3 GRP1_CHAU24-31 Device
> + Device (DHA3) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 3 GRP1_CHA32-33 Device
> + Device (DHA4) {
> + Name (_ADR, 0x00040000)
> + }
> +
> + // Uncore 3 GRP0_CHA0-7 Device
> + Device (DHA5) {
> + Name (_ADR, 0x000A0000)
> + }
> +
> + // Uncore 3 GRP0_CHA24-31 Device
> + Device (DHA8) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 3 GRP0_CHA32-33 Device
> + Device (DHA9) {
> + Name (_ADR, 0x000E0000)
> + }
> +
> + // Uncore 3 GRP0_CHA8-15 Device
> + Device (DHA6) {
> + Name (_ADR, 0x00B00000)
> + }
> +
> + // Uncore 3 GRP0_CHA16-23 Device
> + Device (DHA7) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 3 CHAALL0-1 Device
> + Device (CA01) {
> + Name (_ADR, 0x001D0000)
> + }
> +
> + // Uncore 3 CHASIS_PUINT0-7 Device
> + Device (PUC1) {
> + Name (_ADR, 0x001E0000)
> + }
> +
> + // Uncore 3 Gen3Phy Device
> + Device (GN31) {
> + Name (_ADR, 0x001F0000)
> + }
> + }
> +#endif
> +
> +#if MAX_SOCKET > 2
> + // Socket 2 Root bridge (Stack 0)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 0
> + Device (PC12) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0C)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR50)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // IIOMISC on PC12
> + Device (IIM2) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2A) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2B) {
> + Name (_ADR, 0x00010001)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2C) {
> + Name (_ADR, 0x00010002)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2D) {
> + Name (_ADR, 0x00010003)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2E) {
> + Name (_ADR, 0x00010004)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2F) {
> + Name (_ADR, 0x00010005)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2G) {
> + Name (_ADR, 0x00010006)
> + }
> +
> + // CB3DMA on PC12
> + Device (CB2H) {
> + Name (_ADR, 0x00010007)
> + }
> + }
> +
> + // Socket 2 Root bridge (Stack 1)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 1
> + Device (PC13) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0D)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR51)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // PCI Express Port 1A on PC13
> + Device (RR1A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR52)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 1B on PC13
> + Device (RR1B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR53)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 1C on PC13
> + Device (RR1C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR54)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 1D on PC13
> + Device (RR1D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR55)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> + }
> +
> + // Socket 2 Root bridge (Stack 2)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 2
> + Device (PC14) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0E)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR56)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // PCI Express Port 2A on PC14
> + Device (RR2A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR57)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 2B on PC14
> + Device (RR2B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR58)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 2C on PC14
> + Device (RR2C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR59)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 2D on PC14
> + Device (RR2D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR5A)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> + }
> +
> + // Socket 2 Root bridge (Stack 3)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 3
> + Device (PC15) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x0F)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR5B)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // PCI Express Port 3A on PC15
> + Device (RR3A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR5C)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 3B on PC15
> + Device (RR3B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR5D)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 3C on PC15
> + Device (RR3C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR5E)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 3D on PC15
> + Device (RR3D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR5F)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> + }
> +
> + // Socket 2 Root bridge (Stack 4)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 4
> + Device (PC16) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x10)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR60)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // PCI Express Port 4A on PC16
> + Device (RR4A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR61)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 4B on PC16
> + Device (RR4B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR62)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 4C on PC16
> + Device (RR4C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR63)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 4D on PC16
> + Device (RR4D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR64)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> + }
> +
> + // Socket 2 Root bridge (Stack 5)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 5
> + Device (PC17) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x11)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR65)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck2Ejd.asi"
> +
> + // PCI Express Port 5A on PC17
> + Device (RR5A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR66)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 5B on PC17
> + Device (RR5B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR67)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 5C on PC17
> + Device (RR5C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR68)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> +
> + // PCI Express Port 5D on PC17
> + Device (RR5D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR69)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1210nmEjd.asi"
> + }
> + }
> +
> + // Socket 2 Uncore 0
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 6
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x36)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR6A)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 4 UBOX Device
> + Device (UBX2) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 4 Misc 2 UPI 0-7 Device
> + Device (UP04) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 4 Misc 1 UPI 0-7 Device
> + Device (UP05) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 4 M2UPI Device
> + Device (M2U6) {
> + Name (_ADR, 0x00050000)
> + }
> +
> + // Uncore 4 M2UPI Device
> + Device (M2U7) {
> + Name (_ADR, 0x00060000)
> + }
> +
> + // Uncore 4 M2UPI Device
> + Device (M2U8) {
> + Name (_ADR, 0x00070000)
> + }
> +
> + // Uncore 4 CHASIS_SMBUS Devices
> + Device (CSM2) {
> + Name (_ADR, 0x000B0000)
> + }
> +
> + // Uncore 4 MS2MEM_SCF_MS2MEM0 Device
> + Device (M2M4) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 4 MS2MEM_SCF_MS2MEM1 Device
> + Device (M2M5) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 4 MCDDR0 Device
> + Device (MCD4) {
> + Name (_ADR, 0x001A0000)
> + }
> +
> + // Uncore 4 MCDDR1 Device
> + Device (MCD5) {
> + Name (_ADR, 0x001B0000)
> + }
> + }
> +
> + // Socket 2 Uncore 1
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 2
> +#define STACK 7
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x37)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR6B)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 5 GRP1_CHA0-7 Device
> + Device (EHA0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 5 GRP1_CHA8-15 Device
> + Device (EHA1) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // Uncore 5 GRP1_CHA16-23 Device
> + Device (EHA2) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 5 GRP1_CHAU24-31 Device
> + Device (EHA3) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 5 GRP1_CHA32-33 Device
> + Device (EHA4) {
> + Name (_ADR, 0x00040000)
> + }
> +
> + // Uncore 5 GRP0_CHA0-7 Device
> + Device (EHA5) {
> + Name (_ADR, 0x000A0000)
> + }
> +
> + // Uncore 5 GRP0_CHA24-31 Device
> + Device (EHA8) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 5 GRP0_CHA32-33 Device
> + Device (EHA9) {
> + Name (_ADR, 0x000E0000)
> + }
> +
> + // Uncore 5 GRP0_CHA8-15 Device
> + Device (EHA6) {
> + Name (_ADR, 0x00B00000)
> + }
> +
> + // Uncore 5 GRP0_CHA16-23 Device
> + Device (EHA7) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 5 CHAALL0-1 Device
> + Device (CA02) {
> + Name (_ADR, 0x001D0000)
> + }
> +
> + // Uncore 5 CHASIS_PUINT0-7 Device
> + Device (PUC2) {
> + Name (_ADR, 0x001E0000)
> + }
> +
> + // Uncore 5 Gen3Phy Device
> + Device (GN32) {
> + Name (_ADR, 0x001F0000)
> + }
> + }
> +#endif
> +
> +#if MAX_SOCKET > 3
> + // Socket 3 Root bridge (Stack 0)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 0
> + Device (PC18) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x12)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR6C)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // IIOMISC on PC18
> + Device (IIM3) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3A) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3B) {
> + Name (_ADR, 0x00010001)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3C) {
> + Name (_ADR, 0x00010002)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3D) {
> + Name (_ADR, 0x00010003)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3E) {
> + Name (_ADR, 0x00010004)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3F) {
> + Name (_ADR, 0x00010005)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3G) {
> + Name (_ADR, 0x00010006)
> + }
> +
> + // CB3DMA on PC18
> + Device (CB3H) {
> + Name (_ADR, 0x00010007)
> + }
> + }
> +
> + // Socket 3 Root bridge (Stack 1)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 1
> + Device (PC19) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x13)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR6D)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // PCI Express Port 1A on PC19
> + Device (SR1A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR6E)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 1B on PC19
> + Device (SR1B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR6F)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 1C on PC19
> + Device (SR1C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR70)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 1D on PC19
> + Device (SR1D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR71)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> + }
> +
> + // Socket 3 Root bridge (Stack 2)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 2
> + Device (PC20) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x14)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR72)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // PCI Express Port 2A on PC20
> + Device (SR2A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR73)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 2B on PC20
> + Device (SR2B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR74)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 2C on PC20
> + Device (SR2C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR75)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 2D on PC20
> + Device (SR2D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR76)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> + }
> +
> + // Socket 3 Root bridge (Stack 3)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 3
> + Device (PC21) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x15)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR77)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // PCI Express Port 3A on PC21
> + Device (SR3A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR78)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 3B on PC21
> + Device (SR3B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR79)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 3C on PC21
> + Device (SR3C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR7A)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 3D on PC21
> + Device (SR3D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR7B)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> + }
> +
> + // Socket 3 Root bridge (Stack 4)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 4
> + Device (PC22) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x16)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR7C)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // PCI Express Port 4A on PC22
> + Device (SR4A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR7D)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 4B on PC22
> + Device (SR4B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR7E)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 4C on PC22
> + Device (SR4C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR7F)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 4D on PC22
> + Device (SR4D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR80)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> + }
> +
> + // Socket 3 Root bridge (Stack 5)
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 5
> + Device (PC23) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x17)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR81)
> + }
> +
> + #include "IioRootBridge.asi"
> + #include "Sck3Ejd.asi"
> +
> + // PCI Express Port 5A on PC23
> + Device (SR5A) {
> + Name (_ADR, 0x00020000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR82)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 5B on PC23
> + Device (SR5B) {
> + Name (_ADR, 0x00030000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR83)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 5C on PC23
> + Device (SR5C) {
> + Name (_ADR, 0x00040000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR84)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> +
> + // PCI Express Port 5D on PC23
> + Device (SR5D) {
> + Name (_ADR, 0x00050000)
> + Method (_PRW, 0) {
> + Return (Package (0x02) {0x09, 0x04})
> + }
> + Method (_PRT, 0) {
> +
> + Return (AR85)
> + }
> +
> + #include "PcieHp.asi"
> + #include "PcieHpDev.asi"
> + #include "PC1810nmEjd.asi"
> + }
> + }
> +
> + // Socket 3 Uncore 0
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 6
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x38)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR86)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 6 UBOX Device
> + Device (UBX3) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 6 Misc 2 UPI 0-7 Device
> + Device (UP06) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 6 Misc 1 UPI 0-7 Device
> + Device (UP07) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 6 M2UPI0 Device
> + Device (M2U9) {
> + Name (_ADR, 0x00050000)
> + }
> +
> + // Uncore 6 M2UPI1 Device
> + Device (M2UA) {
> + Name (_ADR, 0x00060000)
> + }
> +
> + // Uncore 6 M2UPI2 Device
> + Device (M2UB) {
> + Name (_ADR, 0x00070000)
> + }
> +
> + // Uncore 6 CHASIS_SMBUS Devices
> + Device (CSM3) {
> + Name (_ADR, 0x000B0000)
> + }
> +
> + // Uncore 6 MS2MEM_SCF_MS2MEM0 Device
> + Device (M2M6) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 6 MS2MEM_SCF_MS2MEM1 Device
> + Device (M2M7) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 6 MCDDR0 Device
> + Device (MCD6) {
> + Name (_ADR, 0x001A0000)
> + }
> +
> + // Uncore 6 MCDDR1 Device
> + Device (MCD7) {
> + Name (_ADR, 0x001B0000)
> + }
> + }
> +
> + // Socket 3 Uncore 1
> + //
> +#undef SOCKET
> +#undef STACK
> +#define SOCKET 3
> +#define STACK 7
> + Device (CONCATENATE3(UC, SOCKET, STACK)) {
> + Name (_HID, EISAID("PNP0A03"))
> + Name (_UID, 0x39)
> +
> + //
> + // _PRT is ACPI method called by OS to read PCI Routing Table.
> + //
> + Method (_PRT, 0)
> + {
> + Return (AR87)
> + }
> +
> + #include "Uncore.asi"
> +
> + // Uncore 7 GRP1_CHA0-7 Device
> + Device (FHA0) {
> + Name (_ADR, 0x00000000)
> + }
> +
> + // Uncore 7 GRP1_CHA8-15 Device
> + Device (FHA1) {
> + Name (_ADR, 0x00010000)
> + }
> +
> + // Uncore 7 GRP1_CHA16-23 Device
> + Device (FHA2) {
> + Name (_ADR, 0x00020000)
> + }
> +
> + // Uncore 7 GRP1_CHAU24-31 Device
> + Device (FHA3) {
> + Name (_ADR, 0x00030000)
> + }
> +
> + // Uncore 7 GRP1_CHA32-33 Device
> + Device (FHA4) {
> + Name (_ADR, 0x00040000)
> + }
> +
> + // Uncore 7 GRP0_CHA0-7 Device
> + Device (FHA5) {
> + Name (_ADR, 0x000A0000)
> + }
> +
> + // Uncore 7 GRP0_CHA24-31 Device
> + Device (FHA8) {
> + Name (_ADR, 0x000D0000)
> + }
> +
> + // Uncore 7 GRP0_CHA32-33 Device
> + Device (FHA9) {
> + Name (_ADR, 0x000E0000)
> + }
> +
> + // Uncore 7 GRP0_CHA8-15 Device
> + Device (FHA6) {
> + Name (_ADR, 0x00B00000)
> + }
> +
> + // Uncore 7 GRP0_CHA16-23 Device
> + Device (FHA7) {
> + Name (_ADR, 0x000C0000)
> + }
> +
> + // Uncore 7 CHAALL0-1 Device
> + Device (CA03) {
> + Name (_ADR, 0x001D0000)
> + }
> +
> + // Uncore 7 CHASIS_PUINT0-7 Device
> + Device (PUC3) {
> + Name (_ADR, 0x001E0000)
> + }
> +
> + // Uncore 7 Gen3Phy Device
> + Device (GN33) {
> + Name (_ADR, 0x001F0000)
> + }
> + }
> +#endif
> +
> + // Virtual FPGA Bridge on Socket 0
> + Device (VFP0) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x18)
> + Method (_BBN, 0, NotSerialized) {
> + return (FBB0)
> + }
> +
> + Method (_PRT, 0) {
> +
> + Return (AR88)
> + }
> +
> + #include "FpgaBus00.asi"
> +
> + // FPGA Device
> + Device (FPG0) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +#if MAX_SOCKET > 1
> +
> + // Virtual FPGA Bridge on Socket 1
> + Device (VFP1) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x19)
> + Method (_BBN, 0, NotSerialized) {
> + return (FBB1)
> + }
> +
> + Method (_PRT, 0) {
> +
> + Return (AR89)
> + }
> +
> + #include "FpgaBus01.asi"
> +
> + // FPGA Device
> + Device (FPG1) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +#endif
> +
> +#if MAX_SOCKET > 2
> + // Virtual FPGA Bridge on Socket 2
> + Device (VFP2) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x1A)
> + Method (_BBN, 0, NotSerialized) {
> + return (FBB2)
> + }
> +
> + Method (_PRT, 0) {
> +
> + Return (AR8A)
> + }
> +
> + #include "FpgaBus02.asi"
> +
> + // FPGA Device
> + Device (FPG2) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +#endif
> +
> +#if MAX_SOCKET > 3
> + // Virtual FPGA Bridge on Socket 3
> + Device (VFP3) {
> + Name (_HID, EISAID("PNP0A08"))
> + Name (_CID, EISAID("PNP0A03"))
> + Name (_UID, 0x1B)
> + Method (_BBN, 0, NotSerialized) {
> + return (FBB3)
> + }
> +
> + Method (_PRT, 0) {
> +
> + Return (AR8B)
> + }
> +
> + #include "FpgaBus03.asi"
> +
> + // FPGA Device
> + Device (FPG3) {
> + Name (_ADR, 0x00000000)
> + }
> + }
> +#endif
> +}
> +
> +Scope (\_GPE) {
> + // [BR1A]: PCI Express Port 1A on PC01
> + // [BR1B]: PCI Express Port 1B on PC01
> + // [BR1C]: PCI Express Port 1C on PC01
> + // [BR1D]: PCI Express Port 1D on PC01
> + // [BR2A]: PCI Express Port 2A on PC02
> + // [BR2B]: PCI Express Port 2B on PC02
> + // [BR2C]: PCI Express Port 2C on PC02
> + // [BR2D]: PCI Express Port 2D on PC02
> + // [BR3A]: PCI Express Port 3A on PC03
> + // [BR3B]: PCI Express Port 3B on PC03
> + // [BR3C]: PCI Express Port 3C on PC03
> + // [BR3D]: PCI Express Port 3D on PC03
> + // [BR4A]: PCI Express Port 4A on PC04
> + // [BR4B]: PCI Express Port 4B on PC04
> + // [BR4C]: PCI Express Port 4C on PC04
> + // [BR4D]: PCI Express Port 4D on PC04
> + // [BR5A]: PCI Express Port 5A on PC05
> + // [BR5B]: PCI Express Port 5B on PC05
> + // [BR5C]: PCI Express Port 5C on PC05
> + // [BR5D]: PCI Express Port 5D on PC05
> + // [QR1A]: PCI Express Port 1A on PC07
> + // [QR1B]: PCI Express Port 1B on PC07
> + // [QR1C]: PCI Express Port 1C on PC07
> + // [QR1D]: PCI Express Port 1D on PC07
> + // [QR2A]: PCI Express Port 2A on PC08
> + // [QR2B]: PCI Express Port 2B on PC08
> + // [QR2C]: PCI Express Port 2C on PC08
> + // [QR2D]: PCI Express Port 2D on PC08
> + // [QR3A]: PCI Express Port 3A on PC09
> + // [QR3B]: PCI Express Port 3B on PC09
> + // [QR3C]: PCI Express Port 3C on PC09
> + // [QR3D]: PCI Express Port 3D on PC09
> + // [QR4A]: PCI Express Port 4A on PC10
> + // [QR4B]: PCI Express Port 4B on PC10
> + // [QR4C]: PCI Express Port 4C on PC10
> + // [QR4D]: PCI Express Port 4D on PC10
> + // [QR5A]: PCI Express Port 5A on PC11
> + // [QR5B]: PCI Express Port 5B on PC11
> + // [QR5C]: PCI Express Port 5C on PC11
> + // [QR5D]: PCI Express Port 5D on PC11
> + // [RR1A]: PCI Express Port 1A on PC13
> + // [RR1B]: PCI Express Port 1B on PC13
> + // [RR1C]: PCI Express Port 1C on PC13
> + // [RR1D]: PCI Express Port 1D on PC13
> + // [RR2A]: PCI Express Port 2A on PC14
> + // [RR2B]: PCI Express Port 2B on PC14
> + // [RR2C]: PCI Express Port 2C on PC14
> + // [RR2D]: PCI Express Port 2D on PC14
> + // [RR3A]: PCI Express Port 3A on PC15
> + // [RR3B]: PCI Express Port 3B on PC15
> + // [RR3C]: PCI Express Port 3C on PC15
> + // [RR3D]: PCI Express Port 3D on PC15
> + // [RR4A]: PCI Express Port 4A on PC16
> + // [RR4B]: PCI Express Port 4B on PC16
> + // [RR4C]: PCI Express Port 4C on PC16
> + // [RR4D]: PCI Express Port 4D on PC16
> + // [RR5A]: PCI Express Port 5A on PC17
> + // [RR5B]: PCI Express Port 5B on PC17
> + // [RR5C]: PCI Express Port 5C on PC17
> + // [RR5D]: PCI Express Port 5D on PC17
> + // [SR1A]: PCI Express Port 1A on PC19
> + // [SR1B]: PCI Express Port 1B on PC19
> + // [SR1C]: PCI Express Port 1C on PC19
> + // [SR1D]: PCI Express Port 1D on PC19
> + // [SR2A]: PCI Express Port 2A on PC20
> + // [SR2B]: PCI Express Port 2B on PC20
> + // [SR2C]: PCI Express Port 2C on PC20
> + // [SR2D]: PCI Express Port 2D on PC20
> + // [SR3A]: PCI Express Port 3A on PC21
> + // [SR3B]: PCI Express Port 3B on PC21
> + // [SR3C]: PCI Express Port 3C on PC21
> + // [SR3D]: PCI Express Port 3D on PC21
> + // [SR4A]: PCI Express Port 4A on PC22
> + // [SR4B]: PCI Express Port 4B on PC22
> + // [SR4C]: PCI Express Port 4C on PC22
> + // [SR4D]: PCI Express Port 4D on PC22
> + // [SR5A]: PCI Express Port 5A on PC23
> + // [SR5B]: PCI Express Port 5B on PC23
> + // [SR5C]: PCI Express Port 5C on PC23
> + // [SR5D]: PCI Express Port 5D on PC23
> + Method (_L09, 0x0, NotSerialized) {
> + #include "Gpe.asi"
> + Notify (\_SB.PC01.BR1A, 0x02)
> + Notify (\_SB.PC01.BR1B, 0x02)
> + Notify (\_SB.PC01.BR1C, 0x02)
> + Notify (\_SB.PC01.BR1D, 0x02)
> + Notify (\_SB.PC02.BR2A, 0x02)
> + Notify (\_SB.PC02.BR2B, 0x02)
> + Notify (\_SB.PC02.BR2C, 0x02)
> + Notify (\_SB.PC02.BR2D, 0x02)
> + Notify (\_SB.PC03.BR3A, 0x02)
> + Notify (\_SB.PC03.BR3B, 0x02)
> + Notify (\_SB.PC03.BR3C, 0x02)
> + Notify (\_SB.PC03.BR3D, 0x02)
> + Notify (\_SB.PC04.BR4A, 0x02)
> + Notify (\_SB.PC04.BR4B, 0x02)
> + Notify (\_SB.PC04.BR4C, 0x02)
> + Notify (\_SB.PC04.BR4D, 0x02)
> + Notify (\_SB.PC05.BR5A, 0x02)
> + Notify (\_SB.PC05.BR5B, 0x02)
> + Notify (\_SB.PC05.BR5C, 0x02)
> + Notify (\_SB.PC05.BR5D, 0x02)
> +#if MAX_SOCKET > 1
> + Notify (\_SB.PC07.QR1A, 0x02)
> + Notify (\_SB.PC07.QR1B, 0x02)
> + Notify (\_SB.PC07.QR1C, 0x02)
> + Notify (\_SB.PC07.QR1D, 0x02)
> + Notify (\_SB.PC08.QR2A, 0x02)
> + Notify (\_SB.PC08.QR2B, 0x02)
> + Notify (\_SB.PC08.QR2C, 0x02)
> + Notify (\_SB.PC08.QR2D, 0x02)
> + Notify (\_SB.PC09.QR3A, 0x02)
> + Notify (\_SB.PC09.QR3B, 0x02)
> + Notify (\_SB.PC09.QR3C, 0x02)
> + Notify (\_SB.PC09.QR3D, 0x02)
> + Notify (\_SB.PC10.QR4A, 0x02)
> + Notify (\_SB.PC10.QR4B, 0x02)
> + Notify (\_SB.PC10.QR4C, 0x02)
> + Notify (\_SB.PC10.QR4D, 0x02)
> + Notify (\_SB.PC11.QR5A, 0x02)
> + Notify (\_SB.PC11.QR5B, 0x02)
> + Notify (\_SB.PC11.QR5C, 0x02)
> + Notify (\_SB.PC11.QR5D, 0x02)
> +#endif
> +#if MAX_SOCKET > 2
> + Notify (\_SB.PC13.RR1A, 0x02)
> + Notify (\_SB.PC13.RR1B, 0x02)
> + Notify (\_SB.PC13.RR1C, 0x02)
> + Notify (\_SB.PC13.RR1D, 0x02)
> + Notify (\_SB.PC14.RR2A, 0x02)
> + Notify (\_SB.PC14.RR2B, 0x02)
> + Notify (\_SB.PC14.RR2C, 0x02)
> + Notify (\_SB.PC14.RR2D, 0x02)
> + Notify (\_SB.PC15.RR3A, 0x02)
> + Notify (\_SB.PC15.RR3B, 0x02)
> + Notify (\_SB.PC15.RR3C, 0x02)
> + Notify (\_SB.PC15.RR3D, 0x02)
> + Notify (\_SB.PC16.RR4A, 0x02)
> + Notify (\_SB.PC16.RR4B, 0x02)
> + Notify (\_SB.PC16.RR4C, 0x02)
> + Notify (\_SB.PC16.RR4D, 0x02)
> + Notify (\_SB.PC17.RR5A, 0x02)
> + Notify (\_SB.PC17.RR5B, 0x02)
> + Notify (\_SB.PC17.RR5C, 0x02)
> + Notify (\_SB.PC17.RR5D, 0x02)
> +#endif
> +#if MAX_SOCKET > 3
> + Notify (\_SB.PC19.SR1A, 0x02)
> + Notify (\_SB.PC19.SR1B, 0x02)
> + Notify (\_SB.PC19.SR1C, 0x02)
> + Notify (\_SB.PC19.SR1D, 0x02)
> + Notify (\_SB.PC20.SR2A, 0x02)
> + Notify (\_SB.PC20.SR2B, 0x02)
> + Notify (\_SB.PC20.SR2C, 0x02)
> + Notify (\_SB.PC20.SR2D, 0x02)
> + Notify (\_SB.PC21.SR3A, 0x02)
> + Notify (\_SB.PC21.SR3B, 0x02)
> + Notify (\_SB.PC21.SR3C, 0x02)
> + Notify (\_SB.PC21.SR3D, 0x02)
> + Notify (\_SB.PC22.SR4A, 0x02)
> + Notify (\_SB.PC22.SR4B, 0x02)
> + Notify (\_SB.PC22.SR4C, 0x02)
> + Notify (\_SB.PC22.SR4D, 0x02)
> + Notify (\_SB.PC23.SR5A, 0x02)
> + Notify (\_SB.PC23.SR5B, 0x02)
> + Notify (\_SB.PC23.SR5C, 0x02)
> + Notify (\_SB.PC23.SR5D, 0x02)
> +#endif
> + }
> +
> + // [EPCU]: EVA PCIe Uplink
> + // [VSP0]: EVA Virtual Switch Port 0
> + // [VSP1]: EVA Virtual Switch Port 1
> + // [VSP2]: EVA Virtual Switch Port 2
> + // [VSP3]: EVA Virtual Switch Port 3
> + Method (_L0B, 0x0, NotSerialized) {
> + Notify (\_SB.PC02.BR2A.EPCU, 0x02)
> + Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02)
> + Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02)
> + Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02)
> + Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02)
> + }
> +}
> +
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 1Ejd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 1Ejd.asi
> new file mode 100644
> index 0000000000..5c5c5fbade
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 1Ejd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2012 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if SCK1 is removed.
> + Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 2Ejd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 2Ejd.asi
> new file mode 100644
> index 0000000000..f8b0cd107d
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 2Ejd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2012 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if SCK2 is removed.
> + Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 3Ejd.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 3Ejd.asi
> new file mode 100644
> index 0000000000..175d5d871b
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck
> 3Ejd.asi
> @@ -0,0 +1,10 @@
> +/** @file
> +
> + @copyright
> + Copyright 2001 - 2012 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + // Eject device if SCK3 is removed.
> + Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx
> .asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx
> .asi
> new file mode 100644
> index 0000000000..d6a1e5da71
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx
> .asi
> @@ -0,0 +1,219 @@
> +/** @file
> +
> + @copyright
> + Copyright 2007 - 2017 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +Device (EPC) {
> + Name (_HID, EISAID ("INT0E0C"))
> + Name (_STR, Unicode ("Enclave Page Cache 1.0"))
> + Name (_MLS, Package () {Package (2) { "en", Unicode ("Enclave Page
> Cache 1.0")}})
> +
> + Name (RBUF, ResourceTemplate () {
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC0 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC1 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC2 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC3 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC4 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC5 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC6 // DescriptorName
> + )
> + QWordMemory (
> + ResourceConsumer, // ResourceUsage
> + PosDecode, // Decode _DEC
> + MinNotFixed, // IsMinFixed _MIF
> + MaxNotFixed, // IsMaxFixed _MAF
> + NonCacheable, // Cacheable _MEM
> + ReadWrite, // ReadAndWrite _RW
> + 0, // AddressGranularity _GRA
> + 0, // AddressMinimum _MIN <= To be patched in Runtime
> + 0, // AddressMaximum _MAX <= To be patched in Runtime
> + 0, // AddressTranslation _TRA
> + 0, // RangeLength _LEN <= To be patched in Runtime
> + , // ResourceSourceIndex
> + , // ResourceSource
> + EPC7 // DescriptorName
> + )
> + })
> +
> + Method (_CRS, 0x0, NotSerialized) {
> + If (LNotEqual (EBA0, 0)) {
> + CreateQwordField (RBUF, ^EPC0._MIN, MIN0)
> + CreateQwordField (RBUF, ^EPC0._MAX, MAX0)
> + CreateQwordField (RBUF, ^EPC0._LEN, LEN0)
> + Store (EBA0, MIN0)
> + Store (ELN0, LEN0)
> + Subtract (Add (EBA0, ELN0), 1, MAX0)
> + }
> + If (LNotEqual (EBA1, 0)) {
> + CreateQwordField (RBUF, ^EPC1._MIN, MIN1)
> + CreateQwordField (RBUF, ^EPC1._MAX, MAX1)
> + CreateQwordField (RBUF, ^EPC1._LEN, LEN1)
> + Store (EBA1, MIN1)
> + Store (ELN1, LEN1)
> + Subtract (Add (EBA1, ELN1), 1, MAX1)
> + }
> + If (LNotEqual (EBA2, 0)) {
> + CreateQwordField (RBUF, ^EPC2._MIN, MIN2)
> + CreateQwordField (RBUF, ^EPC2._MAX, MAX2)
> + CreateQwordField (RBUF, ^EPC2._LEN, LEN2)
> + Store (EBA2, MIN2)
> + Store (ELN2, LEN2)
> + Subtract (Add (EBA2, ELN2), 1, MAX2)
> + }
> + If (LNotEqual (EBA3, 0)) {
> + CreateQwordField (RBUF, ^EPC3._MIN, MIN3)
> + CreateQwordField (RBUF, ^EPC3._MAX, MAX3)
> + CreateQwordField (RBUF, ^EPC3._LEN, LEN3)
> + Store (EBA3, MIN3)
> + Store (ELN3, LEN3)
> + Subtract (Add (EBA3, ELN3), 1, MAX3)
> + }
> + If (LNotEqual (EBA4, 0)) {
> + CreateQwordField (RBUF, ^EPC4._MIN, MIN4)
> + CreateQwordField (RBUF, ^EPC4._MAX, MAX4)
> + CreateQwordField (RBUF, ^EPC4._LEN, LEN4)
> + Store (EBA4, MIN4)
> + Store (ELN4, LEN4)
> + Subtract (Add (EBA4, ELN4), 1, MAX4)
> + }
> + If (LNotEqual (EBA5, 0)) {
> + CreateQwordField (RBUF, ^EPC5._MIN, MIN5)
> + CreateQwordField (RBUF, ^EPC5._MAX, MAX5)
> + CreateQwordField (RBUF, ^EPC5._LEN, LEN5)
> + Store (EBA5, MIN5)
> + Store (ELN5, LEN5)
> + Subtract (Add (EBA5, ELN5), 1, MAX5)
> + }
> + If (LNotEqual (EBA6, 0)) {
> + CreateQwordField (RBUF, ^EPC6._MIN, MIN6)
> + CreateQwordField (RBUF, ^EPC6._MAX, MAX6)
> + CreateQwordField (RBUF, ^EPC6._LEN, LEN6)
> + Store (EBA6, MIN6)
> + Store (ELN6, LEN6)
> + Subtract (Add (EBA6, ELN6), 1, MAX6)
> + }
> + If (LNotEqual (EBA7, 0)) {
> + CreateQwordField (RBUF, ^EPC7._MIN, MIN7)
> + CreateQwordField (RBUF, ^EPC7._MAX, MAX7)
> + CreateQwordField (RBUF, ^EPC7._LEN, LEN7)
> + Store (EBA7, MIN7)
> + Store (ELN7, LEN7)
> + Subtract (Add (EBA7, ELN7), 1, MAX7)
> + }
> + Return (RBUF)
> + }
> +
> + Method (_STA, 0x0, NotSerialized) {
> + If (LNotEqual (EPCS, 0)) {
> + Return (0xF)
> + }
> + Return (0x0)
> + }
> +} // end EPC Device
> diff --git
> a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un
> core.asi
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un
> core.asi
> new file mode 100644
> index 0000000000..bfda78432c
> --- /dev/null
> +++
> b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Un
> core.asi
> @@ -0,0 +1,163 @@
> +/** @file
> +
> + @copyright
> + Copyright 2016 - 2020 Intel Corporation. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // _BBN is ACPI method called by OS to read PCI base bus number for IIO
> stack.
> + //
> + Method(_BBN, 0, NotSerialized)
> + {
> + Return(CONCATENATE3(BB, SOCKET, STACK))
> + }
> +
> + //
> + // _PXM is ACPI method called by OS to read Proximity Domain (aka NUMA
> Node) where IIO stack belongs to.
> + //
> + Method(_PXM, 0, NotSerialized)
> + {
> + Store(SOCKET, Local0)
> + If (CLOD) {
> + //
> + // If Sub-NUMA Cluster (SNC) enabled report PCI in the first of SNC
> domains of a socket,
> + // so multiplicate socket number by the number of SNC domains.
> + //
> + Multiply(Local0, CLOD, Local0)
> + }
> + Return(Local0)
> + }
> +
> + //
> + // _SEG is ACPI method called by OS to read PCI segment of IIO stack.
> + //
> + Method(_SEG, 0, NotSerialized)
> + {
> + Return(CONCATENATE2(SG0, SOCKET))
> + }
> +
> + //
> + // _STA is a ACPI method called by OS to read status of ACPI device, IIO
> stack in this case.
> + //
> + Method(_STA, 0, NotSerialized)
> + { //
> + // Check in processor present bitmap (PRBM) if processor is present, then
> + // in stack present bitmap of given processor (SPBx) if stack is present.
> + //
> + ShiftLeft(1, SOCKET, Local0)
> + If (And(PRBM, Local0)) {
> +
> + ShiftLeft(1, CONCATENATE2(0x,STACK), Local1)
> + if (And(CONCATENATE2(SPB, SOCKET), Local1)) {
> + Return(0x0F)
> + }
> + }
> + Return(0x00)
> + }
> +
> + External (DBGM, FieldUnitObj)
> + Name (SUPP, 0)
> + Name (CTRL, 0)
> +
> + Method(_OSC,4) {
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,0,CDW1)
> + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> +
> + //
> + // Create DWord-addressable fields from the capabilities Buffer
> + //
> + CreateDWordField(Arg3,4,CDW2)
> +
> + //
> + // Fill 3rd capability DWORD only if the count is greater than 2.
> + //
> + If(LGreater(Arg2,2)) {
> + CreateDWordField(Arg3,8,CDW3)
> + }
> +
> + //
> + // Save Capabilities DWord2 & 3
> + //
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> +
> + //
> + // Only allow native hot plug control if OS supports
> + // * ASPM
> + // * MSI/MSI-X
> + //
> + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not
> met?
> + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny.
> + Sleep(1000)
> + }
> +
> + //
> + // Never allow SHPC (no SHPC controller in system)
> + //
> + And(CTRL, 0x1D, CTRL)
> + //
> + // Disable Native PCIe AER handling from OS so that it uses Firmware
> First model in WHEA
> + //
> + And (CTRL, 0x17, CTRL)
> + If (Not(And(CDW1,1))) { // Query Flag Clear?
> + //
> + // Disable GPEs for Features granted native control
> + //
> + If (And(CTRL, 0x01)) { // Native Hot plug control granted?
> + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0
> + }
> + }
> +
> + If (LNotEqual(Arg1,one)) { // unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + //
> + // update DWORD3 in the buffer
> + //
> + Store(CTRL,CDW3)
> + Return(Arg3)
> +
> + } Else {
> + //
> + // Just indicate unrecognized UUID
> + // Leave it at that
> + //
> + Or (CDW1,4,CDW1)
> + if(LEqual(DBGM, 0x01)){
> + Store (0xEE, IO80)
> + }
> + Return(Arg3)
> + }
> + } // End _OSC
> +
> + Name (UNRS, ResourceTemplate() {
> + WORDBusNumber ( // Bus number resource (0); the bridge produces
> bus numbers for its subsequent buses
> + ResourceProducer, // bit 0 of general flags is 1
> + MinFixed, // Range is fixed
> + MaxFixed, // Range is fixed
> + PosDecode, // PosDecode
> + 0x0000, // Granularity (FIX9 - Patched by ACPI Platform Driver
> during POST)
> + 0x0000, // Min (FIX9 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Max (FIX9 - Patched by ACPI Platform Driver during
> POST)
> + 0x0000, // Translation
> + 0x0001, // Range Length = Max-Min+1 (FIX9 - Patched by ACPI
> Platform Driver during POST)
> + ,
> + ,
> + FIX9 // DescriptorName populated so iASL outputs offset for it in
> a .h file
> + )
> + })
> +
> + // Current resource template return
> + Method(_CRS, 0x0, NotSerialized)
> + {
> + Return(UNRS)
> + }
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> index 42680254d1..9c2b8a1048 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc
> @@ -805,6 +805,7 @@
>
> $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
>
> + $(RP_PKG)/Features/Acpi/AcpiTables/AcpiTables10nm.inf
> $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
>
> $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf
> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> index 45460570d9..ca3514b8ba 100644
> --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf
> @@ -671,6 +671,7 @@ SET
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
> INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
> INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
>
> + INF RuleOverride = ACPITABLE
> WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
> INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
> INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
>
> --
> 2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables
[not found] <16D196479AA7211B.12172@groups.io>
@ 2022-02-09 16:33 ` Oram, Isaac W
0 siblings, 0 replies; 18+ messages in thread
From: Oram, Isaac W @ 2022-02-09 16:33 UTC (permalink / raw)
To: devel@edk2.groups.io, Oram, Isaac W
Cc: Chiu, Chasel, Desimone, Nathaniel L, Gao, Liming, Dong, Eric
Series Pushed as b6f9674389..d1e809a50c
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Oram, Isaac W
Sent: Monday, February 7, 2022 11:03 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables
This patch series adds ACPI tables and the associated UBA driver required to patch the tables during boot.
The common AmlGenOffset python script needed to be updated for Python 3.
The server ACPI tables are large, so the 02 through 05 are just separating into multiple commits for review.
Building ACPI tables requires a pre-build step that generates AML offsets by building the ACPI tables with the appropriate flags, then stripping out offsets that do not need to be patched during boot.
Then the stripped down AML offsets are available for the main build as a C source data structure.
In the main build, StaticSkuDataDxe incorporates the AML offset data and publishes them if it is the correct motherboard.
The AcpiTables10nm data file and the StaticSkuDataDxe driver were previously provided in binary form in FvLateOpenBoard. The AcpiPlatform driver that consumes the AML offset data and patches tables with boottime data is still a binary.
The tables are provided as a part of WhitleyOpenBoardPkg because they can support multiple boards.
It is expected that most boards will make copies in their board directories and customize from there.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
Isaac Oram (8):
MinPlatformPkg/AmlGenOffset: Update for python 3
WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions
WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL
WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables
WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table
WhitleyOpenBoardPkg/Build: Enable includable build options
WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table
WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver
Platform/Intel/.gitignore | 2 +
Platform/Intel/MinPlatformPkg/Tools/AmlGenOffset/AmlGenOffset.py | 13 +-
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc | 54 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc | 81 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl | 20 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi | 346 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi | 205 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi | 730 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl | 61 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl | 19 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi | 158 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi | 157 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi | 137 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi | 183 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi | 16 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl | 1322 +++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi | 328 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi | 270 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi | 164 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi | 25 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi | 66 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi | 427 ++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi | 18 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi | 669 +++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl | 91 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi | 191 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi | 5388 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi | 10 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi | 219 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi | 163 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc | 72 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc | 171 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc | 972 ++++
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc | 61 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc | 68 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc | 137 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc | 44 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc | 136 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc | 89 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc | 74 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h | 91 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h | 30 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h | 37 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h | 206 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h | 88 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h | 43 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h | 58 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h | 57 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h | 56 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h | 84 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h | 58 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h | 50 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h | 120 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h | 87 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h | 59 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h | 82 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h | 53 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h | 67 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc | 151 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h | 41 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h | 42 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 7 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 148 +-
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 1 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 5 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c | 54 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c | 100 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c | 110 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md | 19 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c | 60 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h | 41 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf | 59 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 5 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc | 41 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf | 26 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py | 63 +
Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg | 15 +
Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h | 8 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl | 833 +++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl | 307 ++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl | 271 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl | 203 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl | 50 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl | 558 ++
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl | 15 +
Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl | 150 +
Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 1 +
123 files changed, 19064 insertions(+), 157 deletions(-) create mode 100644 Platform/Intel/.gitignore create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Bdat/Bdat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/DBG2/DBG2.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/AMLUPD.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/BiosParameterRegion.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CpuMemHp.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/DSDT.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus00.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus01.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus02.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/FpgaBus03.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Gpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcGpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcNotify10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieEdpcOst.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioPcieHotPlugGpeHandler10nm.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridge.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/IioRootBridgeIcx.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Mother.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/NvdimmGpe.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Os.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0010nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC0610nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1210nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PC1810nmEjd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PchApic.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHp.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieHpDev.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PcieNonHpDev.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Platform.asl
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformGpe10nm.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/PlatformPciTree10nm_EPRP.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck1Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck2Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sck3Ejd.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Sgx.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/Uncore.asi
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Facs/Facs62.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Fadt/Fadt62.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hmat/Hmat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Hpet/Hpet.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Mcfg/Mcfg.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Migt/Migt.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Msct/Msct.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/NFIT/Nfit.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/PCAT/Pcat.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Pmtt/Pmtt10nm.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/SPCR/Spcr.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Spmi/Spmi.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wddt/Wddt1.0.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Wsmt/Wsmt.aslc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaMpTableUpdateLib.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Library/UbaPirqUpdateLib.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AcpiStaticData.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/DeviceDataInstall.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/PlatformDeviceDataSRP10nm.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Readme.md
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.c
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.h
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc
create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/Pch.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchHda.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchNvs.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchPcie.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchSata.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/PchXhci.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP01_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP02_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP03_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP04_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP05_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP06_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP07_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP08_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP09_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP10_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP11_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP12_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP13_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP14_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP15_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP16_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP17_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP18_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP19_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/RP20_ADR.asl
create mode 100644 Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/AcpiTables/Dsdt/TraceHubDebug.asl
--
2.27.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-02-09 16:33 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-02-07 19:02 [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 1/8] MinPlatformPkg/AmlGenOffset: Update for python 3 Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 3/8] WhitleyOpenBoardPkg/AcpiTables: South Cluster ASL Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 4/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add Static ACPI tables Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 5/8] WhitleyOpenBoardPkg/AcpiTables10nm: Add DSDT ACPI table Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 6/8] WhitleyOpenBoardPkg/Build: Enable includable build options Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table Oram, Isaac W
2022-02-09 3:21 ` Nate DeSimone
2022-02-07 19:02 ` [edk2-devel][edk2-platforms][PATCH V1 8/8] WhitleyOpenBoardPkg/StaticSkuDataDxe: Add open source driver Oram, Isaac W
2022-02-09 3:20 ` Nate DeSimone
[not found] <16D196479AA7211B.12172@groups.io>
2022-02-09 16:33 ` [edk2-devel][edk2-platforms][PATCH V1 0/8] Whitley ACPI Tables Oram, Isaac W
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