From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.9335.1652187068864256248 for ; Tue, 10 May 2022 05:51:10 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Tz/vxIEo; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: sebastien.boeuf@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652187069; x=1683723069; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=f7Firy7xN496vJTKiaw4En9VMYDd3U8ePjMfGjsXaFw=; b=Tz/vxIEoGU7zR1/sk9eyJOTOo+Rrc+RNcQNkU3Tz31e+nyBOQz6wt32k wUWfRVPhVtiMnjpfrcOKgy+Fma351Glr9Og8fp1ZfOW7Uk3zleY22kjEz IW04HpZHx+fhUxFqpTxi4nI7wt4WT1enCV02JYqzt6ulI6+3GGtounv58 ANZsMFq23+gHkO4pKvMIr0fQXknj2MExVvkKIslbCmOaVsvKd7yECNJpi Q9zBf/e6rtee2GR8ID6qlwaD2RSSLG9eCaPzGpmeMLkHVMHxHtzyn5fQ4 1pcDsIsPMJUndV04bphm52TiunjtrN7XT4/92NlnQ2PUx5agCJWpSZC8H g==; X-IronPort-AV: E=McAfee;i="6400,9594,10342"; a="269499070" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="269499070" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 05:51:08 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="593493391" Received: from amrutaya-mobl1.gar.corp.intel.com (HELO sboeuf-mobl.intel.com) ([10.251.220.13]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 05:51:05 -0700 From: "Boeuf, Sebastien" To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses Date: Tue, 10 May 2022 14:50:42 +0200 Message-Id: X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit From: Sebastien Boeuf The goal of this series is to reduce the amount of inappropriate PIO and MMIO accesses generated by the firmware when running on Cloud Hypervisor. For MMIO accesses, it is about providing the right base address where the firmware will be loaded by the VMM in order to avoid unexpected accesses to some address ranges. For PIO accesses, it is about preventing some read/write to be performed in the first place, as we know the underlying device is not emulated by Cloud Hypervisor. Signed-off-by: Sebastien Boeuf Sebastien Boeuf (4): OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS OvmfPkg: Check for QemuFwCfg availability before accessing it OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation OvmfPkg: Don't access A20 gate register on Cloud Hypervisor OvmfPkg/CloudHv/CloudHvDefines.fdf.inc | 65 +++++++++++++++++++ OvmfPkg/CloudHv/CloudHvX64.dsc | 4 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 2 +- OvmfPkg/Library/PlatformInitLib/Platform.c | 13 ++-- .../QemuBootOrderLib/QemuBootOrderLib.c | 8 ++- 5 files changed, 82 insertions(+), 10 deletions(-) create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc -- 2.32.0 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 5 208 026.16 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.