* [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg: Update to Whitley FSP 4.2.0.2A
2023-01-12 23:56 [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Isaac Oram
@ 2023-01-12 23:56 ` Isaac Oram
2023-01-12 23:56 ` [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg: " Isaac Oram
2023-01-18 1:27 ` [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Nate DeSimone
2 siblings, 0 replies; 5+ messages in thread
From: Isaac Oram @ 2023-01-12 23:56 UTC (permalink / raw)
To: devel; +Cc: Isaac Oram, Nate DeSimone, Chasel Chiu
This contains binary interface changes and requires FSP 4.2.0.2A or later
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 23 +++++++++-------
.../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 4 ++-
.../Cpu/Include/CpuPolicyPeiDxeCommon.h | 2 +-
.../WhitleySiliconPkg/Include/BdatSchema.h | 16 +++++++-----
.../Include/Guid/MemoryMapData.h | 4 ++-
.../Include/Guid/SocketIioVariable.h | 13 +++++++---
.../Include/Guid/SocketMemoryVariable.h | 3 +++
.../Include/Guid/SocketPciResourceData.h | 4 ++-
.../Guid/SocketPowermanagementVariable.h | 2 ++
.../Guid/SocketProcessorCoreVariable.h | 2 +-
.../WhitleySiliconPkg/Include/IioConfig.h | 11 +++-----
.../Intel/WhitleySiliconPkg/Include/IioRegs.h | 1 -
.../Include/Library/EnhancedWarningLogLib.h | 2 --
.../Include/PlatformInfoTypes.h | 16 +++++++-----
.../Include/Ppi/MemoryPolicyPpi.h | 10 +++++++
.../Include/Ppi/RasImcS3Data.h | 6 -----
.../WhitleySiliconPkg/Include/Upi/KtiHost.h | 2 --
.../Core/Include/DataTypes.h | 10 ++++++-
.../BaseMemoryCoreLib/Core/Include/MemHost.h | 6 +----
.../BaseMemoryCoreLib/Platform/PlatformHost.h | 5 ----
.../Include/Private/Library/PchSpiCommonLib.h | 1 -
.../Product/Whitley/SiliconPkg10nmPcds.dsc | 5 ++++
.../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 2 +-
.../SecurityIp/SecurityIpSgxTem1v0_Outputs.h | 2 +-
.../Intel/WhitleySiliconPkg/SiliconPkg.dec | 26 ++++++++++++-------
25 files changed, 106 insertions(+), 72 deletions(-)
diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
index 2ccdbffa35..db61caf399 100644
--- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec
@@ -252,9 +252,9 @@
WhitleySiliconPkg/CpRcPkg.dec
}
gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2
+ gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4
gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2
- gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a
+ gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A
#
# MRC DEFAULT SETTINGS
@@ -273,7 +273,7 @@
#
gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | 0| UINT8|0x00000040
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE|BOOLEAN|0x0000003A
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE|BOOLEAN|0x0000003A
gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | FALSE|BOOLEAN|0x00000060
@@ -285,7 +285,7 @@
gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | 0x2| UINT8|0x00000066
gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | FALSE|BOOLEAN|0x00000067
gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | 0x6| UINT8|0x00000068
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOOLEAN|0x00000069
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOOLEAN|0x00000069
gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | TRUE| UINT8|0x0000006A
@@ -293,10 +293,10 @@
gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHealthConfig"| VOID*|0x00000070
gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | FALSE|BOOLEAN|0x00000071
gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | FALSE|BOOLEAN|0x00000072
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | 1| UINT8|0x00000073
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | 1| UINT8|0x00000074
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2| UINT8|0x0000011F
- gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE|BOOLEAN|0x00000120
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | 1| UINT8|0x00000073
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | 1| UINT8|0x00000074
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2| UINT8|0x0000011F
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE|BOOLEAN|0x00000120
gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | FALSE|BOOLEAN|0x00000075
#option to choose Mem Boot Health configuration type. 00=>Auto (Use defaults), 01=>Manual (Override defaults with setup option), 02=>Disable (Disable feature)
gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | 00| UINT8|0x00000076
@@ -360,6 +360,11 @@
# Ctl timing: CtlAll
gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | 5| UINT8|0x00000131
+ #MC VC0 Deadlock Breaker
+ gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings | TRUE| BOOLEAN|0x00000132
+ gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer | 18| UINT8|0x00000133
+ gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold | 4| UINT8|0x00000134
+
#Reset on Critical Margin failure to perform Memory Training from scratch
gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | 1| UINT8|0x00000087
@@ -526,7 +531,7 @@
gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000036
gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x00000118
## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor
- gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C
+ gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C
gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D
[PcdsDynamicEx]
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
index 7b027b58c6..763b9d31e4 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec
@@ -91,7 +91,9 @@
# @Prompt CPU Config Register Table Entry Maximum Count.
gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x60000022
-[PcdsDynamic, PcdsDynamicEx]
+ gCpuPkgTokenSpaceGuid.PcdCpuLowestApicIdAsBsp|TRUE|BOOLEAN|0x60000023
+
+[PcdsDynamicEx]
gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001
gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012
diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
index 6e84e0f7a6..dc5e09ea19 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h
@@ -52,7 +52,7 @@ typedef struct {
UINT8 CpuMtoIWa;
BOOLEAN RunCpuPpmInPei;
BOOLEAN AcExceptionOnSplitLockEnable;
- BOOLEAN CpuCrashLogGprs;
+ BOOLEAN CpuCrashDataGprs;
} CPU_POLICY_COMMON;
#endif
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
index 0b80015c65..010e8183af 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h
@@ -131,12 +131,16 @@ typedef struct {
// List of all entry types supported by this revision of memory training data structure
//
typedef enum {
- MemTrainingDataCapability = 0,
- MemTrainingDataIoGroup = 1,
- MemTrainingDataDram = 2,
- MemTrainingDataRcd = 3,
- MemTrainingDataIoSignal = 4,
- MemTrainingDataIoLatency = 5,
+ MemTrainingDataCapability = 0,
+ MemTrainingDataIoGroup = 1,
+ MemTrainingDataDram = 2,
+ MemTrainingDataRcd = 3,
+ MemTrainingDataIoSignal = 4,
+ MemTrainingDataIoLatency = 5,
+ MemTrainingDataPpin = 6,
+ MemTrainingDataBoardUuid = 7,
+ MemTrainingDataTurnaround = 8,
+ MemTrainingDataDcPmmTurnaround = 9,
MemTrainingDataTypeMax,
MemTrainingDataTypeDelim = MAX_INT32
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
index 73f303594a..f7a14ff5f4 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h
@@ -85,7 +85,9 @@ struct ChannelDevice {
UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
- UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+ UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
};
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
index a820cc6c25..0fafd00c98 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h
@@ -133,8 +133,8 @@ typedef struct {
UINT8 PcieSubSystemMode[TOTAL_IOU_VAR];
UINT8 CompletionTimeoutGlobal;
UINT8 CompletionTimeoutGlobalValue;
- UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
- UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+ UINT8 ReservedCto[MAX_SOCKET]; // On Setup
+ UINT8 ReservedCtov[MAX_SOCKET]; // On Setup
UINT8 CoherentReadPart;
UINT8 CoherentReadFull;
UINT8 PcieGlobalAspm;
@@ -372,7 +372,7 @@ typedef struct {
UINT8 ReservedS19; // On Setup
UINT8 ReservedS20; // On Setup
UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup
- UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup
+ UINT8 CompletionTimeoutValue[TOTAL_PORTS_VAR]; // On Setup
UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup
UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup
@@ -437,7 +437,12 @@ typedef struct {
UINT8 VtdPciAcsCtlBit2;
UINT8 VtdPciAcsCtlBit3;
UINT8 VtdPciAcsCtlBit4;
- UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup
+ UINT8 AltAttenTable[TOTAL_PORTS_VAR];
+ UINT8 PciePort10bitTag[TOTAL_PORTS_VAR]; // Controls port support for 10-bit Tag
+
+ UINT8 MaskPcieRpWarmResetMcaWa; //on Setup
+ UINT8 PostedInterruptThrottle;
+
} SOCKET_IIO_CONFIGURATION;
#pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
index 533489fafc..f8710ee7bb 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h
@@ -469,6 +469,9 @@ typedef struct {
UINT8 RmtMinimumMarginCheck;
UINT8 ReservedS149;
+ UINT8 pTRR;
+ UINT8 AdrPatrolScrubDisable;
+
} SOCKET_MEMORY_CONFIGURATION;
#pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
index 567a44e73f..439f61c88d 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h
@@ -41,11 +41,13 @@ typedef struct {
// If anything changed reset the system PCI resource configuration.
//
UINT64 MmioHBase;
- UINT64 MmioHLimit;
+ UINT64 MmioHGranularity;
UINT32 MmioLBase;
UINT32 MmioLLimit;
+ UINT32 MmioLGranularity;
UINT16 IoBase;
UINT16 IoLimit;
+ UINT16 IoGranularity;
UINT16 StackPresentBitmap[MAX_SOCKET];
//
// Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
index 460e6e300b..c29bf51cb6 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVariable.h
@@ -290,6 +290,8 @@ typedef struct {
UINT8 RunCpuPpmInPei;
UINT8 UncoreFreqRaplLimit;
+
+ UINT8 PrgTjOffsetEn;
} SOCKET_POWERMANAGEMENT_CONFIGURATION;
#pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
index 52ab370ce7..ca4ebd4d4a 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVariable.h
@@ -136,7 +136,7 @@ typedef struct {
UINT8 CFRS3mManualCommit;
UINT8 CFRPucodeEnable;
UINT8 CFRPucodeManualCommit;
- UINT8 CpuCrashLogGprs;
+ UINT8 CpuCrashDataGprs;
} SOCKET_PROCESSORCORE_CONFIGURATION;
#pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
index a8e3e69255..385db192d2 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h
@@ -45,6 +45,7 @@ typedef struct {
UINT8 PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup
UINT8 PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS];
+ UINT8 PciePort10bitTag[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET];
UINT8 PciePtm;
UINT8 PcieHotPlugEnable;
UINT8 PCIe_LTR;
@@ -104,8 +105,7 @@ typedef struct {
UINT8 CompletionTimeoutGlobal;
UINT8 CompletionTimeoutGlobalValue;
- UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
- UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
+ UINT8 CompletionTimeoutValue[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup
UINT8 CoherentReadPart;
UINT8 CoherentReadFull;
UINT8 PcieGlobalAspm;
@@ -124,7 +124,6 @@ typedef struct {
UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup
UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup
UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup
- UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup
UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup
UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup
UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup
@@ -273,6 +272,7 @@ typedef struct {
UINT8 ProblematicPort; //on Setup
UINT8 DmiAllocatingFlow; //on Setup
UINT8 PcieAllocatingFlow; //on Setup
+ UINT8 MaskPcieRpWarmResetMcaWa; //on Setup
UINT8 PcieAcpiHotPlugEnable; //on Setup
BOOLEAN PcieLowLatencyRetimersEnabled;
UINT8 HaltOnDmiDegraded; //on Setup
@@ -335,13 +335,10 @@ typedef struct {
UINT32 ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
UINT32 ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_PER_STACK];
- UINT8 ReservedAE[MAX_TOTAL_PORTS]; // On Setup
-
UINT8 ReservedAF[MAX_TOTAL_PORTS];
UINT8 ReservedAG[MAX_TOTAL_PORTS]; // On Setup
BOOLEAN ReservedAH; // On Setup
-
/**
==================================================================================================
====================== IIO Global Performance Tuner Related Setup Options =====================
@@ -374,7 +371,6 @@ typedef struct {
UINT8 MSINFATEN[MAX_TOTAL_PORTS];
UINT8 MSICOREN[MAX_TOTAL_PORTS];
UINT8 ACPIPMEn[MAX_TOTAL_PORTS];
- UINT8 DISL0STx[MAX_TOTAL_PORTS];
UINT8 P2PRdDis[MAX_TOTAL_PORTS];
UINT8 DisPMETOAck[MAX_TOTAL_PORTS];
UINT8 ACPIHP[MAX_TOTAL_PORTS];
@@ -393,6 +389,7 @@ typedef struct {
IIO_PCIE_CONFIG_DATA IioPcieConfig;
UINT32 VtdDisabledBitmask[MAX_SOCKET];
+ UINT8 PostedInterruptThrottle;
} IIO_CONFIG;
#pragma pack()
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
index 37a1e627da..66cb1e3dfc 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h
@@ -128,7 +128,6 @@
#define PCIE_PORT_0_FUNC_0 0x00
#define PCIE_PORT_1A_DEV_1 0x02
-#define PCIE_PORT_1A_FUNC_1 0x00
#define PCIE_PORT_1B_DEV_1 0x03
#define PCIE_PORT_1C_DEV_1 0x04
#define PCIE_PORT_1D_DEV_1 0x05
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
index 211dc48c86..745a52dafe 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib.h
@@ -191,9 +191,7 @@ typedef struct {
UINT32 EccS;
UINT32 Chunk;
UINT32 Column;
- UINT32 ColumnExt;
UINT32 Row;
- UINT32 RowExt;
UINT32 Bank;
UINT32 Rank;
UINT32 Subrank;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
index 8fc0efec24..0c14a2409f 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -41,10 +41,10 @@ typedef enum {
TypeWilsonCityModular,
TypeCoyotePass,
TypeIdaville,
- TypeMoroCityRP,
- TypeBrightonCityRp,
+ TypeMoroCityRP = 0x0E, //maps to PcdDefaultBoardId
+ TypeBrightonCityRp = 0x0F, //maps to PcdDefaultBoardId value
TypeJacobsville,
- TypeSnrSvp,
+ TypeSnrSvp = 0x11, //maps to PcdDefaultBoardId
TypeSnrSvpSodimm,
TypeJacobsvilleMDV,
TypeFrostCreekRP,
@@ -64,13 +64,15 @@ typedef enum {
TypeArcherCityXPV,
TypeBigPineKey,
TypeExperWorkStationRP,
- TypeJunctionCity,
- TypeAowanda,
+ TypeAmericanPass,
EndOfEfiPlatformTypeEnum,
//
// Vendor board range currently starts at 0x80
//
- TypeBoardPortTemplate // 0x80
+ TypeBoardPortTemplate, // 0x80
+ TypeJunctionCity,
+ TypeAowanda,
+ EndOfVendorPlatformTypeEnum
} EFI_PLATFORM_TYPE;
#define TypePlatformUnknown 0xFF
@@ -78,7 +80,7 @@ typedef enum {
#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1
#define TypePlatformDefault TypeWilsonPointRP
#define TypePlatformVendorMin 0x80
-#define TypePlatformVendorMax TypeBoardPortTemplate - 1
+#define TypePlatformVendorMax EndOfVendorPlatformTypeEnum - 1
//
// CPU type: Standard (no MCP), -F, etc
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
index 38b90713f7..7a86804d9b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h
@@ -1905,6 +1905,7 @@ struct memSetup {
/// 1 = High<BR>
/// 2 = Low<BR>
UINT8 PanicWm;
+ UINT8 pTRR;
/// @brief
/// Enable/Disable LRDIMM DB DFE.<BR>
@@ -1923,6 +1924,15 @@ struct memSetup {
//
UINT8 VirtualNumaEnable;
+ ///
+ /// @brief
+ /// Enable/Disable patrol scrub when entering the ADR.<BR>
+ /// @details
+ /// 0 - disable.<BR>
+ /// 1 - enable.<BR>
+ //
+ UINT8 AdrPatrolScrubDisable;
+
///
/// @brief
/// Smart Test Key pattern.<BR>
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
index 2198f8516a..82725bc84e 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h
@@ -44,13 +44,7 @@ EFI_STATUS
OUT VOID *Data
);
-/**
- RAS IMC S3 Data PPI
-**/
struct _RAS_IMC_S3_DATA_PPI {
- /**
- Retrieves data for S3 saved memory RAS features from non-volatile storage.
- **/
RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData;
};
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
index 09a3f37edf..5cadda4907 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h
@@ -300,12 +300,10 @@ typedef struct {
Contains a pointer to a 24 byte fixed length array.
The array contains the 3 instances of the following c-struct
- ~~~
typedef struct {
UINT32 CfrImagePtr;
UINT32 CfrImageSize;
}
- ~~~
This allows a maximum of 3 CFR/SINIT binaries to be provided by platform code.
**/
UINT32 CFRImagePtr;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
index eb4bd92a1d..ef1775e1ed 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h
@@ -12,11 +12,17 @@
#include <Base.h>
+///
+/// 8-byte DWORD addressable unsigned value.
+///
typedef struct u64_struct {
UINT32 lo;
UINT32 hi;
} UINT64_STRUCT, *PUINT64_STRUCT;
+///
+/// 8-byte DWORD addressable unsigned value.
+///
typedef union {
struct {
UINT32 Low;
@@ -25,7 +31,9 @@ typedef union {
UINT64 Data;
} UINT64_DATA;
-
+///
+/// 16-byte DWORD addressable unsigned value.
+///
typedef struct u128_struct {
UINT32 one;
UINT32 two;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
index 8eaea40f72..3ae5bcb612 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h
@@ -641,11 +641,9 @@ struct rankDevice {
///
typedef struct dimmDevice {
INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_TCK)
-#ifdef DEBUG_CODE_BLOCK
UINT32 tCL;
UINT16 tRCD;
UINT16 tRP;
-#endif // DEBUG_CODE_BLOCK
UINT16 NVmemSize;
UINT16 memSize; ///< Memory size for this DIMM (64MB granularity)
UINT16 UnmappedMemSize;
@@ -653,6 +651,7 @@ typedef struct dimmDevice {
struct FmcCacheSt FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status
UINT8 SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DIMM partitionRatios
UINT8 CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MAX_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB
+ BOOLEAN TrainingModeEnabled; //Training Mode for BPS
BOOLEAN FmcWdbFlushFailed; /// < 0 = WDB flush failed on previous boot, 1 = WDB flush completed w/o errors on previous boot
BOOLEAN EadrFlushFailed; /// < 0 = Extended ADR flush failed on previous boot, 1 = Extended ADR flush completed w/o errors on previous boot
} DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice
@@ -919,9 +918,7 @@ typedef struct memVar {
UINT8 callingTrngOffstCfgOnce; ///<to prevent looping inside RMT
UINT8 earlyCmdClkExecuted;
UINT8 checkMappedOutRanks;
-#ifdef DEBUG_CODE_BLOCK
UINT8 earlyCtlClkSerialDebugFlag;
-#endif // DEBUG_CODE_BLOCK
UINT32 memSize; ///< Total physical memory size
UINT32 NVmemSize; ///< Total physical memory size
UINT32 TotalInterleavedMemSize; ///< DDR4 memory size for this socket (64MB granularity)
@@ -1048,4 +1045,3 @@ typedef struct memVar {
#pragma pack(pop)
#endif // _memhost_h
-
diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
index aa9b570f63..2fa735b65b 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Platform/PlatformHost.h
@@ -24,12 +24,7 @@
#define MAX_PPR_ADDR_ENTRIES 20
#define MAX_PPR_ADDR_ENTRIES_SPPR 40
-#if !defined(SILENT_MODE)
-#define DEBUG_CODE_BLOCK 1
-#endif
-
#define UBIOS_GENERATION_EN BIT22 // flag to enable DfxUbiosGeneration from Simics
#define HYBRID_SYSTEM_LEVEL_EMULATION_EN BIT23 // flag to enable DfxHybridSystemLevelEmulation from Simics
#endif // _platformhost_h
-
diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
index f93740f4f0..a1fd5ae0f5 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/Private/Library/PchSpiCommonLib.h
@@ -53,7 +53,6 @@ typedef struct {
EFI_HANDLE Handle;
PCH_SPI_PROTOCOL SpiProtocol;
UINT16 PchAcpiBase;
- UINTN PchSpiBase;
UINT16 ReadPermission;
UINT16 WritePermission;
UINT32 SfdpVscc0Value;
diff --git a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
index f9c588b61c..1988965205 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
+++ b/Silicon/Intel/WhitleySiliconPkg/Product/Whitley/SiliconPkg10nmPcds.dsc
@@ -26,6 +26,11 @@
gEfiCpRcPkgTokenSpaceGuid.PcdCleanTempBusAssignment|TRUE
# Default SMBUS speed for Whitley is 700Khz - see SMB_CLOCK_FREQUENCY definition
+ # 0 - SMB_CLK_100K - 100 Khz
+ # 1 - SMB_CLK_400K - 400 Khz
+ # 2 - SMB_CLK_700K - 700 Khz
+ # 3 - SMB_CLK_1M - 1 Mhz
+ #
gEfiCpRcPkgTokenSpaceGuid.PcdMrcSmbusSpeedDefault|0x2
!if (($(CPUTARGET) == "ICX"))
diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
index c464343929..4b1de79adf 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Inputs.h
@@ -13,7 +13,7 @@
UINT8 EnableSgx; ///< Enable SGX
UINT8 SgxFactoryReset; ///< Delete all registration data, if SGX enabled force IPE/FirstBinding flow
UINT64 PrmrrSize; ///< SGX PRMRR size
-UINT64 ReservedS239;
+UINT64 SprspOrLaterPrmSize; ///< SGX PRM size (SPR+ only)
UINT8 SgxQoS; ///< SGX Quality of Service
UINT8 SgxAutoRegistrationAgent; ///< SGX Auto Registration Agent
UINT8 SgxPackageInfoInBandAccess; ///< SGX Expose Package Info to OS
diff --git a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
index 45b63b21c5..1df00251d7 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Security/Include/Guid/SecurityIp/SecurityIpSgxTem1v0_Outputs.h
@@ -15,8 +15,8 @@ UINT64 ValidPrmrrBitMap;
UINT64 SprspOrLaterPrmSizeBitmap; // ## PRODUCED by SgxPreMemInit
UINT8 ShowEpoch;
UINT8 SkipSignalPpmDone; // ## PRODUCED by SgxEarlyInit
+UINT8 IsSmxCapable; // ## PRODUCED by SgxPreMemInit
-UINT8 SprspOrLaterIsPrmSizeInvalidated; // ## PRODUCED by SgxPreMemInit
UINT8 SprspOrLaterAreHardwarePreconditionsMet; // ## PRODUCED by SgxPreMemInit
UINT8 SprspOrLaterAreMemoryPreconditionsMet; // ## PRODUCED by SgxPreMeminit
UINT8 SprspOrLaterAreSetupPreconditionsMet; // ## PRODUCED by SgxPreMemInit
diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
index e03ee6d5d8..e010d65854 100644
--- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
+++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec
@@ -698,13 +698,6 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
#
# VTD PCDs Begin
#
- ## The mask is used to control VTd behavior.<BR><BR>
- # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.)
- # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)
- # BIT2: Force no IOMMU access attribute request recording before DMAR table is installed.
- # BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Protection
- # @Prompt The policy for VTd driver behavior.
- gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002
## Declares VTd PEI DMA buffer size.<BR><BR>
# When this PCD value is referred by platform to calculate the required
@@ -840,7 +833,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
gSiPkgTokenSpaceGuid.PcdTempRefreshOption |0|UINT8|0x7000000A
# Temperature refresh value default, Values are in Celcius
- gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x19|UINT8|0x70000001
+ gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x00|UINT8|0x70000001
gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue |0x53|UINT8|0x70000002
gSiPkgTokenSpaceGuid.PcdFourxRefreshValue |0x5F|UINT8|0x70000003
@@ -933,6 +926,8 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
# VTD PCDs End
#
+ gSiPkgTokenSpaceGuid.PcdPcieMultiVcEnable|FALSE|BOOLEAN|0xF0000038
+
[PcdsDynamicEx]
gReferenceCodePolicyTokenSpaceGuid.PcdEvMode |0x00|UINT8|0x00010001
# ReservedC: The Mailbox Command which it gona to assert.
@@ -958,12 +953,26 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
#
gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E
+ #
+ # RAS: PcdRasIerrPresent - TRUE: IERR has occured need reset; FALSE: No IERR
+ #
+ gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002
+
[PcdsDynamicEx]
gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007
gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A
gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D
gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B
+## Will be set if platform is WS else remains FALSE for Server platform.
+ gPlatformTokenSpaceGuid.PcdIsCPUWsType|FALSE|BOOLEAN|0x6000001A
+
+## C2F
+## Will be set if platform is resuming from a global reset after ADR trigger.
+ # C2F driver will read the PCD and determine whether to perform C2f Entry.
+ # @Prompt Provide status if Adr resume or not
+
+ gPlatformTokenSpaceGuid.PcdAdrResumeStatus|0|UINT8|0x0000104A
##
## ME
##
@@ -979,7 +988,6 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43,
## RAS
##
gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001
- gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002
[PcdsFeatureFlag]
## This PCD used by FPGA drivers to decide to install FPGA features.
--
2.39.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg: Update to Whitley FSP 4.2.0.2A
2023-01-12 23:56 [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Isaac Oram
2023-01-12 23:56 ` [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg: Update to Whitley FSP 4.2.0.2A Isaac Oram
@ 2023-01-12 23:56 ` Isaac Oram
2023-01-18 1:27 ` [edk2-devel][edk2-platforms][PATCH V1 0/2] Update Si support Nate DeSimone
2 siblings, 0 replies; 5+ messages in thread
From: Isaac Oram @ 2023-01-12 23:56 UTC (permalink / raw)
To: devel; +Cc: Isaac Oram, Nate DeSimone, Chasel Chiu
This contains binary interface changes and requires FSP 4.2.0.2A or later
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
---
.../Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c | 2 +-
.../AcpiTables/Dsdt/CommonPlatform10nm.asi | 1 +
.../Pci/Dxe/PciHostBridge/PciRebalance.c | 243 ++++++++++--------
.../Include/Dsc/BuildOptions.dsc | 2 +-
.../Include/Dsc/EnableRichDebugMessages.dsc | 9 +
.../Include/Guid/SetupVariable.h | 3 +
.../SiliconPolicyUpdateLib.c | 2 +-
.../SiliconPolicyUpdateLibFsp.c | 2 +-
.../WhitleyOpenBoardPkg/PlatformPkgConfig.dsc | 6 +-
.../WhitleyOpenBoardPkg/StructurePcd.dsc | 173 ++++++++++++-
.../WhitleyOpenBoardPkg/StructurePcdCpx.dsc | 91 ++++++-
11 files changed, 415 insertions(+), 119 deletions(-)
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c
index d2a7b811dc..a9728edf61 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.c
@@ -364,7 +364,7 @@ PlatformCpuPolicyEntryPoint (
mCpuPolicyConfiguration.Policy.CpuExpandedIioLlcWaysBitMask = SetupData.SocketConfig.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask;
mCpuPolicyConfiguration.Policy.CpuRemoteWaysBitMask = SetupData.SocketConfig.SocketProcessorCoreConfiguration.RemoteWaysMask;
mCpuPolicyConfiguration.Policy.CpuRrqCountThreshold = mIioUds->PlatformData.RemoteRequestThreshold;
- mCpuPolicyConfiguration.Policy.CpuCrashLogGprs = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.CpuCrashLogGprs > 0) ? TRUE : FALSE;
+ mCpuPolicyConfiguration.Policy.CpuCrashDataGprs = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.CpuCrashDataGprs > 0) ? TRUE : FALSE;
//CSR SAPM CTL
for( socket = 0; socket < MAX_SOCKET; socket++) {
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
index 28a997b102..714a5ddbb0 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/CommonPlatform10nm.asi
@@ -186,6 +186,7 @@
If(LEqual(And(CPBF, 0x00000040), 0x00000040)) {
Store(1,HWPS)
}
+
}
If (CondRefOf (\_SB.OSPC)) {
Return (\_SB.OSPC(Arg0, Arg1, Arg2, Arg3))
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.c
index b32f0bf835..24f047c237 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciRebalance.c
@@ -419,7 +419,7 @@ AdjustSocketResources (
Status = AdjustSocketMmioH (SocketResources, ResourceType, ValidSockets);
break;
default:
- DEBUG((DEBUG_ERROR, "ERROR: Resource Type Unknown = %x\n",ResourceType));
+ DEBUG((DEBUG_ERROR, "[PCI] ERROR: Resource Type Unknown = %x\n", ResourceType));
Status = EFI_INVALID_PARAMETER;
break;
} // switch
@@ -429,7 +429,7 @@ AdjustSocketResources (
/**
- Calculate current system resource map with retrieved NVRAM variable to see if stored settings were applied
+ Compare current system resource map with rebalance request NVRAM variable to see if stored settings were applied.
@param[in] SocketPciResourceData - Pointer to stored CPU resource map
@@ -488,7 +488,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d.%d] Current I/O: 0x%04X..0x%04X\n", Socket, Stack,
IioUdsStackLimits->PciResourceIoBase, IioUdsStackLimits->PciResourceIoLimit);
PCIDEBUG ("[%d.%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket, Stack,
- StackLimits->Io.Base, StackLimits->Io.Limit, Rejected ? "rejected" : "");
+ StackLimits->Io.Base, StackLimits->Io.Limit,
+ (StackLimits->Io.Limit != 0 && Rejected) ? "rejected" : "");
if (IioUdsStackLimits->Mmio32Base != StackLimits->LowMmio.Base && StackLimits->LowMmio.Base != 0) {
Rejected = TRUE;
@@ -499,7 +500,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d.%d] Current MMIOL: 0x%08X..0x%08X\n", Socket, Stack,
IioUdsStackLimits->Mmio32Base, IioUdsStackLimits->Mmio32Limit);
PCIDEBUG ("[%d.%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket, Stack,
- StackLimits->LowMmio.Base, StackLimits->LowMmio.Limit, Rejected ? "rejected" : "");
+ StackLimits->LowMmio.Base, StackLimits->LowMmio.Limit,
+ (StackLimits->LowMmio.Limit != 0 && Rejected) ? "rejected" : "");
if (IioUdsStackLimits->Mmio64Base != StackLimits->HighMmio.Base && StackLimits->HighMmio.Base != 0) {
Rejected = TRUE;
@@ -510,7 +512,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d.%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socket, Stack,
IioUdsStackLimits->Mmio64Base, IioUdsStackLimits->Mmio64Limit);
PCIDEBUG ("[%d.%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", Socket, Stack,
- StackLimits->HighMmio.Base, StackLimits->HighMmio.Limit, Rejected ? "rejected" : "");
+ StackLimits->HighMmio.Base, StackLimits->HighMmio.Limit,
+ (StackLimits->HighMmio.Limit != 0 && Rejected) ? "rejected" : "");
}
}
//
@@ -525,7 +528,8 @@ IsResourceMapRejected (
PCIDEBUG("[%d] Current I/O: 0x%04X..0x%04X\n", Socket,
IioUdsSocketLimits->PciResourceIoBase, IioUdsSocketLimits->PciResourceIoLimit);
PCIDEBUG("[%d] Saved I/O: 0x%04X..0x%04X %a\n", Socket,
- SocketLimits->Io.Base, SocketLimits->Io.Limit, Rejected ? "rejected" : "");
+ SocketLimits->Io.Base, SocketLimits->Io.Limit,
+ (SocketLimits->Io.Limit != 0 && Rejected) ? "rejected" : "");
if (IioUdsSocketLimits->Mmio32Base != SocketLimits->LowMmio.Base && SocketLimits->LowMmio.Base != 0) {
Rejected = TRUE;
@@ -536,7 +540,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d] Current MMIOL: 0x%08X..0x%08X\n", Socket,
IioUdsSocketLimits->Mmio32Base, IioUdsSocketLimits->Mmio32Limit);
PCIDEBUG ("[%d] Saved MMIOL: 0x%08X..0x%08X %a\n", Socket,
- SocketLimits->LowMmio.Base, SocketLimits->LowMmio.Limit, Rejected ? "rejected" : "");
+ SocketLimits->LowMmio.Base, SocketLimits->LowMmio.Limit,
+ (SocketLimits->LowMmio.Limit != 0 && Rejected) ? "rejected" : "");
if (IioUdsSocketLimits->Mmio64Base != SocketLimits->HighMmio.Base && SocketLimits->HighMmio.Base != 0) {
Rejected = TRUE;
@@ -547,7 +552,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d] Current MMIOH: 0x%012llX..0x%012llX\n", Socket,
IioUdsSocketLimits->Mmio64Base, IioUdsSocketLimits->Mmio64Limit);
PCIDEBUG ("[%d] Saved MMIOH: 0x%012llX..0x%012llX %a\n", Socket,
- SocketLimits->HighMmio.Base, SocketLimits->HighMmio.Limit, Rejected ? "rejected" : "");
+ SocketLimits->HighMmio.Base, SocketLimits->HighMmio.Limit,
+ (SocketLimits->HighMmio.Limit != 0 && Rejected) ? "rejected" : "");
if (IioUdsUboxStackLimits->Mmio64Base != UboxStackLimits->HighMmio.Base && UboxStackLimits->HighMmio.Base != 0) {
Rejected = TRUE;
@@ -558,7 +564,8 @@ IsResourceMapRejected (
PCIDEBUG ("[%d] Current UBOX: 0x%08X..0x%08X\n", Socket,
IioUdsUboxStackLimits->Mmio64Base, IioUdsUboxStackLimits->Mmio64Limit);
PCIDEBUG ("[%d] Saved UBOX: 0x%08X..0x%08X %a\n", Socket,
- UboxStackLimits->HighMmio.Base, UboxStackLimits->HighMmio.Limit, Rejected ? "rejected" : "");
+ UboxStackLimits->HighMmio.Base, UboxStackLimits->HighMmio.Limit,
+ (UboxStackLimits->HighMmio.Limit != 0 && Rejected) ? "rejected" : "");
}
}
DEBUG ((DEBUG_INFO, "[PCI] Resource rebalance rejected ? %a\n", Rejected ? "TRUE" : "FALSE"));
@@ -567,91 +574,67 @@ IsResourceMapRejected (
/**
- Read SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME variable from flash and verify its content.
+ Verify whether system resource map changed comparing to the state when rebalance request was created.
- If the variable does not exist, or is not valid for current system configuration
- the buffer at *PciResConfigPtr is just cleared.
+ @param[in] PciResConfigPtr - Buffer with the rebalance request.
- @param[out] PciResConfigPtr - Buffer for the resource configuration variable.
-
- @retval EFI_SUCCESS The function completed successfully.
- @retval EFI_NOT_FOUND The variable was not found.
- @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
- @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure.
+ @return If current map is different than the one used when rebalance was created true is returned,
+ otherwise false.
**/
-EFI_STATUS
-PciHostReadResourceConfig (
- OUT SYSTEM_PCI_BASE_LIMITS *PciResConfigPtr
+BOOLEAN
+IsSystemMapChanged (
+ IN SYSTEM_PCI_BASE_LIMITS *PciResConfigPtr
)
{
- UINTN VarSize;
- EFI_STATUS Status;
- UINT8 Socket;
+ UINT8 Socket;
- VarSize = sizeof(*PciResConfigPtr);
- Status = gRT->GetVariable (SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, &gEfiSocketPciResourceDataGuid,
- NULL, &VarSize, PciResConfigPtr);
- if (EFI_ERROR (Status) && Status != EFI_BUFFER_TOO_SMALL) {
- goto ErrExit;
- }
- if (Status == EFI_BUFFER_TOO_SMALL || VarSize != sizeof(*PciResConfigPtr)) {
-
- PCIDEBUG ("Got variable '%s' of unexpected size %d (expect %d) - overwrite\n",
- SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, VarSize, sizeof(*PciResConfigPtr));
- Status = EFI_NOT_FOUND;
- goto ErrExit;
- }
- //
- // If any of the below checks fails clear the buffer and return EFI_NOT_FOUND.
- //
- Status = EFI_NOT_FOUND;
if (PciResConfigPtr->MmioHBase != mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base ||
- PciResConfigPtr->MmioHLimit != mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit) {
+ PciResConfigPtr->MmioHGranularity != *(UINT64*)&mIioUds->IioUdsPtr->PlatformData.MmiohGranularity) {
- PCIDEBUG ("%s: Memory map changed (MMIOH %012llX..%012llX != %012llX..%012llX) - overwrite\n",
- SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
- PciResConfigPtr->MmioHBase, PciResConfigPtr->MmioHLimit,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit);
- goto ErrExit;
+ DEBUG ((DEBUG_ERROR, "[PCI] %s: MMIOH Base %012llX [%llX] != %012llX [%llX] - system map changed\n",
+ SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
+ PciResConfigPtr->MmioHBase, PciResConfigPtr->MmioHGranularity,
+ mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base,
+ *(UINT64*)&mIioUds->IioUdsPtr->PlatformData.MmiohGranularity));
+ return TRUE;
}
if (PciResConfigPtr->MmioLBase != mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base ||
- PciResConfigPtr->MmioLLimit != mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit) {
+ PciResConfigPtr->MmioLLimit != mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit ||
+ PciResConfigPtr->MmioLGranularity != mIioUds->IioUdsPtr->PlatformData.MmiolGranularity) {
- PCIDEBUG ("%s: Memory map changed (MMIOL %08X..%08X != %08X..%08X) - overwrite\n",
- SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
- PciResConfigPtr->MmioLBase, PciResConfigPtr->MmioLLimit,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit);
- goto ErrExit;
+ DEBUG ((DEBUG_ERROR, "[PCI] %s: MMIOL %08X..%08X [%X] != %08X..%08X [%X] - system map changed\n",
+ SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
+ PciResConfigPtr->MmioLBase, PciResConfigPtr->MmioLLimit, PciResConfigPtr->MmioLGranularity,
+ mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base,
+ mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit,
+ mIioUds->IioUdsPtr->PlatformData.MmiolGranularity));
+ return TRUE;
}
if (PciResConfigPtr->IoBase != mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase ||
- PciResConfigPtr->IoLimit != mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit) {
+ PciResConfigPtr->IoLimit != mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit ||
+ PciResConfigPtr->IoGranularity != mIioUds->IioUdsPtr->PlatformData.IoGranularity) {
- PCIDEBUG ("%s: Memory map changed (I/O %04X..%04X != %04X..%04X) - overwrite\n",
- SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
- PciResConfigPtr->IoBase, PciResConfigPtr->IoLimit,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase,
- mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit);
- goto ErrExit;
+ DEBUG ((DEBUG_ERROR, "[PCI] %s: I/O %04X..%04X [%X] != %04X..%04X [%X] - system map changed\n",
+ SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME,
+ PciResConfigPtr->IoBase, PciResConfigPtr->IoLimit, PciResConfigPtr->IoGranularity,
+ mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase,
+ mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit,
+ mIioUds->IioUdsPtr->PlatformData.IoGranularity));
+ return TRUE;
}
for (Socket = 0; Socket < NELEMENTS (PciResConfigPtr->Socket); Socket++) {
if (PciResConfigPtr->StackPresentBitmap[Socket] !=
mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap) {
- PCIDEBUG ("%s: Stack bitmap mismach (%04X != %04X) in socket %d - overwrite\n",
- SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, PciResConfigPtr->StackPresentBitmap[Socket],
- mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap, Socket);
- goto ErrExit;
+ DEBUG ((DEBUG_ERROR, "[PCI] %s: Stack bitmap mismach (%04X != %04X) in socket %d - system map changed\n",
+ SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, PciResConfigPtr->StackPresentBitmap[Socket],
+ mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap, Socket));
+ return TRUE;
}
}
- return EFI_SUCCESS;
-
- ErrExit:
- ZeroMem (PciResConfigPtr, sizeof(*PciResConfigPtr));
- return Status;
-} // PciHostReadResourceConfig()
+ return FALSE;
+} // IsSystemMapChanged()
/**
@@ -689,6 +672,7 @@ AdjustResourceAmongRootBridges (
UINT8 TypeIndex;
UINT8 ChangedBitMap;
EFI_STATUS Status;
+ UINTN VarSize;
SYSTEM_PCI_BASE_LIMITS SocketPciResourceData;
UINT8 Stack;
UINT8 LastStack;
@@ -717,28 +701,47 @@ AdjustResourceAmongRootBridges (
MmiohGranularity |= ((UINT64)mIioUds->IioUdsPtr->PlatformData.MmiohGranularity.hi) << 32;
ZeroMem (&SocketResources[0], sizeof(SocketResources));
//
- // Read the system resource cfg from NVRAM. If the variable does not exist, or is
- // not valid for current system configuration the buffer SocketPciResourceData
- // is just cleared.
+ // Read the system resource cfg from NVRAM. If the variable does not exist just create new one.
+ // If variable exists, check if it was applied by KTI. If not we got two options possible:
+ // (1) it is not valid because system resource map changed, or
+ // (2) it is not valid because of unknown reason.
+ // The first case is detected and new request shall be created for rebalance.
+ // In the second case just continue boot to avoid reboot loop.
//
- Status = PciHostReadResourceConfig (&SocketPciResourceData);
- if (EFI_ERROR (Status)) {
+ VarSize = sizeof(SocketPciResourceData);
+ ZeroMem (&SocketPciResourceData, sizeof(SocketPciResourceData));
+ Status = gRT->GetVariable (SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, &gEfiSocketPciResourceDataGuid,
+ NULL, &VarSize, &SocketPciResourceData);
+ if (EFI_ERROR (Status) && Status != EFI_NOT_FOUND && Status != EFI_BUFFER_TOO_SMALL) {
- if (Status != EFI_NOT_FOUND) {
-
- ASSERT_EFI_ERROR (Status);
- return;
- }
- //
- // Variable is not initialized yet, go with empty structure.
- //
- } else if (IsResourceMapRejected (&SocketPciResourceData)) {
- //
- // If variable is already initialized, but rejected by KTI do not reboot to avoid loop.
- //
+ ASSERT_EFI_ERROR (Status);
return;
}
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ VarSize += 1; // Make it not equal to sizeof(SocketPciResourceData)
+ }
+ if (VarSize != sizeof(SocketPciResourceData)) {
+
+ PCIDEBUG ("Got variable '%s' of unexpected size %d (expect %d)\n",
+ SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME, VarSize, sizeof(SocketPciResourceData));
+ }
+ if (Status != EFI_NOT_FOUND) {
+ //
+ // Variable exists, let's check if it was applied by KTI.
+ //
+ if (IsResourceMapRejected (&SocketPciResourceData)) {
+ //
+ // Rejected so check if system resources map was changed.
+ //
+ if (!IsSystemMapChanged (&SocketPciResourceData) && VarSize == sizeof(SocketPciResourceData)) {
+
+ DEBUG ((DEBUG_ERROR, "[PCI] ERROR: Resource rebalance rejected by KTI - continue without rebalance\n"));
+ return;
+ }
+ ZeroMem (&SocketPciResourceData, sizeof(SocketPciResourceData));
+ }
+ }
UboxMmioSize = mIioUds->IioUdsPtr->PlatformData.UboxMmioSize;
PlatGlobalMmiolBase = mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base;
ValidSockets = 0;
@@ -918,6 +921,13 @@ AdjustResourceAmongRootBridges (
NewLength += Alignment;
}
+ //
+ // Check if new length is big enough to support PEI MMIO resource assigment for the stacks
+ //
+ if (NewLength < mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes[Stack].Mmio32MinSize) {
+ NewLength = mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes[Stack].Mmio32MinSize;
+ }
+
if (NewLength != 0) {
//
// At least 4MB align per KTI requirement. Add the length requested with given alignment.
@@ -1036,6 +1046,9 @@ AdjustResourceAmongRootBridges (
Remainder = MmiohGranularity - (NewLength % MmiohGranularity);
NewLength += Remainder;
}
+
+ NewLength = ALIGN_VALUE (NewLength, Alignment);
+
//
// Store length as length - 1 for handling
//
@@ -1134,31 +1147,44 @@ AdjustResourceAmongRootBridges (
}
}
}
- } else if (OutOfResources && ChangedTypeOOR[TypeMem64]){
- //
- // Allow mmioh to be adjusted to access max available physical address range.
- //
- Status = AdjustSocketResources (SocketResources, TypeMem64, ValidSockets);
- if (Status == EFI_SUCCESS) {
- ChangedBitMap |= (1 << TypeIndex);
- } else {
- ChangedBitMap &= ~(1 << TypeIndex);
+ } else if (OutOfResources) {
+ if (ChangedTypeOOR[TypeMem64]) {
+ //
+ // Allow mmioh to be adjusted to access max available physical address range.
+ //
+ Status = AdjustSocketResources (SocketResources, TypeMem64, ValidSockets);
+ if (Status == EFI_SUCCESS) {
+ ChangedBitMap |= (1 << TypeIndex);
+ } else {
+ ChangedBitMap &= ~(1 << TypeIndex);
+ }
+ }
+ if (ChangedTypeOOR[TypeIo] || ChangedTypeOOR[TypeMem32]) {
+ DEBUG ((DEBUG_ERROR, "Clearing %s request\n", mPciResourceTypeStr[TypeIo]));
+ DEBUG ((DEBUG_ERROR, "Clearing %s request\n", mPciResourceTypeStr[TypeMem32]));
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+ for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) {
+ SocketResources[Socket].StackRes[Stack].NeedIoUpdate = 0;
+ SocketResources[Socket].StackRes[Stack].MmiolUpdate = 0;
+ }
+ }
}
}
-
+ //
// Update changed resource type.
// OemGetResourceMapUpdate() will only update changed resource type so it is alright if data is zero.
+ //
if (ChangedBitMap != 0) {
for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
SocketPciResourceData.StackPresentBitmap[Socket] = mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap;
for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) {
+
if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap & (1 << Stack))) {
continue;
}
CurStackLimits = &SocketPciResourceData.Socket[Socket].StackLimits[Stack];
-
//
// Disable stacks that have no resources and are assigned none.
// Reaching this far means the stack is valid and should be disabled if base equals limit and
@@ -1293,9 +1319,10 @@ AdjustResourceAmongRootBridges (
CurSocketLimits->HighMmio.Base = SocketResources[Socket].MmiohBase;
CurSocketLimits->HighMmio.Limit = SocketResources[Socket].MmiohLimit;
}
-
- DEBUG((DEBUG_INFO, "\nSocketResources[%x].UboxBase =%x\n",Socket,UboxStackLimits->LowMmio.Base));
- DEBUG((DEBUG_INFO, "SocketResources[%x].UboxLimit =%x\n",Socket,UboxStackLimits->LowMmio.Limit));
+ DEBUG((DEBUG_INFO, "\nSocketResources[%x].UboxBase = %x\n",
+ Socket, SocketPciResourceData.Socket[Socket].StackLimits[UBOX_STACK].LowMmio.Base));
+ DEBUG((DEBUG_INFO, "SocketResources[%x].UboxLimit = %x\n",
+ Socket, SocketPciResourceData.Socket[Socket].StackLimits[UBOX_STACK].LowMmio.Limit));
DEBUG((DEBUG_INFO, "\nSocketResources[%x].IoBase =%x\n",Socket,SocketResources[Socket].IoBase));
DEBUG((DEBUG_INFO, "SocketResources[%x].IoLimit =%x\n",Socket,SocketResources[Socket].IoLimit));
DEBUG((DEBUG_INFO, "SocketResources[%x].MmiolBase =%x\n",Socket,SocketResources[Socket].MmiolBase));
@@ -1304,16 +1331,18 @@ AdjustResourceAmongRootBridges (
DEBUG((DEBUG_INFO, "SocketResources[%x].MmiohLimit =%lx\n",Socket,SocketResources[Socket].MmiohLimit));
} // for Socket
SocketPciResourceData.MmioHBase = mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Base;
- SocketPciResourceData.MmioHLimit = mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio64Limit;
+ SocketPciResourceData.MmioHGranularity = *(UINT64*)&mIioUds->IioUdsPtr->PlatformData.MmiohGranularity;
SocketPciResourceData.MmioLBase = mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Base;
SocketPciResourceData.MmioLLimit = mIioUds->IioUdsPtr->PlatformData.PlatGlobalMmio32Limit;
+ SocketPciResourceData.MmioLGranularity = mIioUds->IioUdsPtr->PlatformData.MmiolGranularity;
SocketPciResourceData.IoBase = mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoBase;
SocketPciResourceData.IoLimit = mIioUds->IioUdsPtr->PlatformData.PlatGlobalIoLimit;
+ SocketPciResourceData.IoGranularity = mIioUds->IioUdsPtr->PlatformData.IoGranularity;
PCIDEBUG("Writing resource rebalance request '%s':\n", SYSTEM_PCI_RESOURCE_CONFIGURATION_DATA_NAME);
- PCIDEBUG("System I/O : %04X..%04X\n", SocketPciResourceData.IoBase, SocketPciResourceData.IoLimit);
- PCIDEBUG("System MMIOL: %08X..%08X\n", SocketPciResourceData.MmioLBase, SocketPciResourceData.MmioLLimit);
- PCIDEBUG("System MMIOH: %012llX..%012llX\n", SocketPciResourceData.MmioHBase, SocketPciResourceData.MmioHLimit);
+ PCIDEBUG("System I/O : %04X..%04X [%X]\n", SocketPciResourceData.IoBase, SocketPciResourceData.IoLimit, SocketPciResourceData.IoGranularity);
+ PCIDEBUG("System MMIOL: %08X..%08X [%X]\n", SocketPciResourceData.MmioLBase, SocketPciResourceData.MmioLLimit, SocketPciResourceData.MmioLGranularity);
+ PCIDEBUG("System MMIOH: %012llX [%llX]\n", SocketPciResourceData.MmioHBase, SocketPciResourceData.MmioHGranularity);
for (Socket = 0; Socket < NELEMENTS (SocketPciResourceData.Socket); Socket++) {
PCIDEBUG("[%d] StackPresent: 0x%04X\n", Socket, SocketPciResourceData.StackPresentBitmap[Socket]);
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
index 9213507b98..f4bcd60ced 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/BuildOptions.dsc
@@ -16,7 +16,7 @@
!endif
!if $(DEBUG_FLAGS_ENABLE) == TRUE
- DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
!else
DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
!endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessages.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessages.dsc
index 6a66f2ebbb..be423da00a 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessages.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/EnableRichDebugMessages.dsc
@@ -14,6 +14,15 @@
# Customize debug messages
#
[PcdsFixedAtBuild]
+ ## The mask is used to control DebugLib behavior.<BR><BR>
+ # BIT0 - Enable Debug Assert.<BR>
+ # BIT1 - Enable Debug Print.<BR>
+ # BIT2 - Enable Debug Code.<BR>
+ # BIT3 - Enable Clear Memory.<BR>
+ # BIT4 - Enable BreakPoint as ASSERT.<BR>
+ # BIT5 - Enable DeadLoop as ASSERT.<BR>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+
## This flag is used to control the built in Debug messages.
# BIT0 - Initialization message.<BR>
# BIT1 - Warning message.<BR>
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h
index c47f040ca3..5a22a2f61b 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Guid/SetupVariable.h
@@ -670,6 +670,9 @@ typedef struct {
// TCC Mode
//
UINT8 TccMode;
+ // RAS Fast string Disable option
+ //
+ UINT8 DisableFastString;
} SYSTEM_CONFIGURATION;
typedef struct {
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c
index 08144936dd..35268a76c7 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c
@@ -553,7 +553,7 @@ Returns:
//
// Update SPI policies
//
- PchPolicy->SpiConfig.ShowSpiController = TRUE;
+ PchPolicy->SpiConfig.ShowSpiController = FALSE;
PchPolicy->PmConfig.PmcReadDisable = TRUE;
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c
index f7e4ee5e2f..21a5444884 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.c
@@ -561,7 +561,7 @@ Returns:
//
// Update SPI policies
//
- PchPolicy->SpiConfig.ShowSpiController = TRUE;
+ PchPolicy->SpiConfig.ShowSpiController = FALSE;
PchPolicy->PmConfig.PmcReadDisable = TRUE;
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
index c9620f11d8..73739e4070 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
@@ -13,7 +13,11 @@
[Defines]
DEFINE CRB_FLAG_ENABLE = TRUE
-DEFINE DEBUG_FLAGS_ENABLE = FALSE
+!if $(TARGET) == "RELEASE"
+ DEFINE DEBUG_FLAGS_ENABLE = FALSE
+!else
+ DEFINE DEBUG_FLAGS_ENABLE = TRUE
+!endif
DEFINE SERVER_BIOS_ENABLE = TRUE
DEFINE PCH_SERVER_BIOS_ENABLE = TRUE
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
index 9437686fcb..0c0ffde53e 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc
@@ -1049,6 +1049,7 @@ gStructPcdTokenSpaceGuid.PcdSetup.DdrtInternalAlertEn|0x1
gStructPcdTokenSpaceGuid.PcdSetup.ReservedS2|0x2
gStructPcdTokenSpaceGuid.PcdSetup.ReservedS1|0x0
gStructPcdTokenSpaceGuid.PcdSetup.ReservedS3|0x2
+gStructPcdTokenSpaceGuid.PcdSetup.DisableFastString|0x0 # Disable Fast String after first poison error
gStructPcdTokenSpaceGuid.PcdSetup.DisableMAerrorLoggingDueToLER|0x1 # LER MA Error Logging
gStructPcdTokenSpaceGuid.PcdSetup.EdpcEn|0x0 # IIO eDPC Support
gStructPcdTokenSpaceGuid.PcdSetup.EdpcErrCorMsg|0x1 # IIO eDPC ERR_COR Message
@@ -1700,6 +1701,86 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9 # PCI-E Completion Timeout
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9 # PCI-E Completion Timeout
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[4]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[5]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[6]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[7]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[8]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[9]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[10]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[11]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[12]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[13]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[14]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[15]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[16]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[17]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[18]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[19]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[20]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[21]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[22]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[23]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[24]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[25]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[26]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[27]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[28]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[29]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[30]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[31]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[32]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[33]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[34]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[35]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[36]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[37]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[38]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[39]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[40]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[41]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[42]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[43]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[44]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[45]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[46]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[47]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[48]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[49]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[50]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[51]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[52]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[53]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[54]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[55]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[56]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[57]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[58]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[59]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[60]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[61]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[62]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[63]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[64]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[65]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[66]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[67]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[68]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[69]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[70]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[71]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[72]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[73]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[74]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[75]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[76]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[77]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[78]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[79]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[80]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[81]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[82]|0x9 # PCI-E Completion Timeout
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[83]|0x9 # PCI-E Completion Timeout
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[0]|0x0 # Compliance Mode
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[1]|0x0 # Compliance Mode
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ComplianceMode[2]|0x0 # Compliance Mode
@@ -6396,6 +6477,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[80]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 # Link Speed
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 # Link Speed
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 # Link Speed
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[0]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[1]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[2]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[3]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[4]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[5]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[6]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[7]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[8]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[9]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[10]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[11]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[12]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[13]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[14]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[15]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[16]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[17]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[18]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[19]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[20]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[21]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[22]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[23]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[24]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[25]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[26]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[27]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[28]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[29]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[30]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[31]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[32]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[33]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[34]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[35]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[36]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[37]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[38]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[39]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[40]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[41]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[42]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[43]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[44]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[45]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[46]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[47]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[48]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[49]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[50]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[51]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[52]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[53]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[54]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[55]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[56]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[57]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[58]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[59]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[60]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[61]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[62]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[63]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[64]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[65]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[66]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[67]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[68]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[69]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[70]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[71]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[72]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[73]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[74]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[75]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[76]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[77]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[78]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[79]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[80]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[81]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[82]|0x2
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePort10bitTag[83]|0x2
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x2 # PCIe PTM Support
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 # Pcie Relaxed Ordering
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 # PCIe Slot Item Control
@@ -6600,6 +6765,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[21]|0x0
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[22]|0x0 # Enable MMIO read cmpl poison for STACK_4
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PoisonMmioReadEn[23]|0x0 # Enable MMIO read cmpl poison for STACK_5
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterrupt|0x1 # Posted Interrupt
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PostedInterruptThrottle|0x1 # Posted Interrupt Throttle
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PrioritizeTPH|0x0 # Prioritize TPH
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ProblematicPort|0x0 # Problematic port
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.RetimerGlParmReg0Override[2]|0x0 # - Override
@@ -7411,6 +7577,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADDDCEn|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2 # ADR Data Save Mode
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1 # Enable ADR
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1 # Enable ADDDC Error Injection
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdrPatrolScrubDisable|0x0 # ADR Patrol Scrub Disable
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186a0 # Adv MemTest Pause
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTrefi|0x3cf0 # Adv MemTest tREFI
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondTwr|0xa # Adv MemTest tWR
@@ -7479,6 +7646,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrMemoryType|0x2
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtCkeEn|0x1 # PMem CKE
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DdrtSrefEn|0x0 # PMem SELF REFRESH
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.DfeGainBias|0x0 # DfeGainBias
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS48|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS127|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS122|0x1
@@ -7529,7 +7697,6 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS137|0x2
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS128|0x2
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS123|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x8
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS125|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS64|0x7ff
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS113|0x1
@@ -7782,6 +7949,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.multiSparingRanks|0x2
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.normOppInterval|0x400 # Normal Operation Duration
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oneRankTimingMode|0x1 # One Rank Timing Mode
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.oppReadInWmm|0x1 # Opp read during WMM
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pTRR|0x0 # pTRR
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsad0|0x0 # Mirror TAD0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[0]|0x0 # Partial Mirror 1 Size (GB)
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[1]|0x0 # Partial Mirror 2 Size (GB)
@@ -8406,6 +8574,7 @@ gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVal|0x0
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SnpLatVld|0x0 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.SwLtrOvrdCtl|0x0 # PCIe LTR Override Control
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TCCActivationOffset|0x0 # TCC Activation Offset
+gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.PrgTjOffsetEn|0x0 # Programmable TJ Offset Enable
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.TStateEnable|0x0 # Software Controlled T-States
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStatusFilter|0x0 # Therm-Monitor-Status Filter
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig.ThermalMonitorStatusFilterTimeWindow|0x9 # Therm-Monitor-Status Filter Time Window
@@ -8451,7 +8620,7 @@ gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[1]|0x0
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[2]|0x0 # Disable Bitmap
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreDisableMask[3]|0x0 # Disable Bitmap
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CoreFailover|0x1 # Core Failover
-gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashLogGprs|0x0 # Cpu CrashLog Gprs
+gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuCrashDataGprs|0x0 # Cpu Crash Data Gprs
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuDbpEnable|0x0 # DBP-F
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuL1NextPagePrefetcherDisable|0x0 # L1 Next Page Prefetcher
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig.CpuMtoIWa|0x1 # MtoI Workaround
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
index 0c166ade00..a9311f3e9b 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcdCpx.dsc
@@ -76,10 +76,6 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CbDmaMultiCastEnable|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CoherencySupport|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobal|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutGlobalValue|0x9
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9
-gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[0]|0xFF
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[1]|0xFF
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ConfigIOU0[2]|0xFF
@@ -1664,6 +1660,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[80]|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[81]|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[82]|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[83]|0x1
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[0]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[1]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[2]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[3]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[4]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[5]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[6]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[7]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[8]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[9]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[10]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[11]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[12]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[13]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[14]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[15]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[16]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[17]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[18]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[19]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[20]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[21]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[22]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[23]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[24]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[25]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[26]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[27]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[28]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[29]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[30]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[31]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[32]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[33]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[34]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[35]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[36]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[37]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[38]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[39]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[40]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[41]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[42]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[43]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[44]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[45]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[46]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[47]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[48]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[49]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[50]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[51]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[52]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[53]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[54]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[55]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[56]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[57]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[58]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[59]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[60]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[61]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[62]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[63]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[64]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[65]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[66]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[67]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[68]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[69]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[70]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[71]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[72]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[73]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[74]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[75]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[76]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[77]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[78]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[79]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[80]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[81]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[82]|0x9
+gStructPcdTokenSpaceGuid.PcdSocketIioConfig.CompletionTimeoutValue[83]|0x9
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[0]|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[1]|0x1
gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[2]|0x1
@@ -2445,6 +2525,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS191|0x2
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.Cpu3P5ReservedS246|0x2
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdddcErrInjEn|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADRDataSaveMode|0x2
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdrPatrolScrubDisable|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ADREn|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondition|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.AdvMemTestCondPause|0x186A0
@@ -2523,7 +2604,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS141|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS142|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS75|0x1
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS80|0x4
-gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x1
+gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS149|0x0
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[0]|0xFF
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[1]|0xFF
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ReservedS81[2]|0xFF
--
2.39.0.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread