From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 4ABDC740038 for ; Sat, 16 Sep 2023 15:59:41 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=F7SNPZC/k9aHSwEHSGmi+lqH8SNU9U0Wxjit+iY1Hus=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1694879979; v=1; b=jvHtJgujix4RhePsP81s6jYG1MlALk8rbFjigxMUHUTZFqAJp3EfIngvcYvQvVODAyYTooAW +r8Ec+sz1SnlRc+fvlagnAfjkQ+xDJKDCSmB4u/yp+wwdPmmzDxB6/igFXteHYfxGFYrD+vYWgR 4NdOKpSYdf8iOdo8ebf+C+gY= X-Received: by 127.0.0.2 with SMTP id qHUkYY7687511xg7FvLNQkoK; Sat, 16 Sep 2023 08:59:39 -0700 X-Received: from m12.mail.163.com (m12.mail.163.com [220.181.12.196]) by mx.groups.io with SMTP id smtpd.web10.14137.1694879976789673029 for ; Sat, 16 Sep 2023 08:59:38 -0700 X-Received: from rv-uefi.. (unknown [211.87.236.31]) by zwqz-smtp-mta-g5-1 (Coremail) with SMTP id _____wAHw+Lf0AVlMAD7CA--.586S2; Sat, 16 Sep 2023 23:59:27 +0800 (CST) From: caiyuqing_hz@163.com To: devel@edk2.groups.io Cc: Sunil V L , Leif Lindholm , Michael D Kinney , USER0FISH , Inochi Amaoto Subject: [edk2-devel] [PATCH edk2-platforms v4 0/8] EDK2 on RISC-V Sophgo SG2042 platform Date: Sat, 16 Sep 2023 23:59:26 +0800 Message-Id: MIME-Version: 1.0 X-CM-TRANSID: _____wAHw+Lf0AVlMAD7CA--.586S2 X-Coremail-Antispam: 1Uf129KBjvAXoW3ur1UXFWDCrykCF4DtF1UWrg_yoW8JryxWo WkGr92v3WUCr15A3s7Cws3G3y8W3ZrCr4UJr4jyF4DZFZ09rZFqr17Kw47uF9akry8Wrnr A34jqw1xWFsIq34fn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxUcJ3vUUUUU X-Originating-IP: [211.87.236.31] X-CM-SenderInfo: 5fdl535tlqwslk26il2tof0z/1tbiSAPsxV+Fh910NQAAsj Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,caiyuqing_hz@163.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: EfbuzsvLahB1mlMpaFv68imLx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=jvHtJguj; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=163.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: caiyuqing379 Description: Deploy EDK2 to run on 64-core CPU under RISC-V architecture, and successfully boot to OS. Implementation can be seen at: https://github.com/AII-SDU/edk2-platforms/tree/devel-Sophgo/SG2042Pkg/Platform/Sophgo. Current progress and status: 1.Adopted the scheme of separating OpenSBI and EDK2. It follows PEI less design. 2.The startup process is roughly: ZSBL + FSBL + OpenSBI + EDK2 + GRUB + Linux OS. - The boot medium is SD card, where ZSBL is loaded and executed by an auxiliary MCU, performing initial initialization operations such as DIMM initialization. - FSBL then continues with further initialization tasks. - OpenSBI is used to initialize the hardware platform and kernel. Additionally, we have upgraded the OpenSBI from version V0.9 to V1.2 to align with community progress. - EDK2, running in S-mode, handles configuration operations, primarily completing the SD card driver in the DXE stage, while PCIe driver testing and follow-up work are planned. - GRUB2 is used to load the operating system, facilitating subsequent operations. 3.Clang toolchain support Build the port using the CLANGDWARF toolchain (clang version 18.0.0). It is able to build successfully and the built binary can boot Linux OS normally. Testing: 1.Test the project on Sophgo SG2042 EVB and be able to boot Linux OS. 2.Test the project on Milk V Pioneer board and is able to boot into the UEFI shell. However, the SD card driver is unable to properly recognize all partitions and boot Linux OS. Current limitation: 1.PCIE driver is not supported. 2.MMU support SG2042 (Xuantie C920) MMU can be enabled in SV39 mode. Introduce the PCD variable PcdForceNoMMU to disable MMU configuration. Currently, enabling MMU results in a timeout for reading data blocks from the SD card, So MMU is disabled by default. Patch Revision History: Patch v1: The patch series can be seen at: https://edk2.groups.io/g/devel/message/107885 (Between message 107885 and message 107893, total of nine patches) The patch series provides the following main features: 1.The patch 1 use standard SMBIOS modules. 2.The patch 2 copy RISC-V MMU Library. SG2042 (Xuantie C920) MMU can be enabled in SV39 mode, but there are bugs with exception handling and MMC that need to be fixed, so MMU is disabled. Add this library is to ensure build successfully. So the RiscVConfigureMmu function was modified in patch 2 to set the satp mode to SATP_MODE_OFF. 3.The SEC module in patch 5 has made a few changes compared to RiscVVirt. The memory space size of SG2042 EVB is determined by the number and size of DDRs inserted on the board. All memory in RiscVVirt is added in the SEC moudle, using InitializeRamRegions to initialize the system memory space for each memory node separately, but the actual MemoryLength is only the size of the first memory node. Therefore, InitializeRamRegions is called only once to initialize the total system memory. 4.Use opensbi v1.2 instead of the latest v1.3 The opensbi for SG2042 is maintained by Sophgo and there are issues with using opensbi v1.3. Currently, Sophgo has plans to submit patches upstream and is in the process of upgrading. Patch v2: The patch series can be seen at: https://edk2.groups.io/g/devel/message/108216 (Between message 108210 and message 108218, total of nine patches) The patch series provides the following updates: 1.To avoid further duplication, the patch 2 adds a PlatformUpdateMmuDxe which contains two main functions. The first function is to change the page attributes corresponding to memory. C920 has five customizable page attributes that control whether the page is Strong order(SO), Cacheable(C), Bufferable(B), Shareable(SH), Trustable(Sec). This driver modifies the page table attributes to avoid exceptions based on the memory attributes of the C920. Update Read/Write /Strong Order attribute for memory mapped IO. And update Read/Write/Execute/Sharable/Cacheable attribute for system memory. The second function is to introduces a PCD variable PcdForceNoMMU to disable MMU configuration. Currently, enabling MMU results in a timeout for reading data blocks from the SD card, So MMU is disabled by default. 2.No change in patch 5's memory initialization method. It's not guaranteed that you won't hit grub overflow errors with this method, but using this method at least masks the problem for the time being. Patch v3: The patch series can be seen at: https://edk2.groups.io/g/devel/message/108376 (Between message 108376 and message 108384, total of nine patches) The patch series provides the following updates: 1.Remove firmware context Referring to Andrei's branch, in the SEC module, the patch 5 avoids getting the FDT pointer from the firmware. 2.Blurb The patch 0 adds some descriptions in Blurb to explain the current status, testing situation, and limitations of the project. And added a link to the public git in Blurb at https://github.com/AII-SDU/edk2-platforms/tree/devel-Sophgo/SG2042Pkg/Platform/Sophgo 3.Milk-V Pioneer board Running EDK2 on the Milk-V Pioneer board boots into UEFI shell normally, but the SD driver can't recognize all the partitions correctly and can't boot Linux OS normally. 4.Layout Based on Leif's comment, we moved most of the code in the port from Platform/Sophgo/SG2042Pkg/ to Silicon/Sophgo/SG2042Pkg/ 5.Clang toolchain support Our team tried to build the port using the CLANGDWARF toolchain (clang version 18.0.0), and updated README for CLANGDWARF support. It's able to build successfully but the built binary is not fully work. Patch v4: The patch series provides the following updates: 1.The patch 3&4 fix INF_VERSION to 1.27. 2.Some of the code in patch 3&4 is based on the open source code provided by Sophgo, which is licensed under bds-3. The patch 3&4 change license from BDS-3 to BDS-2 by confirming with Sophgo. 3.Adding a comment to the patch 5 indicates that OpenSBI 1.3/1.3.1 should be used, which fixed the no-mapping issue. The current OpenSBI provided by Sophgo is v1.2, and the dt provided by Sophgo does not use no-map, v1.3 is being actively upgraded. 4.This version already supports Clang toolchain, which can be seen at README. Signed-off-by: caiyuqing379 Co-authored-by: USER0FISH Cc: dahogn Cc: meng-cz Cc: yli147 Cc: ChaiEvan Cc: Sunil V L Cc: Leif Lindholm Cc: Michael D Kinney caiyuqing379 (8): Sophgo/SG2042Pkg: Add SmbiosPlatformDxe module. Sophgo/SG2042Pkg: Add PlatformUpdateMmuDxe module. Sophgo/SG2042Pkg: Add Sophgo SDHCI driver. Sophgo/SG2042Pkg: Add base MMC driver. Sophgo/SG2042Pkg: Add SEC module. Sophgo/SG2042_EVB_Board: Add Sophgo SG2042 platform. Sophgo/SG2042Pkg: Add SG2042Pkg. Sophgo/SG2042Pkg: Add platform readme and document. Platform/Sophgo/SG2042_EVB_Board/SG2042.dec | 19 + Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec | 35 + Platform/Sophgo/SG2042_EVB_Board/SG2042.dsc | 548 +++++++++++ Platform/Sophgo/SG2042_EVB_Board/SG2042.fdf | 248 +++++ .../SG2042Pkg/Drivers/MmcDxe/MmcDxe.inf | 46 + .../PlatformUpdateMmuDxe.inf | 34 + .../SG2042Pkg/Drivers/SdHostDxe/SdHostDxe.inf | 47 + .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 39 + Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 ++ Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/Mmc.h | 513 ++++++++++ .../SG2042Pkg/Drivers/SdHostDxe/SdHci.h | 309 ++++++ Silicon/Sophgo/SG2042Pkg/Include/MmcHost.h | 225 +++++ Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h | 104 ++ .../SG2042Pkg/Drivers/MmcDxe/ComponentName.c | 156 +++ .../SG2042Pkg/Drivers/MmcDxe/Diagnostics.c | 323 ++++++ Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/Mmc.c | 527 ++++++++++ .../SG2042Pkg/Drivers/MmcDxe/MmcBlockIo.c | 646 ++++++++++++ .../SG2042Pkg/Drivers/MmcDxe/MmcDebug.c | 194 ++++ .../Drivers/MmcDxe/MmcIdentification.c | 719 ++++++++++++++ .../PlatformUpdateMmuDxe.c | 593 +++++++++++ .../SG2042Pkg/Drivers/SdHostDxe/SdHci.c | 929 ++++++++++++++++++ .../SG2042Pkg/Drivers/SdHostDxe/SdHostDxe.c | 448 +++++++++ .../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 805 +++++++++++++++ Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 + Silicon/Sophgo/SG2042Pkg/Sec/Memory.c | 348 +++++++ Silicon/Sophgo/SG2042Pkg/Sec/Platform.c | 130 +++ Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c | 115 +++ Platform/Sophgo/About_Sophgo_platform.md | 39 + .../Documents/Media/EDK2_SDU_Programme.png | Bin 0 -> 59830 bytes .../Sophgo/Documents/Media/SG2042_CPU.png | Bin 0 -> 806062 bytes .../Documents/Media/Sophgo_SG2042_EVB.png | Bin 0 -> 1445528 bytes Platform/Sophgo/Maintainers.md | 107 ++ Platform/Sophgo/SG2042_EVB_Board/Readme.md | 100 ++ .../Sophgo/SG2042_EVB_Board/SG2042.fdf.inc | 62 ++ .../Sophgo/SG2042_EVB_Board/VarStore.fdf.inc | 77 ++ Silicon/Sophgo/SG2042Pkg/SG2042Pkg.uni | 13 + Silicon/Sophgo/SG2042Pkg/SG2042PkgExtra.uni | 12 + Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 + 38 files changed, 8625 insertions(+) create mode 100644 Platform/Sophgo/SG2042_EVB_Board/SG2042.dec create mode 100644 Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec create mode 100644 Platform/Sophgo/SG2042_EVB_Board/SG2042.dsc create mode 100644 Platform/Sophgo/SG2042_EVB_Board/SG2042.fdf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDxe.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/SdHostDxe/SdHostDxe.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/Mmc.h create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/SdHostDxe/SdHci.h create mode 100644 Silicon/Sophgo/SG2042Pkg/Include/MmcHost.h create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/ComponentName.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/Diagnostics.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/Mmc.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcBlockIo.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcIdentification.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/PlatformUpdateMmuDxe/PlatformUpdateMmuDxe.c create mode 100755 Silicon/Sophgo/SG2042Pkg/Drivers/SdHostDxe/SdHci.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/SdHostDxe/SdHostDxe.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Memory.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Platform.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c create mode 100644 Platform/Sophgo/About_Sophgo_platform.md create mode 100644 Platform/Sophgo/Documents/Media/EDK2_SDU_Programme.png create mode 100644 Platform/Sophgo/Documents/Media/SG2042_CPU.png create mode 100644 Platform/Sophgo/Documents/Media/Sophgo_SG2042_EVB.png create mode 100644 Platform/Sophgo/Maintainers.md create mode 100644 Platform/Sophgo/SG2042_EVB_Board/Readme.md create mode 100644 Platform/Sophgo/SG2042_EVB_Board/SG2042.fdf.inc create mode 100644 Platform/Sophgo/SG2042_EVB_Board/VarStore.fdf.inc create mode 100644 Silicon/Sophgo/SG2042Pkg/SG2042Pkg.uni create mode 100644 Silicon/Sophgo/SG2042Pkg/SG2042PkgExtra.uni create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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