[edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Abdul Lateef Attar via groups.io]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

Resending the patch with updated Cc list.

PR: https://github.com/tianocore/edk2/pull/5269

V2: delta changes
 - Added additional check apart from supported CPUID extneded number.
 - removed EFIAPI

Implements AMD extended toplogy.
Adds CPUID macro
update APIC library to use new exteded cpuid.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

Abdul Lateef Attar (2):
  MdePkg: Adds AMD Extended CPU topology CPUID
  UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology

 MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
 .../Library/BaseXApicLib/BaseXApicLib.c       | 126 +++++++++++++++++-
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126 +++++++++++++++++-
 3 files changed, 272 insertions(+), 3 deletions(-)

-- 
2.34.1



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[edk2-devel] [PATCH RESEND v2 1/2] MdePkg: Adds AMD Extended CPU topology CPUID

[Abdul Lateef Attar via groups.io]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

Adds cpuid macro for AMD extended CPU topology.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 MdePkg/Include/Register/Amd/Cpuid.h | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/Amd/Cpuid.h
index 44394fc7a4..add43c40aa 100644
--- a/MdePkg/Include/Register/Amd/Cpuid.h
+++ b/MdePkg/Include/Register/Amd/Cpuid.h
@@ -6,7 +6,7 @@
   If a register returned is a single 32-bit value, then a data structure is
   not provided for that register.
 
-  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+  Copyright (c) 2017 - 2024, Advanced Micro Devices. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -42,6 +42,27 @@ CPUID Signature Information
 /// @}
 ///
 
+/**
+  CPUID Extended Topology Enumeration
+
+  @note
+  Reference: AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions,
+             Revision 3.35 Appendix E,
+  E.4.24 Function 8000_0026—Extended CPU Topology:
+    CPUID Fn8000_0026 reports extended topology information for logical processors, including
+    asymmetric and heterogenous topology descriptions. Individual logical processors may report
+    different values in systems with asynchronous and heterogeneous topologies.
+    The topology level is selected by the value passed to the instruction in ECX. To discover the topology
+    of a system, software should execute CPUID Fn8000_0026 with increasing ECX values, starting with
+    a value of zero, until the returned hierarchy level type (CPUID Fn8000_0026_ECX[LevelType]) is
+    equal to zero. It is not guaranteed that all topology level types are present in the system
+
+  @param   EAX  AMD_CPUID_EXTENDED_TOPOLOGY   (0x80000026)
+  @param   ECX  Level number
+
+**/
+#define AMD_CPUID_EXTENDED_TOPOLOGY  0x80000026
+
 /**
   CPUID Extended Processor Signature and Features
 
-- 
2.34.1



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[edk2-devel] [PATCH RESEND v2 2/2] UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology

[Abdul Lateef Attar via groups.io]

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

This patch adds support for AMD's new extended topology.
If processor supports CPUID 80000026 leaf then obtain
the topology information using new method.

Algorithm:
  if CPUID is AMD:
    then
     check for AMD's extended cpu tology leaf.
     if yes
       then extract cpu tology based on
       AMD programmer manual's instruction.
     else
       then fallback to existing topology function.
    endif
  endif

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
---
 .../Library/BaseXApicLib/BaseXApicLib.c       | 126 +++++++++++++++++-
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126 +++++++++++++++++-
 2 files changed, 250 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index efb9d71ca1..c4457d98b3 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports xAPIC mode only.
 
   Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
-  Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
+  Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -1157,6 +1157,125 @@ GetProcessorLocationByApicId (
   }
 }
 
+/**
+  Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor family.
+
+  The algorithm assumes the target system has symmetry across physical
+  package boundaries with respect to the number of threads per core, number of
+  cores per module, number of modules per die, number
+  of dies per package.
+
+  @param[in]   InitialApicId Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Die           Returns the processor die ID.
+  @param[out]  Tile          Returns zero.
+  @param[out]  Module        Returns the processor module ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+AmdGetProcessorLocation2ByApicId (
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Die      OPTIONAL,
+  OUT UINT32  *Tile     OPTIONAL,
+  OUT UINT32  *Module   OPTIONAL,
+  OUT UINT32  *Core     OPTIONAL,
+  OUT UINT32  *Thread   OPTIONAL
+  )
+{
+  CPUID_EXTENDED_TOPOLOGY_EAX  ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX  ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX  ExtendedTopologyEcx;
+  UINT32                       MaxExtendedCpuIdIndex;
+  UINT32                       TopologyLevel;
+  UINT32                       PreviousLevel;
+  UINT32                       Data;
+
+  if (Die != NULL) {
+    *Die = 0;
+  }
+
+  if (Tile != NULL) {
+    *Tile = 0;
+  }
+
+  if (Module != NULL) {
+    *Module = 0;
+  }
+
+  PreviousLevel = 0;
+  TopologyLevel = 0;
+
+  /// Check if extended toplogy supported
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
+  if (MaxExtendedCpuIdIndex >= AMD_CPUID_EXTENDED_TOPOLOGY) {
+    do {
+      AsmCpuidEx (
+        AMD_CPUID_EXTENDED_TOPOLOGY,
+        TopologyLevel,
+        &ExtendedTopologyEax.Uint32,
+        &ExtendedTopologyEbx.Uint32,
+        &ExtendedTopologyEcx.Uint32,
+        NULL
+        );
+
+      if (ExtendedTopologyEbx.Bits.LogicalProcessors == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
+        /// if this fails at first level
+        /// then will fall back to non-extended topology
+        break;
+      }
+
+      Data  = InitialApicId >> PreviousLevel;
+      Data &= (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLevel)) - 1;
+
+      switch (ExtendedTopologyEcx.Bits.LevelType) {
+        case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT:
+          if (Thread != NULL) {
+            *Thread = Data;
+          }
+
+          break;
+        case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE:
+          if (Core != NULL) {
+            *Core = Data;
+          }
+
+          break;
+        case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE:
+          if (Module != NULL) {
+            *Module = Data;
+          }
+
+          break;
+        case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE:
+          if (Die != NULL) {
+            *Die = Data;
+          }
+
+          break;
+        default:
+          break;
+      }
+
+      TopologyLevel++;
+      PreviousLevel = ExtendedTopologyEax.Bits.ApicIdShift;
+    } while (ExtendedTopologyEbx.Bits.LogicalProcessors != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+
+    if (Package != NULL) {
+      *Package = InitialApicId >> PreviousLevel;
+    }
+  }
+
+  /// If extended topology CPUID is not supported
+  /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return 0).
+  if (TopologyLevel == 0) {
+    GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
+  }
+
+  return;
+}
+
 /**
   Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
 
@@ -1194,6 +1313,11 @@ GetProcessorLocation2ByApicId (
   UINT32                       Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
   UINT32                       *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
 
+  if (StandardSignatureIsAuthenticAMD ()) {
+    AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, Module, Core, Thread);
+    return;
+  }
+
   for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
     Bits[LevelType] = 0;
   }
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index c0a8475833..0560d38ce5 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,7 +5,7 @@
   which have xAPIC and x2APIC modes.
 
   Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
-  Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
+  Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -1396,6 +1396,125 @@ GetProcessorLocationByApicId (
   }
 }
 
+/**
+  Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor family.
+
+  The algorithm assumes the target system has symmetry across physical
+  package boundaries with respect to the number of threads per core, number of
+  cores per module, number of modules per die, number
+  of dies per package.
+
+  @param[in]   InitialApicId Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Die           Returns the processor die ID.
+  @param[out]  Tile          Returns zero.
+  @param[out]  Module        Returns the processor module ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+AmdGetProcessorLocation2ByApicId (
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Die      OPTIONAL,
+  OUT UINT32  *Tile     OPTIONAL,
+  OUT UINT32  *Module   OPTIONAL,
+  OUT UINT32  *Core     OPTIONAL,
+  OUT UINT32  *Thread   OPTIONAL
+  )
+{
+  CPUID_EXTENDED_TOPOLOGY_EAX  ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX  ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX  ExtendedTopologyEcx;
+  UINT32                       MaxExtendedCpuIdIndex;
+  UINT32                       TopologyLevel;
+  UINT32                       PreviousLevel;
+  UINT32                       Data;
+
+  if (Die != NULL) {
+    *Die = 0;
+  }
+
+  if (Tile != NULL) {
+    *Tile = 0;
+  }
+
+  if (Module != NULL) {
+    *Module = 0;
+  }
+
+  PreviousLevel = 0;
+  TopologyLevel = 0;
+
+  /// Check if extended toplogy supported
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
+  if (MaxExtendedCpuIdIndex >= AMD_CPUID_EXTENDED_TOPOLOGY) {
+    do {
+      AsmCpuidEx (
+        AMD_CPUID_EXTENDED_TOPOLOGY,
+        TopologyLevel,
+        &ExtendedTopologyEax.Uint32,
+        &ExtendedTopologyEbx.Uint32,
+        &ExtendedTopologyEcx.Uint32,
+        NULL
+        );
+
+      if (ExtendedTopologyEbx.Bits.LogicalProcessors == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
+        /// if this fails at first level
+        /// then will fall back to non-extended topology
+        break;
+      }
+
+      Data  = InitialApicId >> PreviousLevel;
+      Data &= (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLevel)) - 1;
+
+      switch (ExtendedTopologyEcx.Bits.LevelType) {
+        case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT:
+          if (Thread != NULL) {
+            *Thread = Data;
+          }
+
+          break;
+        case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE:
+          if (Core != NULL) {
+            *Core = Data;
+          }
+
+          break;
+        case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE:
+          if (Module != NULL) {
+            *Module = Data;
+          }
+
+          break;
+        case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE:
+          if (Die != NULL) {
+            *Die = Data;
+          }
+
+          break;
+        default:
+          break;
+      }
+
+      TopologyLevel++;
+      PreviousLevel = ExtendedTopologyEax.Bits.ApicIdShift;
+    } while (ExtendedTopologyEbx.Bits.LogicalProcessors != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+
+    if (Package != NULL) {
+      *Package = InitialApicId >> PreviousLevel;
+    }
+  }
+
+  /// If extended topology CPUID is not supported
+  /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return 0).
+  if (TopologyLevel == 0) {
+    GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
+  }
+
+  return;
+}
+
 /**
   Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
 
@@ -1433,6 +1552,11 @@ GetProcessorLocation2ByApicId (
   UINT32                       Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
   UINT32                       *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
 
+  if (StandardSignatureIsAuthenticAMD ()) {
+    AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, Module, Core, Thread);
+    return;
+  }
+
   for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
     Bits[LevelType] = 0;
   }
-- 
2.34.1



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Re: [edk2-devel] [PATCH RESEND v2 1/2] MdePkg: Adds AMD Extended CPU topology CPUID

[Michael D Kinney]

Acked-by: Michael D Kinney <michael.d.kinney@intel.com>

> -----Original Message-----
> From: Abdul Lateef Attar <abdattar@amd.com>
> Sent: Wednesday, January 17, 2024 7:54 PM
> To: devel@edk2.groups.io
> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
> Liu, Zhiguang <zhiguang.liu@intel.com>; Ni, Ray <ray.ni@intel.com>;
> Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann
> <kraxel@redhat.com>
> Subject: [PATCH RESEND v2 1/2] MdePkg: Adds AMD Extended CPU topology
> CPUID
> 
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> Adds cpuid macro for AMD extended CPU topology.
> 
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> ---
>  MdePkg/Include/Register/Amd/Cpuid.h | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/MdePkg/Include/Register/Amd/Cpuid.h
> b/MdePkg/Include/Register/Amd/Cpuid.h
> index 44394fc7a4..add43c40aa 100644
> --- a/MdePkg/Include/Register/Amd/Cpuid.h
> +++ b/MdePkg/Include/Register/Amd/Cpuid.h
> @@ -6,7 +6,7 @@
>    If a register returned is a single 32-bit value, then a data
> structure is
>    not provided for that register.
> 
> -  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
> +  Copyright (c) 2017 - 2024, Advanced Micro Devices. All rights
> reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> @@ -42,6 +42,27 @@ CPUID Signature Information
>  /// @}
>  ///
> 
> +/**
> +  CPUID Extended Topology Enumeration
> +
> +  @note
> +  Reference: AMD64 Architecture Programmer’s Manual Volume 3: General-
> Purpose and System Instructions,
> +             Revision 3.35 Appendix E,
> +  E.4.24 Function 8000_0026—Extended CPU Topology:
> +    CPUID Fn8000_0026 reports extended topology information for logical
> processors, including
> +    asymmetric and heterogenous topology descriptions. Individual
> logical processors may report
> +    different values in systems with asynchronous and heterogeneous
> topologies.
> +    The topology level is selected by the value passed to the
> instruction in ECX. To discover the topology
> +    of a system, software should execute CPUID Fn8000_0026 with
> increasing ECX values, starting with
> +    a value of zero, until the returned hierarchy level type (CPUID
> Fn8000_0026_ECX[LevelType]) is
> +    equal to zero. It is not guaranteed that all topology level types
> are present in the system
> +
> +  @param   EAX  AMD_CPUID_EXTENDED_TOPOLOGY   (0x80000026)
> +  @param   ECX  Level number
> +
> +**/
> +#define AMD_CPUID_EXTENDED_TOPOLOGY  0x80000026
> +
>  /**
>    CPUID Extended Processor Signature and Features
> 
> --
> 2.34.1



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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Abdul Lateef Attar via groups.io]

Gentle reminder, please review the patch series.

On 18-01-2024 09:24, Abdul Lateef Attar via groups.io wrote:
> Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
>
>
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>
> Resending the patch with updated Cc list.
>
> PR: https://github.com/tianocore/edk2/pull/5269
>
> V2: delta changes
>   - Added additional check apart from supported CPUID extneded number.
>   - removed EFIAPI
>
> Implements AMD extended toplogy.
> Adds CPUID macro
> update APIC library to use new exteded cpuid.
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>
> Abdul Lateef Attar (2):
>    MdePkg: Adds AMD Extended CPU topology CPUID
>    UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology
>
>   MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
>   .../Library/BaseXApicLib/BaseXApicLib.c       | 126 +++++++++++++++++-
>   .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126 +++++++++++++++++-
>   3 files changed, 272 insertions(+), 3 deletions(-)
>
> --
> 2.34.1
>
>
>
> 
>
>


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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Ni, Ray]

Acked-by: Ray Ni <ray.ni@intel.com>

+ Tom

Thanks,
Ray
> -----Original Message-----
> From: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>
> Sent: Thursday, January 25, 2024 1:02 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Ni,
> Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd
> Hoffmann <kraxel@redhat.com>
> Subject: Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended
> topology
> 
> Gentle reminder, please review the patch series.
> 
> On 18-01-2024 09:24, Abdul Lateef Attar via groups.io wrote:
> > Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> >
> >
> > From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> >
> > Resending the patch with updated Cc list.
> >
> > PR: https://github.com/tianocore/edk2/pull/5269
> >
> > V2: delta changes
> >   - Added additional check apart from supported CPUID extneded number.
> >   - removed EFIAPI
> >
> > Implements AMD extended toplogy.
> > Adds CPUID macro
> > update APIC library to use new exteded cpuid.
> >
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Gerd Hoffmann <kraxel@redhat.com>
> > Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> >
> > Abdul Lateef Attar (2):
> >    MdePkg: Adds AMD Extended CPU topology CPUID
> >    UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu
> topology
> >
> >   MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
> >   .../Library/BaseXApicLib/BaseXApicLib.c       | 126
> +++++++++++++++++-
> >   .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126
> +++++++++++++++++-
> >   3 files changed, 272 insertions(+), 3 deletions(-)
> >
> > --
> > 2.34.1
> >
> >
> >
> > 
> >
> >


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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Lendacky, Thomas via groups.io]

On 1/25/24 04:20, Ni, Ray via groups.io wrote:
> Acked-by: Ray Ni <ray.ni@intel.com>
> 
> + Tom

Looks good to me. Should AmdGetProcessorLocation2ByApicId() be STATIC?

Not asking for this patch series, but there is a lot of duplicated code 
between the two APIC libraries. It would be nice if there was a way to 
have a common file where just a single copy of the duplicated code could live.

Acked-by: Tom Lendacky <thomas.lendacky@amd.com>

Thanks,
Tom

> 
> Thanks,
> Ray
>> -----Original Message-----
>> From: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>
>> Sent: Thursday, January 25, 2024 1:02 PM
>> To: devel@edk2.groups.io
>> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao
>> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Ni,
>> Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd
>> Hoffmann <kraxel@redhat.com>
>> Subject: Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended
>> topology
>>
>> Gentle reminder, please review the patch series.
>>
>> On 18-01-2024 09:24, Abdul Lateef Attar via groups.io wrote:
>>> Caution: This message originated from an External Source. Use proper
>> caution when opening attachments, clicking links, or responding.
>>>
>>>
>>> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>>>
>>> Resending the patch with updated Cc list.
>>>
>>> PR: https://github.com/tianocore/edk2/pull/5269
>>>
>>> V2: delta changes
>>>    - Added additional check apart from supported CPUID extneded number.
>>>    - removed EFIAPI
>>>
>>> Implements AMD extended toplogy.
>>> Adds CPUID macro
>>> update APIC library to use new exteded cpuid.
>>>
>>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>>> Cc: Liming Gao <gaoliming@byosoft.com.cn>
>>> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>>> Cc: Ray Ni <ray.ni@intel.com>
>>> Cc: Rahul Kumar <rahul1.kumar@intel.com>
>>> Cc: Gerd Hoffmann <kraxel@redhat.com>
>>> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>>>
>>> Abdul Lateef Attar (2):
>>>     MdePkg: Adds AMD Extended CPU topology CPUID
>>>     UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu
>> topology
>>>
>>>    MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
>>>    .../Library/BaseXApicLib/BaseXApicLib.c       | 126
>> +++++++++++++++++-
>>>    .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126
>> +++++++++++++++++-
>>>    3 files changed, 272 insertions(+), 3 deletions(-)
>>>
>>> --
>>> 2.34.1
>>>
>>>
>>>
>>>
>>>
>>>
> 
> 
> 
> 
> 


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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Abdul Lateef Attar via groups.io]

Hi All,

     Thanks for reviewing the patch, I had re-based the patch and added 
"Acked-by".

Please take a look and merge the PR.

https://github.com/tianocore/edk2/pull/5269

Thanks

AbduL

On 25-01-2024 21:51, Tom Lendacky wrote:
> On 1/25/24 04:20, Ni, Ray via groups.io wrote:
>> Acked-by: Ray Ni <ray.ni@intel.com>
>>
>> + Tom
>
> Looks good to me. Should AmdGetProcessorLocation2ByApicId() be STATIC?

[Abdul] I think its okay to not have STATIC, as I can see other local 
functions also doesn't have STATIC prefix.

>
> Not asking for this patch series, but there is a lot of duplicated 
> code between the two APIC libraries. It would be nice if there was a 
> way to have a common file where just a single copy of the duplicated 
> code could live.

[Abdul] Agree lot of duplicate code, we can combine BaseXApic and 
BaseXApicX2Apic library to single library and have separate INF file 
with shared source file.

>
> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
>
> Thanks,
> Tom
>
>>
>> Thanks,
>> Ray
>>> -----Original Message-----
>>> From: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>
>>> Sent: Thursday, January 25, 2024 1:02 PM
>>> To: devel@edk2.groups.io
>>> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Liming Gao
>>> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Ni,
>>> Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd
>>> Hoffmann <kraxel@redhat.com>
>>> Subject: Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended
>>> topology
>>>
>>> Gentle reminder, please review the patch series.
>>>
>>> On 18-01-2024 09:24, Abdul Lateef Attar via groups.io wrote:
>>>> Caution: This message originated from an External Source. Use proper
>>> caution when opening attachments, clicking links, or responding.
>>>>
>>>>
>>>> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>>>>
>>>> Resending the patch with updated Cc list.
>>>>
>>>> PR: https://github.com/tianocore/edk2/pull/5269
>>>>
>>>> V2: delta changes
>>>>    - Added additional check apart from supported CPUID extneded 
>>>> number.
>>>>    - removed EFIAPI
>>>>
>>>> Implements AMD extended toplogy.
>>>> Adds CPUID macro
>>>> update APIC library to use new exteded cpuid.
>>>>
>>>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>>>> Cc: Liming Gao <gaoliming@byosoft.com.cn>
>>>> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>>>> Cc: Ray Ni <ray.ni@intel.com>
>>>> Cc: Rahul Kumar <rahul1.kumar@intel.com>
>>>> Cc: Gerd Hoffmann <kraxel@redhat.com>
>>>> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
>>>>
>>>> Abdul Lateef Attar (2):
>>>>     MdePkg: Adds AMD Extended CPU topology CPUID
>>>>     UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu
>>> topology
>>>>
>>>>    MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
>>>>    .../Library/BaseXApicLib/BaseXApicLib.c       | 126
>>> +++++++++++++++++-
>>>> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126
>>> +++++++++++++++++-
>>>>    3 files changed, 272 insertions(+), 3 deletions(-)
>>>>
>>>> -- 
>>>> 2.34.1
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>
>>
>> 
>>
>>


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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Laszlo Ersek]

On 1/18/24 04:54, Abdul Lateef Attar via groups.io wrote:
> From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> Resending the patch with updated Cc list.
> 
> PR: https://github.com/tianocore/edk2/pull/5269
> 
> V2: delta changes
>  - Added additional check apart from supported CPUID extneded number.
>  - removed EFIAPI
> 
> Implements AMD extended toplogy.
> Adds CPUID macro
> update APIC library to use new exteded cpuid.
> 
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
> 
> Abdul Lateef Attar (2):
>   MdePkg: Adds AMD Extended CPU topology CPUID
>   UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology
> 
>  MdePkg/Include/Register/Amd/Cpuid.h           |  23 +++-
>  .../Library/BaseXApicLib/BaseXApicLib.c       | 126 +++++++++++++++++-
>  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c   | 126 +++++++++++++++++-
>  3 files changed, 272 insertions(+), 3 deletions(-)
> 

series merged via <https://github.com/tianocore/edk2/pull/5326>, commits

     1  d14526372d6c MdePkg: Adds AMD Extended CPU topology CPUID
     2  0e9b124f9c67 UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology



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Re: [edk2-devel] [PATCH RESEND v2 0/2] AMD CPU extended topology

[Laszlo Ersek]

On 1/31/24 05:54, Abdul Lateef Attar via groups.io wrote:
> Hi All,
> 
>     Thanks for reviewing the patch, I had re-based the patch and added
> "Acked-by".
> 
> Please take a look and merge the PR.
> 
> https://github.com/tianocore/edk2/pull/5269

(repeating here too:)

series merged via <https://github.com/tianocore/edk2/pull/5326>, commits

     1  d14526372d6c MdePkg: Adds AMD Extended CPU topology CPUID
     2  0e9b124f9c67 UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology




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