From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC0A3210D439A for ; Wed, 1 Aug 2018 18:46:29 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id z8-v6so304009pgu.8 for ; Wed, 01 Aug 2018 18:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=DdLfCb7uEmRjXuZ9AcJJMDXF4mxmp4sq45SIzbMEEKA=; b=kS5ipvPvtgowbpS7Fjjaqh1u/Zt5R/AVP2Kue426imzVczbxl++kCFPZjLCV5rJhtn vJJLQpRmPrYy6fSZXx0xR8sUI4Q0gXMy9HM3jVO9ckmDlAZZfTOpx2YIaR0KEeat/5xf Arvdaw4WOWQ4CZ3iuvImDvQ8ucaLwW1NPyA08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=DdLfCb7uEmRjXuZ9AcJJMDXF4mxmp4sq45SIzbMEEKA=; b=n0Z7cgMRTKjA+uW2Ad1HT9uCMr/rAA0eqAjhmTq19f9qWuaY+3EZYPJwCxDGBF2AAA yi8hYL+6a9mccsCvSATRZf6M5NWT+YlG5fVC3dRKEqPZwb1cGAd3c6Fg48etLt0fqjll 7I1aonSdc9nsKjvQOJfRihtttbDe6zBFOt52jTo1vhusnmEWnQhgflNLNIOc59cncuMq 0QYXyuMwUlO6PFpC6HU4OlY/TZxDMEcgn8jRaFtJouCdMM0JemBnaXwZT7WtSted2E2B h157YhtkyDoaMkpoFuIZp3//soI2CNK+lL0I5EV5/lgmm5DKv6BLxXCJK0kjumxc2/Gn YDkw== X-Gm-Message-State: AOUpUlFbiUjP8GdzhliMFXPqUSFAym7TZEHNx5/ups/LrLYjH8N0CK88 J+eeo29+5NzIhqA9YK5Y5fywJQ== X-Google-Smtp-Source: AAOMgpeM4PlrynC67yuO80pM3Oj5VFPfI9P0NCoZ7raALL+t2kiBLle+XGWaCtyG8ZmGS2qxTT2Cpg== X-Received: by 2002:a62:9849:: with SMTP id q70-v6mr776655pfd.178.1533174388523; Wed, 01 Aug 2018 18:46:28 -0700 (PDT) Received: from [10.95.1.166] ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id d26-v6sm458528pfl.159.2018.08.01.18.46.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Aug 2018 18:46:27 -0700 (PDT) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org References: <20180724070922.63362-1-ming.huang@linaro.org> <20180801215640.5o364hnk2qd4diwn@bivouac.eciton.net> From: Ming Message-ID: Date: Thu, 2 Aug 2018 09:46:13 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20180801215640.5o364hnk2qd4diwn@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v1 00/38] Upload for D06 platform X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Aug 2018 01:46:30 -0000 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit ÔÚ 8/2/2018 5:56 AM, Leif Lindholm дµÀ: > On Tue, Jul 24, 2018 at 03:08:44PM +0800, Ming Huang wrote: >> The major features of this patchset include: >> 1 D06 source code; >> 2 Unify some D0x modules; >> >> This patch set is base on pcihostbridage-v2. >> For compiling D06, add below hunk to edk2-platforms.config >> [d06] >> LONGNAME=HiSilicon D06 >> DSC=Platform/Hisilicon/D06/D06.dsc >> ARCH=AARCH64 > > Very helpful, thank you. > >> >> Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git >> branch: d06-platform-v1 > > Now, I started by trying to compile this, but I run into two issues. > > First, the platform fails to build without FIRMWARE_VER specified on > the command line, since there is an extra '"' in the definition of > PcdFirmwareVersionString. > > Then there is a build fault when generating ACPI tables. I tried to > update to a newer version of acpica-tools, but I still get: > --- > "aarch64-linux-gnu-gcc" -x c -E -include AutoGen.h > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables > -I/work/git/tianocore/Build/D06/DEBUG_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/DEBUG > -I/work/git/edk2/ArmPkg -I/work/git/edk2/ArmPkg/Include > -I/work/git/edk2/ArmPlatformPkg > -I/work/git/edk2/ArmPlatformPkg/Include -I/work/git/edk2/EmbeddedPkg > -I/work/git/edk2/EmbeddedPkg/Include -I/work/git/edk2/MdeModulePkg > -I/work/git/edk2/MdeModulePkg/Include -I/work/git/edk2/MdePkg > -I/work/git/edk2/MdePkg/Include > -I/work/git/edk2/MdePkg/Include/AArch64 > -I/work/git/edk2-platforms/Silicon/Hisilicon > -I/work/git/edk2-platforms/Silicon/Hisilicon/Include > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables > /work/git/tianocore/Build/D06/DEBUG_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.i >> /work/git/tianocore/Build/D06/DEBUG_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.iii > Trim --source-code -l -o > /work/git/tianocore/Build/D06/DEBUG_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/work/git/tianocore/Build/D06/DEBUG_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.iiii"aarch64-linux-gnu-gcc" > -x c -E -include AutoGen.h > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables > -I/work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/DEBUG > -I/work/git/edk2/ArmPkg -I/work/git/edk2/ArmPkg/Include > -I/work/git/edk2/ArmPlatformPkg > -I/work/git/edk2/ArmPlatformPkg/Include -I/work/git/edk2/EmbeddedPkg > -I/work/git/edk2/EmbeddedPkg/Include -I/work/git/edk2/MdeModulePkg > -I/work/git/edk2/MdeModulePkg/Include -I/work/git/edk2/MdePkg > -I/work/git/edk2/MdePkg/Include > -I/work/git/edk2/MdePkg/Include/AArch64 > -I/work/git/edk2-platforms/Silicon/Hisilicon > -I/work/git/edk2-platforms/Silicon/Hisilicon/Include > -I/work/git/edk2-platforms/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables > /work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.i >> /work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.iii > Trim --source-code -l -o > /work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi16Copyright > (c) 2000 - 2018 Intel Corporation > /work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.iiii > 71: [0004] ID Count : 00000100 > Error 6303 - > Integer too large for target ^ (0000000000000100 - max 1 bytes) > > Table Input: > /work/git/tianocore/Build/D06/RELEASE_GCC5/AARCH64/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620/OUTPUT/./Hi1620Iort.iiii > - 1991 lines, 59818 bytes, 68 fields > > Compilation complete. 2 Errors, 0 Warnings, 0 Remarks > --- > > Any ideas what may be causing this? > > / > Leif > I am sorry for the first issue, the modify FIRMWARE_VER patch is add alone just befor send out the patchset. For generating acpi table, I use acpica-tools 20180508 version and it works. I think acpica-tools are not backward compatibility and confused about acpica-tools. Thanks. >> >> Heyi Guo (2): >> Hisilicon/Hi1620: Add ACPI PPTT table >> Platform/Hisilicon/D06: Enable ACPI PPTT >> >> Luqi Jiang (1): >> Hisilicon/D06: add apei driver >> >> Ming Huang (18): >> Silicon/Hisilicon: Modify the MRC interface for other module >> Silicon/Hisilicon: Separate PlatformArch.h >> Hisilicon/D06: Add several basal file for D06 >> Platform/Hisilicon/D06: Add M41T83RealTimeClockLib >> Platform/Hisilicon/D06: Add binary file for D06 >> Hisilicon/D06: Add OemMiscLibD06 >> Silicon/Hisilicon/D06: Wait for all disk ready >> Silicon/Hisilicon/Acpi: Unify HisiAcipPlatformDxe >> Silicon/Hisilicon/I2C: Optimize I2C library >> Platform/Hisilicon/D06: Add OemNicLib >> Hisilicon/D0X: Rename the global variable gDS3231RtcDevice >> Platform/Hisilicon/D06: Add EarlyConfigPeim peim >> Platform/Hisilicon/D06: Add PciHostBridgeLib >> Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h >> Silicon/Hisilicon/Setup: Support SPCR table switch >> Silicon/Hisilicon/setup: Support SMMU switch >> Hisilicon/D06: Add PciPlatformLib >> Platform/Hisilicon/D0x: Update version string to 18.08 >> >> Sun Yuanchen (5): >> Silicon/Hisilicon/D06: Stop watchdog >> Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h >> Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h >> Hisilicon/D0x: Update SMBIOS type9 info >> Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h >> >> Yan Zhang (2): >> Hisilicon/D06: Add Debug Serial Port Init Driver >> Hisilicon/D06: Add ACPI Tables for D06 >> >> Yang XinYi (2): >> Hisilicon/D06: Add Hi1620OemConfigUiLib >> Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP" >> >> ZhenYao (1): >> Silicon/Hisilicon/D06: Modify for close slave core clock. >> >> shaochangliang (6): >> Silicon/Hisilicon/D06: Fix I2C enable fail issue for D06 >> Silicon/Hisilicon/D06: Add I2C delay for HNS auto config >> Silicon/Hisilicon/D06: Optimize HNS config CDR post time >> Platform/Hisilicon/D06: Add OemNicConfig2P Driver >> Hisilicon/D0x: Unify FlashFvbDxe driver >> Silicon/Hisilicon/D06: Add I2C Bus Exception deal function >> >> xulinwei (1): >> Platform/Hisilicon/D06: Add capsule upgrade support >> >> Platform/Hisilicon/D03/D03.dsc | 2 +- >> Platform/Hisilicon/D03/D03.fdf | 6 +- >> .../DS3231RealTimeClockLib.c | 8 +- >> .../OemMiscLib2P/BoardFeature2PHi1610.c | 2 +- >> .../Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 24 + >> .../OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 + >> Platform/Hisilicon/D05/D05.dsc | 2 +- >> Platform/Hisilicon/D05/D05.fdf | 6 +- >> .../Library/OemMiscLibD05/BoardFeatureD05.c | 2 +- >> .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +- >> .../Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + >> .../SystemFirmwareUpdateConfig.ini | 46 + >> Platform/Hisilicon/D06/D06.dec | 29 + >> Platform/Hisilicon/D06/D06.dsc | 492 ++++ >> Platform/Hisilicon/D06/D06.fdf | 444 ++++ >> .../OemNicConfig2PHi1620/OemNicConfig.h | 25 + >> .../OemNicConfig2PHi1620/OemNicConfig2P.c | 71 + >> .../OemNicConfig2PHi1620/OemNicConfig2P.inf | 43 + >> .../SystemFirmwareDescriptor.aslc | 81 + >> .../SystemFirmwareDescriptor.inf | 50 + >> .../SystemFirmwareDescriptorPei.c | 70 + >> .../D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 108 + >> .../EarlyConfigPeim/EarlyConfigPeimD06.inf | 50 + >> .../Hisilicon/D06/Include/Library/CpldD06.h | 37 + >> .../M41T83RealTimeClock.h | 168 ++ >> .../M41T83RealTimeClockLib.c | 603 +++++ >> .../M41T83RealTimeClockLib.inf | 46 + >> .../Library/OemMiscLibD06/BoardFeatureD06.c | 432 ++++ >> .../OemMiscLibD06/BoardFeatureD06Strings.uni | Bin 0 -> 5204 bytes >> .../D06/Library/OemMiscLibD06/OemMiscLibD06.c | 246 ++ >> .../Library/OemMiscLibD06/OemMiscLibD06.inf | 51 + >> .../D06/Library/OemNicLib/OemNicLib.c | 571 +++++ >> .../D06/Library/OemNicLib/OemNicLib.inf | 35 + >> .../PciHostBridgeLib/PciHostBridgeLib.c | 636 ++++++ >> .../PciHostBridgeLib/PciHostBridgeLib.inf | 36 + >> .../Drivers/FlashFvbDxe/FlashFvbDxe.c | 22 +- >> .../Drivers/FlashFvbDxe/FlashFvbDxe.inf | 7 +- >> .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 1 + >> .../HisiAcpiPlatformDxe/UpdateAcpiTable.c | 111 +- >> .../Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +- >> .../Smbios/MemorySubClassDxe/MemorySubClass.c | 22 +- >> .../Smbios/MemorySubClassDxe/MemorySubClass.h | 2 - >> .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 27 +- >> .../Hisilicon/Hi1610/Include/PlatformArch.h | 69 + >> .../Hi1616/D05AcpiTables/Hi1616Platform.h | 24 +- >> .../Hisilicon/Hi1616/Include/PlatformArch.h | 69 + >> Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c | 92 + >> Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h | 48 + >> .../Hisilicon/Hi1620/Drivers/Apei/Apei.inf | 63 + >> .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c | 86 + >> .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h | 42 + >> .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c | 326 +++ >> .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h | 154 ++ >> .../Hi1620/Drivers/Apei/ErrorSource/Ghes.c | 320 +++ >> .../Hi1620/Drivers/Apei/ErrorSource/Ghes.h | 100 + >> .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c | 379 ++++ >> .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h | 145 ++ >> .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c | 98 + >> .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h | 58 + >> .../Hi1620/Drivers/Apei/OemApeiHi1620.c | 303 +++ >> .../Hi1620/Drivers/Apei/OemApeiHi1620.h | 28 + >> .../Pl011DebugSerialPortInitDxe.c | 64 + >> .../Pl011DebugSerialPortInitDxe.inf | 48 + >> .../Hi1620AcpiTables/AcpiTablesHi1620.inf | 59 + >> .../Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl | 409 ++++ >> .../Hi1620/Hi1620AcpiTables/Dsdt/Com.asl | 30 + >> .../Hi1620AcpiTables/Dsdt/DsdtHi1620.asl | 35 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Apei.asl | 93 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Ged.asl | 58 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl | 1459 ++++++++++++ >> .../Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl | 41 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 1216 ++++++++++ >> .../Hi1620AcpiTables/Dsdt/Hi1620Power.asl | 28 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Rde.asl | 47 + >> .../Hi1620AcpiTables/Dsdt/Hi1620Sec.asl | 57 + >> .../Dsdt/Hi1620Socip4_i2c100k.asl | 249 +++ >> .../Dsdt/Hi1620Socip4_i2c400k.asl | 249 +++ >> .../Hi1620AcpiTables/Dsdt/LpcUart_clk.asl | 49 + >> .../Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl | 1658 ++++++++++++++ >> .../Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl | 49 + >> .../Hi1620/Hi1620AcpiTables/Facs.aslc | 67 + >> .../Hi1620/Hi1620AcpiTables/Fadt.aslc | 91 + >> .../Hi1620/Hi1620AcpiTables/Gtdt.aslc | 86 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc | 86 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 1989 +++++++++++++++++ >> .../Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 1736 ++++++++++++++ >> .../Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc | 64 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Platform.h | 27 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc | 64 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc | 81 + >> .../Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc | 166 ++ >> .../Hi1620/Hi1620AcpiTables/MadtHi1620.aslc | 375 ++++ >> .../Hi1620OemConfigUiLib/MemoryConfig.hfr | 154 ++ >> .../Hi1620OemConfigUiLib/MemoryConfig.uni | 172 ++ >> .../Hi1620OemConfigUiLib/MiscConfig.hfr | 48 + >> .../Hi1620OemConfigUiLib/MiscConfig.uni | 36 + >> .../Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 380 ++++ >> .../Hi1620/Hi1620OemConfigUiLib/OemConfig.h | 141 ++ >> .../Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h | 64 + >> .../Hi1620OemConfigUiLib/OemConfigUiLib.inf | 67 + >> .../Hi1620OemConfigUiLib/OemConfigUiLib.uni | 24 + >> .../OemConfigUiLibStrings.uni | 64 + >> .../Hi1620OemConfigUiLib/OemConfigVfr.Vfr | 89 + >> .../Hi1620OemConfigUiLib/PcieConfig.hfr | 219 ++ >> .../PcieConfigStrings.uni | 185 ++ >> .../Hi1620OemConfigUiLib/PciePortConfig.hfr | 167 ++ >> .../Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr | 171 ++ >> .../Hi1620/Hi1620OemConfigUiLib/RasConfig.uni | 135 ++ >> .../Hi1620OemConfigUiLib/iBMCConfig.hfr | 80 + >> .../Hi1620OemConfigUiLib/iBMCConfig.uni | 49 + >> .../Hi1620/Include/Library/SerdesLib.h | 85 + >> .../Hisilicon/Hi1620/Include/PlatformArch.h | 68 + >> .../Hi1620PciPlatformLib.c | 69 + >> .../Hi1620PciPlatformLib.inf | 30 + >> Silicon/Hisilicon/Hi1620/Pptt/Pptt.c | 543 +++++ >> Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 69 + >> Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf | 48 + >> Silicon/Hisilicon/HisiPkg.dec | 2 + >> .../Hisilicon/Include/Library/AcpiNextLib.h | 31 +- >> .../Hisilicon/Include/Library/HwMemInitLib.h | 351 +-- >> .../Hisilicon/Include/Library/IpmiCmdLib.h | 16 + >> Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +- >> .../Include/Library/OemAddressMapLib.h | 6 + >> .../Hisilicon/Include/Library/OemConfigData.h | 85 + >> .../Hisilicon/Include/Library/OemMiscLib.h | 5 +- >> Silicon/Hisilicon/Include/Library/OemNicLib.h | 58 + >> .../Include/Library/PlatformSysCtrlLib.h | 8 + >> Silicon/Hisilicon/Include/PlatformArch.h | 35 - >> .../DS3231RealTimeClockLib.c | 8 +- >> Silicon/Hisilicon/Library/I2CLib/I2CHw.h | 4 + >> Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 220 +- >> .../PlatformBootManagerLib/PlatformBm.c | 65 + >> .../PlatformBootManagerLib.inf | 4 + >> 133 files changed, 21324 insertions(+), 573 deletions(-) >> create mode 100644 Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini >> create mode 100644 Platform/Hisilicon/D06/D06.dec >> create mode 100644 Platform/Hisilicon/D06/D06.dsc >> create mode 100644 Platform/Hisilicon/D06/D06.fdf >> create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h >> create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c >> create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf >> create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc >> create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf >> create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c >> create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c >> create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf >> create mode 100644 Platform/Hisilicon/D06/Include/Library/CpldD06.h >> create mode 100644 Platform/Hisilicon/D06/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h >> create mode 100644 Platform/Hisilicon/D06/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c >> create mode 100644 Platform/Hisilicon/D06/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf >> create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c >> create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni >> create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c >> create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf >> create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c >> create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf >> create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c >> create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf >> create mode 100644 Silicon/Hisilicon/Hi1610/Include/PlatformArch.h >> create mode 100644 Silicon/Hisilicon/Hi1616/Include/PlatformArch.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr >> create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni >> create mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Include/PlatformArch.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf >> create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.c >> create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.h >> create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf >> create mode 100644 Silicon/Hisilicon/Include/Library/OemConfigData.h >> create mode 100644 Silicon/Hisilicon/Include/Library/OemNicLib.h >> delete mode 100644 Silicon/Hisilicon/Include/PlatformArch.h >> >> -- >> 2.17.0 >>