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From: "Zhiguang Liu" <zhiguang.liu@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
	"Javeed, Ashraf" <ashraf.javeed@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>,
	"Gao, Liming" <liming.gao@intel.com>
Subject: Re: [edk2-devel] [PATCH V1] MdePkg-PciExpress40.h: DVSEC definition missing
Date: Tue, 17 Mar 2020 07:15:42 +0000	[thread overview]
Message-ID: <d08887f43e0e4cf496d3076e8c9d3c30@intel.com> (raw)
In-Reply-To: <95C5C2B113DE604FB208120C742E9824579C6A05@BGSMSX101.gar.corp.intel.com>

Hi Ashraf

I think the code change is good.
But you have put the code inside the below comment block, which is confusing.

/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
///@{
......
///@}

Maybe you can add another comment block to explain which the spec and section the code change is based on.

Thanks
Zhiguang

-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Javeed, Ashraf
Sent: Monday, March 16, 2020 1:35 PM
To: devel@edk2.groups.io; Javeed, Ashraf <ashraf.javeed@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: Re: [edk2-devel] [PATCH V1] MdePkg-PciExpress40.h: DVSEC definition missing

Patch uploaded in the BZ# 2598, and its code differences can be viewed in the following link:
https://bugzilla.tianocore.org/attachment.cgi?id=485&action=diff

Thanks
Ashraf

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Javeed, 
> Ashraf
> Sent: Sunday, March 15, 2020 10:01 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming 
> <liming.gao@intel.com>
> Subject: [edk2-devel] [PATCH V1] MdePkg-PciExpress40.h: DVSEC 
> definition missing
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
> 
> All registers definition of DVSEC are defined as per the PCI Express 
> Base Specification 4.0 chapter 7.9.6.
> 
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> ---
>  MdePkg/Include/IndustryStandard/PciExpress40.h | 24
> ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
> b/MdePkg/Include/IndustryStandard/PciExpress40.h
> index 9d9b272546..02c30a7757 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress40.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
> @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard.
>  This header file may not define all structures.  Please extend as required.
> 
>  Copyright (c) 2018, American Megatrends, Inc. All rights 
> reserved.<BR>
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>  **/
> @@ -76,6 +77,29 @@ typedef struct {
>    UINT32                                                        Reserved;
> 
> PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTRO
> L LaneEqualizationControl[1];  }
> PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
> +
> +typedef union {
> +  struct {
> +    UINT32 DvsecVendorId                                        : 16; //bit 0..15
> +    UINT32 DvsecRevision                                        : 4;  //bit 16..19
> +    UINT32 DvsecLength                                          : 12; //bit 20..31
> +  }Bits;
> +  UINT32                                                        Uint32;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
> +
> +typedef union {
> +  struct {
> +    UINT16 DvsecId                                              : 16; //bit 0..15
> +  }Bits;
> +  UINT16                                                        Uint16;
> +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
> +
> +typedef struct {
> +  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
> +  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1
> DesignatedVendorSpecificHeader1;
> +  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2
> DesignatedVendorSpecificHeader2;
> +  UINT8                                                         DesignatedVendorSpecific[1];
> +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
>  ///@}
> 
>  #pragma pack()
> --
> 2.21.0.windows.1
> 
> 
> 





  reply	other threads:[~2020-03-17  7:15 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <15FC874490F7A30A.28876@groups.io>
2020-03-16  5:34 ` [edk2-devel] [PATCH V1] MdePkg-PciExpress40.h: DVSEC definition missing Javeed, Ashraf
2020-03-17  7:15   ` Zhiguang Liu [this message]
2020-03-17  7:26     ` Javeed, Ashraf

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